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read buffer & last operation
This commit is contained in:
Piotr Jaczewski
parent
7de77dd557
commit
f05389366d
@ -2,7 +2,7 @@
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GAL20V8
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EQN2JED - Boolean Equations to JEDEC file assembler (Version V101)
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Copyright (c) National Semiconductor Corporation 1990-1993
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Assembled from "e:/APPLE1~1/ADDRES~1.EQN". Date: 5-24-120
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Assembled from "c:/APPLE1~1/ADDRES~1.EQN". Date: 6-7-120
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*
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NOTE PINS RW:2 A0:3 A1:4 A2:5 A3:6 A4:7 A5:8 A6:9 A7:10 A8:11*
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NOTE PINS GND:12 A9:14 A10:15 A11:16 SR:17 RD:18 WD:19 ROM:20*
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@ -19,7 +19,7 @@ L0640
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L0960
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1011011010011011101110111010101001101011*
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L1280
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0111101010011011101110111010101001101011*
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0111101010111011101110111010101001101011*
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L1600
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0111101010111011101110111010101010101011*
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L2560
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@ -30,5 +30,5 @@ L2640
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0000000010000000111100001000000010000000100000000000000000000000*
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L2704
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10*
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C1FC0*
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C1FC4*
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0000
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@ -7,7 +7,7 @@ R=23 VCC=24
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equations
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SR = /A0 * /A1 * /A2 * /A3 * /A4 * /A5 * /A6 * /A7 * /A8 * /A9 * /A10 * /A11 * /R * RW
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RD = /A0 * /A1 * /A2 * /A3 * /A4 * /A5 * /A6 * A7 * /A8 * /A9 * /A10 * /A11 * /R * RW * PHI
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RD = /A0 * /A1 * /A2 * /A3 * /A4 * /A5 * /A6 * A7 * /A8 * /A9 * /A10 * /A11 * /R * RW
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WD = A0 * /A1 * /A2 * /A3 * /A4 * /A5 * /A6 * A7 * /A8 * /A9 * /A10 * /A11 * /R * /RW * PHI
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/ROM = A8 * /R * RW
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+ A9 * /R * RW
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@ -21,6 +21,8 @@
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#define DATA6 PD3
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#define DATA7 PD4
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#define BUFFER_SIZE 8
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typedef enum {NONE, READ, WRITE} mode_t;
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mode_t mode = NONE;
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@ -31,6 +33,10 @@ uint8_t lower_part = 0x00;
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uint8_t data_write_interrupt_count = 0;
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uint8_t data_read_interrupt_count = 0;
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// receive buffer
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uint8_t receive_buffer[BUFFER_SIZE];
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int8_t receive_index = -1;
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// Registers: PCMSK0, PCMSK1, PCMSK2 :registers that enable or disable pin-change interrupts
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// on individual pins
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@ -46,38 +52,46 @@ inline void not_ready() {
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PORTD &= ~(_BV(STATUS));
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}
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void setup() {
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inline void put_data() {
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upper_part = (PORTD & 0xe3) | ((0xe0 & receive_buffer[0])>>3);
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lower_part = (PORTB & 0xc1) | ((0x1f & receive_buffer[0])<<1);
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PORTD = upper_part;
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PORTB = lower_part;
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}
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void setup() {
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// set input on DATA_READ_LINE
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DDRB &= ~(_BV(DATA_READ_LINE));
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// interrupt on DATA_READ_LINE change
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PCMSK0 |= _BV(PCINT0);
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PCICR |= _BV(PCIE0);
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// set input on DATA_WRITE_LINE
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DDRD &= ~(_BV(DATA_WRITE_LINE));
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// interrupt on DATA_WRITE_LINE change
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PCMSK2 |= _BV(PCINT23);
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PCICR |= _BV(PCIE2);
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UBRR0H = UBRRH_VALUE;
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UBRR0L = UBRRL_VALUE;
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UCSR0A = 0x00;
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UCSR0C = 0x00;
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// 8 bits of data, 1 stop bit, no parity
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UCSR0C = _BV(UCSZ00) | _BV(UCSZ01);
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// TXD pullup
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PORTD |= _BV(PD1);
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// interrupt on DATA_READ_LINE change
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PCMSK0 |= _BV(PCINT0);
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PCICR |= _BV(PCIE0);
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// set output on status
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DDRD |= _BV(STATUS);
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not_ready();
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// enable global interrupts
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sei();
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}
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@ -87,15 +101,34 @@ ISR(PCINT0_vect) {
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if (data_read_interrupt_count == 0) {
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if (mode != READ) {
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mode = READ;
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// enable RXD and it's interrupt
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UCSR0B = _BV(RXEN0) | _BV(RXCIE0);
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// set output on data pins
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DDRD |= _BV(DATA5) | _BV(DATA6) | _BV(DATA7);
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DDRB |= _BV(DATA0) | _BV(DATA1) | _BV(DATA2) | _BV(DATA3) | _BV(DATA4);
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receive_index = -1;
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not_ready();
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data_read_interrupt_count = 1;
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return;
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}
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if (receive_index > -1) {
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uint8_t i;
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for (i = 1; i <= receive_index; i++) {
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receive_buffer[i - 1] = receive_buffer[i];
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}
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receive_index--;
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if (receive_index == -1) {
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not_ready();
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} else {
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// put next byte from receive buffer
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put_data();
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}
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}
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not_ready();
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data_read_interrupt_count = 1;
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} else {
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data_read_interrupt_count = 0;
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@ -106,18 +139,18 @@ ISR(PCINT0_vect) {
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ISR(PCINT2_vect) {
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upper_part = PINB;
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lower_part = PIND;
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if (data_write_interrupt_count == 0) {
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if (mode == WRITE) {
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upper_part = upper_part >> 1;
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upper_part &= 0x1f;
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lower_part = lower_part << 3;
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lower_part &= 0xe0;
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// set status to not ready
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PORTD &= ~(_BV(STATUS));
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// send byte
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loop_until_bit_is_set(UCSR0A, UDRE0);
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UDR0 = upper_part | lower_part;
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@ -128,14 +161,14 @@ ISR(PCINT2_vect) {
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PORTB &= 0xc1;
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}
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mode = WRITE;
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// enable TXD interrupt and it's interrupt
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UCSR0B = _BV(TXEN0) | _BV(TXCIE0);
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// set input on data pins
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DDRD &= ~(_BV(DATA5) | _BV(DATA6) | _BV(DATA7));
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DDRB &= ~(_BV(DATA0) | _BV(DATA1) | _BV(DATA2) | _BV(DATA3) | _BV(DATA4));
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ready();
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}
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data_write_interrupt_count = 1;
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@ -149,11 +182,14 @@ ISR(USART_RX_vect)
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if (mode == READ) {
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data = UDR0;
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upper_part = (PORTD & 0xe3) | ((0xe0 & data)>>3);
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lower_part = (PORTB & 0xc1) | ((0x1f & data)<<1);
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if (receive_index >= BUFFER_SIZE - 1) {
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receive_index = -1;
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}
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PORTD = upper_part;
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PORTB = lower_part;
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receive_buffer[++receive_index] = data;
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// always put first byte from receive buffer
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put_data();
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ready();
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}
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@ -168,10 +204,9 @@ ISR(USART_TX_vect)
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int main(void) {
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setup();
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for(;;){
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// only interrupt driven
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}
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return 0; /* never reached */
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}
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@ -1,10 +1,15 @@
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;End address of dump block
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#define hex1_l $50
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#define hex1_h $51
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#define hex1_l $24
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#define hex1_h $25
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;Begin address of dump block
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#define hex2_l $52
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#define hex2_h $53
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#define hex2_l $26
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#define hex2_h $27
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#define last_command $28
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#define last_command_none $00
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#define last_command_read $01
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#define last_command_write $02
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;Input buffer
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#define input $0200
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@ -44,6 +49,8 @@ apple_serial
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jsr echo
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lda #CR ;And drop the cursor one line
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jsr echo
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lda #$00 ;Set last command type to NONE
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sta last_command
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ldy #$FF ;Reset the input buffer index
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next_char
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@ -133,28 +140,16 @@ separator
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sta hex1_h
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jmp next_chr
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reset
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txa
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pha
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lda serial_reset
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ldx #$00
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ldy #$00
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reset_loop ; ((2 + 2 + 3) * 255 + 2 + 3) * 255 =
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nop ; 2 cycles
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iny ; 2 cycles
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bne reset_loop ; 3 cycles
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inx ; 2 cycles
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bne reset_loop ; 3 cycles
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pla
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tax
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rts
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;-------------------------------------------------------------------------
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; Read procedure
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;-------------------------------------------------------------------------
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read
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lda last_command
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cmp #last_command_read
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beq read_ready
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lda serial_read ;Enable read mode, this can be done quick, without reset
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read_ready
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ldy #$00
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read_byte
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@ -171,6 +166,8 @@ read_byte
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cmp hex1_h ;Compare upper destination address half with upper end address half
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bne read_next ;If not equal then proceed to read next byte
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lda last_command_read ;Set last command to READ
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sta last_command
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jmp next_cmd ;Read is completed, proceed to next command
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read_next
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@ -187,10 +184,14 @@ read_next
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;-------------------------------------------------------------------------
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write
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lda last_command
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cmp #last_command_write
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beq write_ready
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jsr reset ;Reset serial and give some time to stabilize
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;This is required due to inability to guess what is the current device mode
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;and prevents from polluting the output while setting the write mode
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sta serial_write ;Enable write mode
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write_ready
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ldy #$00
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write_byte
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@ -207,6 +208,8 @@ write_byte
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cmp hex1_h ;Compare upper source address half with upper end address half
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bne write_next ;If not equal then proceed to write next byte
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lda last_command_write ;Set last command to WRITE
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sta last_command
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jmp next_cmd ;Write is completed, proceed to next command
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write_next
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@ -222,6 +225,30 @@ write_next
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; tool routines
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;-------------------------------------------------------------------------
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reset
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txa ;Preserve X on stack
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pha
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tya ;Preserve Y on stack
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pha
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lda serial_reset ;Reset
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ldx #$00
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ldy #$00
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reset_loop ; ~((2 + 2 + 3) * 255 + 2 + 3) * 255 =
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nop ; 2 cycles
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iny ; 2 cycles
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bne reset_loop ; 3 cycles
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inx ; 2 cycles
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bne reset_loop ; 3 cycles
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pla ;Restore Y from stack
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tay
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pla ;Restore X from stack
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tax
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rts
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increment_16bit
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inc $00,X
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bne increment_16bit_done
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31
src/tests.xa
31
src/tests.xa
@ -5,12 +5,12 @@
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#define serial_read $C080
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#define serial_write $C081
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* = $C200
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* = $C300
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.dsb (*-end_of_apple1serial), 0
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; teletype on apple-1
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* = $C200
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teletype_apple1 = $C200
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* = $C300
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teletype_apple1 = $C300
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lda serial_read
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wait
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lda serial_ready
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@ -20,16 +20,12 @@ wait
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jmp wait
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end_of_teletype_apple1
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; AD 80 C0 AD 00 C0 F0 FB
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; AD 80 C0 20 EF FF 4C 03
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; 00
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; teletype on remote
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* = $C300
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* = $C400
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.dsb (*-end_of_teletype_apple1), 0
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* = $C300
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teletype_remote = $C300
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* = $C400
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teletype_remote = $C400
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lda #$FF
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sta serial_write
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get_key
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@ -42,16 +38,12 @@ get_key
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jmp get_key
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end_of_teletype_remote
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; A9 FF 8D 81 C0 AD 11 D0
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; 10 FB AD 10 D0 38 E9 A0
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; 8D 81 C0 4C 85 02
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; 0-255 repeating counter over TXD
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* = $C400
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* = $C500
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.dsb (*-end_of_teletype_remote), 0
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* = $C400
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counter_remote = $C400
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* = $C500
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counter_remote = $C500
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ldy #$00
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sta serial_write
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check_ready
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@ -61,7 +53,4 @@ check_ready
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sta serial_write
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iny
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jmp check_ready
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; A0 00 8D 81 C0 AD 00 C0
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; F0 FB 98 8D 81 C0 C8 4C
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; 85 02
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