Apple-1-HW/verilog-apple-one
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fixed conflicts

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This commit is contained in:
Niels Moseley 2018-02-11 22:53:30 +01:00
commit 29b42f8e1f
18 changed files with 250 additions and 8 deletions
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4
boards/README.md
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@ -2,7 +2,7 @@
The directory structure for board should follow the following convention:
/boards/[target_board_name]/[build_env]
`/boards/[target_board_name]/[build_env]`
### target_board_name
Choose a target/board name that uniquely identifies the board, including required extension boards. For example: <b>UPDuino_v1</b> or <b>Terasic_DE0</b>
@ -15,4 +15,4 @@ Choose a build_env name that uniquely identifies the development environment, su
### README.md
For each project, a README.md file should be present describing the hardware setup, the build environment and, if needed, the pinout used. Also include contact information of the maintainer.
Photos are a plus.
Photos are a plus.

2
boards/ice40hx8k-b-evn/yosys/Makefile
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@ -1,7 +1,7 @@
DEVICE = hx8k
PIN_DEF=ice40hx8k.pcf
SOURCEDIR = ../../rtl
SOURCEDIR = ../../../rtl
BUILDDIR = build
all: apple1 prog

10
boards/tinyfpga_b2/README.md Normal file
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@ -0,0 +1,10 @@
# TinyFPGA B2 support
This adds support for building apple one design for [TinyFPGA B2 board](http://tinyfpga.com/b-series-guide.html) on [TinyFPGA Computer Project Board](https://hackaday.io/project/29526-tinyfpga-computer-project-board) used for VGA and PS2
## Building
Install a recent IceStorm toolchain, and:
make
Since programming here is done with custom tool it is important to have tinyfpgab installed.

29
boards/tinyfpga_b2/tinyfpga.pcf Normal file
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@ -0,0 +1,29 @@
# For the TinyFPGA Computer Project Board
### left side of board
#set_io --warn-no-port pin1_usb_dp A3
#set_io --warn-no-port pin2_usb_dn A4
set_io --warn-no-port pin3_clk_16mhz B4
set_io --warn-no-port pin4 B2
set_io --warn-no-port pin5 A2
set_io --warn-no-port pin6 A1
set_io --warn-no-port pin7 B1
#set_io --warn-no-port pin8 C1
#set_io --warn-no-port pin9 D1
#set_io --warn-no-port pin10 E1
set_io --warn-no-port pin11 G1
set_io --warn-no-port pin12 H1
set_io --warn-no-port pin13 J1
### right side of board
#set_io --warn-no-port pin14_sdo G6
#set_io --warn-no-port pin15_sdi H7
#set_io --warn-no-port pin16_sck G7
#set_io --warn-no-port pin17_ss F7
#set_io --warn-no-port pin18 D9
set_io --warn-no-port pin19 C9
set_io --warn-no-port pin20 E8
set_io --warn-no-port pin21 A9
set_io --warn-no-port pin22 A8
set_io --warn-no-port pin23 A7
set_io --warn-no-port pin24 A6

72
boards/tinyfpga_b2/yosys/Makefile Normal file
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@ -0,0 +1,72 @@
DEVICE = lp8k
PIN_DEF=tinyfpga.pcf
SOURCEDIR = ../../rtl
BUILDDIR = build
all: apple1 prog
info:
@echo " To build: make apple1"
@echo " To program: make prog"
@echo "To build report: make report"
@echo " To clean up: make clean"
dir:
mkdir -p $(BUILDDIR)
# ------ TEMPLATES ------
$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^
$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
arachne-pnr -d 8k -P cm81 -o $@ -p $^
$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
icepack $^ $@
%.rpt: $(BUILDDIR)/%.asc
icetime -d $(DEVICE) -mtr $@ $<
%_tb.vvp: %_tb.v %.v
iverilog -o $@ $^
%_tb.vcd: %_tb.vvp
vvp -N $< +vcd=$@
# ------ APPLE 1 ------
apple1: dir $(BUILDDIR)/apple1.bin
report: dir apple1.rpt
$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
$(SOURCEDIR)/clock.v \
$(SOURCEDIR)/pwr_reset.v \
$(SOURCEDIR)/ram.v \
$(SOURCEDIR)/rom_wozmon.v \
$(SOURCEDIR)/rom_basic.v \
$(SOURCEDIR)/cpu/arlet_6502.v \
$(SOURCEDIR)/cpu/arlet/ALU.v \
$(SOURCEDIR)/cpu/arlet/cpu.v \
$(SOURCEDIR)/uart/uart.v \
$(SOURCEDIR)/uart/async_tx_rx.v \
$(SOURCEDIR)/vga/vga.v \
$(SOURCEDIR)/vga/vram.v \
$(SOURCEDIR)/vga/font_rom.v \
$(SOURCEDIR)/ps2keyboard/debounce.v \
$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
clock_pll.v \
apple1_hx8k.v
apple1.rpt: $(BUILDDIR)/apple1.asc
prog: dir $(BUILDDIR)/apple1.bin
tinyfpgab -p $(filter-out $<,$^)
# ------ HELPERS ------
clean:
rm -rf build apple1.rpt
.SECONDARY:
.PHONY: all info clean prog iceprog

1
boards/tinyfpga_b2/yosys/tinyfpga.pcf Symbolic link
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@ -0,0 +1 @@
../tinyfpga.pcf

0
rtl/boards/ice40hx8k/apple1_hx8k.v → rtl/boards/ice40hx8k-b-evn/apple1_hx8k.v
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0
rtl/boards/ice40hx8k/clock_pll.v → rtl/boards/ice40hx8k-b-evn/clock_pll.v
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0
rtl/boards/ice40hx8k/clock_pll_inst.v → rtl/boards/ice40hx8k-b-evn/clock_pll_inst.v
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0
rtl/boards/ice40hx8k/clock_pll_v.lpc → rtl/boards/ice40hx8k-b-evn/clock_pll_v.lpc
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92
rtl/boards/tinyfpga_b2/apple1_hx8k.v Normal file
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@ -0,0 +1,92 @@
// Licensed to the Apache Software Foundation (ASF) under one
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
// to you under the Apache License, Version 2.0 (the
// "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// software distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//
// Description: Apple 1 implementation for the iCE40HX8K dev
// board.
//
// Author.....: Miodrag Milanovic
// Date.......: 11-2-2018
//
module apple1_top(
input pin3_clk_16mhz,// 16 MHz board clock
// Outputs to VGA display
output pin4, // hozizontal VGA sync pulse
output pin5, // vertical VGA sync pulse
input pin6, // PS/2 data input
input pin7, // PS/2 clock
// I/O interface to computer
input pin11, // asynchronous serial data input from computer
output pin12, // asynchronous serial data output to computer
output pin13, // clear to send flag to computer
output reg pin24, // red VGA signal
output reg pin23, // red VGA signal
output reg pin22, // green VGA signal
output reg pin21, // green VGA signal
output reg pin20, // blue VGA signal
output reg pin19 // blue VGA signal
);
wire clk25;
// 16MHz up to 25MHz
clock_pll clock_pll_inst(
.REFERENCECLK(pin3_clk_16mhz),
.PLLOUTGLOBAL(clk25),
.RESET(1'b1)
);
wire [15:0] pc_monitor;
reg [1:0] button = 2'b01;
wire vga_red;
wire vga_grn;
wire vga_blu;
// apple one main system
apple1 my_apple1(
.clk25(clk25),
.rst_n(button[0]),
.ps2_clk(pin7), // PS/2 not working with my keyboard
.ps2_din(pin6),
.ps2_select(1'b0), // change to 1 in order to test with keyboard
.uart_rx(pin11),
.uart_tx(pin12),
.uart_cts(pin13),
.clr_screen_btn(button[1]),
.vga_h_sync(pin4),
.vga_v_sync(pin5),
.vga_red(vga_red),
.vga_grn(vga_grn),
.vga_blu(vga_blu),
.pc_monitor(pc_monitor)
);
assign pin19 = vga_blu;
assign pin20 = vga_blu;
assign pin21 = vga_grn;
assign pin22 = vga_grn;
assign pin23 = vga_red;
assign pin24 = vga_red;
endmodule

38
rtl/boards/tinyfpga_b2/clock_pll.v Normal file
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module clock_pll(REFERENCECLK,
PLLOUTCORE,
PLLOUTGLOBAL,
RESET);
input REFERENCECLK;
input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
output PLLOUTCORE;
output PLLOUTGLOBAL;
SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
.PLLOUTCORE(PLLOUTCORE),
.PLLOUTGLOBAL(PLLOUTGLOBAL),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(RESET),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(),
.SDI(),
.SDO(),
.SCLK());
//\\ Fin=16, Fout=25;
defparam clock_pll_inst.DIVR = 4'b0000;
defparam clock_pll_inst.DIVF = 7'b0110001;
defparam clock_pll_inst.DIVQ = 3'b101;
defparam clock_pll_inst.FILTER_RANGE = 3'b001;
defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
endmodule

0
rtl/boards/ice40up5k/apple1_up5k.v → rtl/boards/upduino/apple1_up5k.v
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2
rtl/ram.v
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@ -31,7 +31,7 @@ module ram(
);
`ifdef SIM
parameter RAM_FILENAME = "../../roms/ram.hex";
parameter RAM_FILENAME = "../roms/ram.hex";
`else
parameter RAM_FILENAME = "../../../roms/ram.hex";
`endif

2
rtl/rom_basic.v
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@ -29,7 +29,7 @@ module rom_basic(
);
`ifdef SIM
parameter BASIC_FILENAME = "../../roms/basic.hex";
parameter BASIC_FILENAME = "../roms/basic.hex";
`else
parameter BASIC_FILENAME = "../../../roms/basic.hex";
`endif

2
rtl/rom_wozmon.v
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@ -29,7 +29,7 @@ module rom_wozmon(
);
`ifdef SIM
parameter ROM_FILENAME = "../../roms/wozmon.hex";
parameter ROM_FILENAME = "../roms/wozmon.hex";
`else
parameter ROM_FILENAME = "../../../roms/wozmon.hex";
`endif

2
rtl/vga/font_rom.v
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@ -34,7 +34,7 @@ module font_rom(
);
`ifdef SIM
parameter ROM_FILENAME = "../../roms/vga_font_bitreversed.hex";
parameter ROM_FILENAME = "../roms/vga_font_bitreversed.hex";
`else
parameter ROM_FILENAME = "../../../roms/vga_font_bitreversed.hex";
`endif

2
rtl/vga/vram.v
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@ -33,7 +33,7 @@ module vram(
);
`ifdef SIM
parameter RAM_FILENAME = "../../roms/vga_vram.bin";
parameter RAM_FILENAME = "../roms/vga_vram.bin";
`else
parameter RAM_FILENAME = "../../../roms/vga_vram.bin";
`endif