Apple-1-HW/verilog-apple-one
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Fixed issue with yosys compile

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This commit is contained in:
Alan Garfield 2018-02-05 00:24:12 +11:00
parent 20919fa726
commit 7b3c65b8d9
4 changed files with 7 additions and 17 deletions
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1
boards/ice40hx8k_yosys/Makefile
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@ -53,6 +53,7 @@ $(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
$(SOURCEDIR)/uart/async_tx_rx.v \
$(SOURCEDIR)/vga/vga.v \
$(SOURCEDIR)/vga/vram.v \
$(SOURCEDIR)/vga/font_rom.v \
$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
$(SOURCEDIR)/boards/ice40hx8k/clock_pll.v \
$(SOURCEDIR)/boards/ice40hx8k/apple1_hx8k.v

8
rtl/apple1.v
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@ -90,8 +90,8 @@ module apple1(
.we (we),
.irq_n (1'b1),
.nmi_n (1'b1),
.ready (cpu_clken)
//.pc_monitor (pc_monitor)
.ready (cpu_clken),
.pc_monitor (pc_monitor)
);
//////////////////////////////////////////////////////////////////////////
@ -198,9 +198,7 @@ module apple1(
.w_en(we & vga_cs),
.din(dbo),
.clr_screen_btn(clr_screen_btn),
.blink_clken(blink_clken),
.debug(pc_monitor)
.blink_clken(blink_clken)
);
//////////////////////////////////////////////////////////////////////////

1
rtl/vga/vga.v
View File

@ -114,7 +114,6 @@ module vga(
vram my_vram(
.clk(clk25),
.rst(rst),
.read_addr(vram_r_addr),
.write_addr(vram_w_addr),
.r_en(h_active),

12
rtl/vga/vram.v
View File

@ -24,7 +24,6 @@
module vram(
input clk, // clock signal
input rst, //
input [9:0] read_addr, // read address bus
input [9:0] write_addr, // write address bus
input r_en, // active high read enable strobe
@ -44,17 +43,10 @@ module vram(
initial
$readmemb(RAM_FILENAME, ram_data, 0, 1023);
always @(posedge clk or posedge rst )
always @(posedge clk)
begin
if (rst)
dout <= 0;
else
begin
//if (r_en) dout <= ram_data[read_addr];
dout <= ram_data[read_addr];
if (r_en) dout <= ram_data[read_addr];
if (w_en) ram_data[write_addr] <= din;
end
end
endmodule