Merge pull request #11 from ironsteel/master
Support for Olimex iCE40HX8K-EVB fpga board
This commit is contained in:
Alan Garfield
GitHub
commit
7ef0df07da
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DEVICE = hx8k
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PIN_DEF=ice40hx8k.pcf
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SOURCEDIR = ../../rtl
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BUILDDIR = build
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all: apple1 prog
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info:
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@echo " To build: make apple1"
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@echo " To program: make prog"
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@echo "To build report: make report"
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@echo " To clean up: make clean"
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dir:
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mkdir -p $(BUILDDIR)
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# ------ TEMPLATES ------
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$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
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yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif $@" $^
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$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
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arachne-pnr -d $(subst hx,,$(subst lp,,$(DEVICE))) -o $@ -p $^
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$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
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icepack $^ $@
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%.rpt: $(BUILDDIR)/%.asc
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icetime -d $(DEVICE) -mtr $@ $<
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%_tb.vvp: %_tb.v %.v
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iverilog -o $@ $^
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%_tb.vcd: %_tb.vvp
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vvp -N $< +vcd=$@
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# ------ APPLE 1 ------
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apple1: dir $(BUILDDIR)/apple1.bin
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report: dir apple1.rpt
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$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
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$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
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$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
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$(SOURCEDIR)/clock.v \
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$(SOURCEDIR)/pwr_reset.v \
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$(SOURCEDIR)/ram.v \
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$(SOURCEDIR)/rom_wozmon.v \
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$(SOURCEDIR)/rom_basic.v \
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$(SOURCEDIR)/cpu/arlet_6502.v \
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$(SOURCEDIR)/cpu/arlet/ALU.v \
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$(SOURCEDIR)/cpu/arlet/cpu.v \
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$(SOURCEDIR)/uart/uart.v \
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$(SOURCEDIR)/uart/async_tx_rx.v \
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$(SOURCEDIR)/vga/vga.v \
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$(SOURCEDIR)/vga/vram.v \
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$(SOURCEDIR)/vga/font_rom.v \
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$(SOURCEDIR)/ps2keyboard/debounce.v \
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$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
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$(SOURCEDIR)/boards/olimex_ice40hx8k/pll.v \
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$(SOURCEDIR)/boards/olimex_ice40hx8k/apple1_hx8k.v
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apple1.rpt: $(BUILDDIR)/apple1.asc
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prog: dir $(BUILDDIR)/apple1.bin
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iceprogduino $(filter-out $<,$^)
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# ------ HELPERS ------
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clean:
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rm -rf build apple1.rpt
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.SECONDARY:
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.PHONY: all info clean prog iceprog
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# Olimex iCE40hx8k-evb support
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This adds support for building apple one design for [Olimex iCE40hx8k-evb board](https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/open-source-hardware) with attached [Olimex iCE40-IO extension](https://www.olimex.com/Products/FPGA/iCE40/iCE40-IO/open-source-hardware) for vga and ps2
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## Peripheral support
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VGA port is working trought the iCE40-IO expansion.
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A usb-serial converter can be attached on pins 5(RX), 7(TX), 9(CTS) on either the iCE40-IO extension or witout it directly to the header of the FPGA board (pin out is the same). Consult the schematics for [iCE40-IO](https://github.com/OLIMEX/iCE40-IO/raw/master/ICE40-IO_Rev_A.pdf) and [iCE40HX8K-EVB](https://github.com/OLIMEX/iCE40HX8K-EVB/blob/master/HARDWARE/REV-B/iCE40HX8K-EVB_Rev_B.pdf) for extension header pinmap.
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The iCE40-IO board has a ps2 connector you can use if you have a ps2 keyboard but it's not edded to the design pin map.
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This port is using 1 PLL for generating the target 25Mhz clock.
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## Building
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Install a recent IceStorm toolchain, and:
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make
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## Use
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There are 2 possible ways for flashing the board:
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1. [Olimex OLIMEXINO-32U4 as programmer](https://www.olimex.com/wiki/ICE40HX1K-EVB#Preparing_OLIMEXINO-32U4_as_programmer)
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2. [Iceprog with Raspberry PI](https://www.olimex.com/wiki/ICE40HX1K-EVB#Iceprog_with_Raspberry_PI)
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To load BASIC type "E000R" with CAPS LOCK on.
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# For the olimex-iCE40HX8K-EVB
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# plus iCE40-IO expansion board with vga and ps2
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## System Clock 100Mhz
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set_io clk J3
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### UART
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set_io uart_rx E4
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set_io uart_tx B2
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set_io uart_cts F5
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set_io button[0] K11
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set_io button[1] P13
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### VGA Display
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set_io vga_v_sync H2
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set_io vga_h_sync J4
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set_io vga_r[0] E3
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set_io vga_r[1] H5
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set_io vga_r[2] F3
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set_io vga_g[0] H3
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set_io vga_g[1] F2
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set_io vga_g[2] H6
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set_io vga_b[0] F1
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set_io vga_b[1] H4
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set_io vga_b[2] G2
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@ -0,0 +1,69 @@
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Apple 1 implementation for the iCE40HX8K dev
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// board.
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//
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// Author.....: Alan Garfield
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// Date.......: 26-1-2018
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//
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module apple1_top(
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input clk, // 100 MHz board clock
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// I/O interface to computer
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input uart_rx, // asynchronous serial data input from computer
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output uart_tx, // asynchronous serial data output to computer
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output uart_cts, // clear to send flag to computer
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// Outputs to VGA display
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output vga_h_sync, // hozizontal VGA sync pulse
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output vga_v_sync, // vertical VGA sync pulse
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output [2:0] vga_r, // red VGA signal
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output [2:0] vga_g, // green VGA signal
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output [2:0] vga_b, // blue VGA signal
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input [1:0] button
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);
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wire clk25;
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pll pll(.clock_in(clk),
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.clock_out(clk25),
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);
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wire vga_bit;
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// set the monochrome base colour here..
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assign vga_r[2:0] = vga_bit ? 3'b100 : 3'b000;
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assign vga_g[2:0] = vga_bit ? 3'b111 : 3'b000;
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assign vga_b[2:0] = vga_bit ? 3'b100 : 3'b000;
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// apple one main system
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apple1 my_apple1(
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.clk25(clk25),
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.rst_n(button[0]),
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.uart_rx(uart_rx),
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.uart_tx(uart_tx),
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.uart_cts(uart_cts),
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.clr_screen_btn(0),
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.vga_h_sync(vga_h_sync),
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.vga_v_sync(vga_v_sync),
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.vga_red(vga_bit),
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.ps2_select(1'b0),
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);
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endmodule
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/**
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* PLL configuration
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*
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* This Verilog module was generated automatically
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* using the icepll tool from the IceStorm project.
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* Use at your own risk.
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*
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* Given input frequency: 100.000 MHz
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* Requested output frequency: 25.000 MHz
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* Achieved output frequency: 25.000 MHz
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*/
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module pll(
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input clock_in,
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output clock_out,
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output locked
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);
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000), // DIVR = 0
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.DIVF(7'b0000111), // DIVF = 7
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.DIVQ(3'b101), // DIVQ = 5
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.FILTER_RANGE(3'b101) // FILTER_RANGE = 5
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) uut (
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.LOCK(locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clock_in),
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.PLLOUTCORE(clock_out)
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);
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endmodule
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