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34 lines
679 B
Verilog
34 lines
679 B
Verilog
/**
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* PLL configuration
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*
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* This Verilog module was generated automatically
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* using the icepll tool from the IceStorm project.
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* Use at your own risk.
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*
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* Given input frequency: 100.000 MHz
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* Requested output frequency: 25.000 MHz
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* Achieved output frequency: 25.000 MHz
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*/
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module pll(
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input clock_in,
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output clock_out,
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output locked
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);
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'b0000), // DIVR = 0
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.DIVF(7'b0000111), // DIVF = 7
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.DIVQ(3'b101), // DIVQ = 5
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.FILTER_RANGE(3'b101) // FILTER_RANGE = 5
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) uut (
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.LOCK(locked),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(clock_in),
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.PLLOUTCORE(clock_out)
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);
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endmodule
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