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added missing DE0 top level
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rtl/boards/terasic_de0/apple1_de0_top.v
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54
rtl/boards/terasic_de0/apple1_de0_top.v
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// Licensed to the Apache Software Foundation (ASF) under one
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// or more contributor license agreements. See the NOTICE file
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// distributed with this work for additional information
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// regarding copyright ownership. The ASF licenses this file
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// to you under the Apache License, Version 2.0 (the
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// "License"); you may not use this file except in compliance
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// with the License. You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing,
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// software distributed under the License is distributed on an
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// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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// KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations
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// under the License.
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//
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// Description: Top level Apple 1 module for Terasic DE0 board
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//
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// Author.....: Niels A. Moseley
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// Date.......: 26-1-2018
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//
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module apple1_de0_top(
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input CLOCK_50, // the 50 MHz DE0 master clock
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// UART I/O signals
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output UART_TXD, // UART transmit pin on DE0 board
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input UART_RXD, // UART receive pin on DE0 board
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output UART_CTS // UART clear-to-send pin on DE0 board
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);
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//////////////////////////////////////////////////////////////////////////
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// Registers and Wires
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reg clk25;
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// generate 25MHz clock from 50MHz master clock
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always @(posedge CLOCK_50)
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begin
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clk25 <= ~clk25;
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end
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//////////////////////////////////////////////////////////////////////////
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// Core of system
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top core_top(
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.clk25(clk25),
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.rst_n(1'b1), // we don't have any reset pulse..
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.uart_rx(UART_RXD),
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.uart_tx(UART_TXD),
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.uart_cts(UART_CTS)
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);
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endmodule
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