Apple-1-HW
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verilog-apple-one
mirror of https://github.com/alangarf/apple-one.git
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Remove invalid port clr_screen_btn (as I don't see any other references to it in the repo) 

yosys -q -p "chparam -list; hierarchy -top apple1_top; synth_ice40 -blif build/apple1.blif" ../../../rtl/apple1.v build/pll.sv ../../../rtl/clock.v ../../../rtl/pwr_reset.v ../../../rtl/ram.v ../../../rtl/rom_wozmon.v ../../../rtl/rom_basic.v ../../../rtl/cpu/arlet_6502.v ../../../rtl/cpu/arlet/ALU.v ../../../rtl/cpu/arlet/cpu.v ../../../rtl/uart/uart.v ../../../rtl/uart/async_tx_rx.v ../../../rtl/vga/vga.v ../../../rtl/vga/vram.v ../../../rtl/vga/font_rom.v ../../../rtl/ps2keyboard/debounce.v ../../../rtl/ps2keyboard/ps2keyboard.v ../../../rtl/boards/upduino/apple1_up5k.v
Warning: Replacing memory \AXYS with list of registers. See ../../../rtl/cpu/arlet/cpu.v:541
ERROR: Module `$paramod$e7b6f8008bbd43376eeb102f607da77667371076\apple1' referenced in module `apple1_top' in cell `my_apple1' does not have a port named 'clr_screen_btn'.
Makefile:26: recipe for target 'build/apple1.blif' failed
make: *** [build/apple1.blif] Error 1
This commit is contained in:
Steve White 2018-05-05 12:59:52 -07:00
parent 59bbb91a8d
commit f4a450f022
1 changed files with 0 additions and 1 deletions
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1
rtl/boards/upduino/apple1_up5k.v
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@ -79,7 +79,6 @@ module apple1_top #(
.uart_rx(uart_rx),
.uart_tx(uart_tx),
.uart_cts(uart_cts),
.clr_screen_btn(1'b0),
.vga_h_sync(vga_h_sync),
.vga_v_sync(vga_v_sync),
.vga_red(vga_red),