Merge aea51dc240 into 0ebf86427b

README.md

@@ -9,14 +9,14 @@ Contributor supported boards (YMMV):
 - [Blackice II](https://www.tindie.com/products/Folknology/blackice-ii/)
 - [icoBoard](http://icoboard.org/)
 - [Olimex iCE40HX8K with ICE40-IO](https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/open-source-hardware)
-- [TinyFPGA B2](http://tinyfpga.com/)
-- [Upduino](http://gnarlygrey.atspace.cc/development-platform.html)
+- TinyFPGA B2
+- Upduino
 
 <p align="center">
  <img src="media/apple-one.png" alt="Apple One Running">
 </p>
 
-This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project and [Arlet Otten's](https://github.com/Arlet/verilog-6502) tiny 6502 core. Also many special thanks to [sbprojects.com](https://www.sbprojects.net/projects/apple1/index.php) for the wealth of information I gleaned from there.
+This project borrows heavily from the *awesome* work of Andrew Holme and his ["Pool"](http://www.aholme.co.uk/6502/Main.htm) project and [Arlet Otten's](https://github.com/Arlet/verilog-6502) tiny 6502 core. Also many special thanks to [sbprojects.net](https://www.sbprojects.net/projects/apple1/index.php) for the wealth of information I gleaned from there.
 
 ## Memory Map
  
@@ -45,11 +45,13 @@ $ make
 ```
 
 ### Board READMEs
-- [iCE40HX8K-B-EVN breakout](boards/ice40hx8k-b-evn/README.md)
-- [Terasic DE0](boards/terasic_de0/README.md)
-- [Digilent Spartan-3E Starter Board](boards/spartan3e_starterkit/README.md)
 - [Blackice II](boards/blackice2/README.md)
+- [iCE40HX8K-B-EVN breakout](boards/ice40hx8k-b-evn/README.md)
+- [iCE40UpDEvBoard](boards/ice40updevboard/README.md)
+- [icoBoard](boards/icoboard)
 - [Olimex iCE40HX8K with ICE40-IO](boards/olimex_ice40hx8k_evb_ice40-io/README.md)
+- [Digilent Spartan-3E Starter Board](boards/spartan3e_starterkit/README.md)
+- [Terasic DE0](boards/terasic_de0/README.md)
 - [TinyFPGA B2](boards/tinyfpga_b2/README.md)
 - [Upduino](boards/upduino/README.md)
 
@@ -71,7 +73,6 @@ Depending on the board you can use serial to communicate with the Apple 1, some
  
 A very basic hardware flow control is implemented. You should turn on CTS support as this will allow you to cut and paste code into the Woz Mon without the Apple 1 missing any bytes.
 
- 
 ## VGA / PS/2 Setup
  
 Most boards support PS/2 input and VGA output. This is the most support method, however all output is replicated to the UART (if available) and the PS/2 keyboard input can be replaced with the UART out if the "toggle" mode buttons is selected.
@@ -104,6 +105,6 @@ These controls are mapped to memory locations you can tweak using WozMon and are
  
 ## Helping
  
-All PRs and suggestions happily accepted! Please any support us most welcome, and it would be good to have this as feature complete as possible with the real Apple1. I'd like to implement the cassette interface next with the basic electronics to talk to the headphone/mic jack of a mobile phone to upload and download recordings as a means to save programs.
+All PRs and suggestions happily accepted! Please, any support us most welcome. It would be good to have this Apple 1 as feature complete as possible with the real Apple 1. I'd like to implement the cassette interface with the basic electronics to talk to the headphone/mic jack of a mobile phone to upload and download recordings as a means to save programs.
  
 But yes, help happily accepted!

boards/tinyfpga_bx/icecube2/icecube2_sbt.project

@@ -0,0 +1,88 @@
+[Project]
+ProjectVersion=2.0
+Version=Lattice Semiconductor Corporation iCEcube - Release: 2017.08.27940 - Build Date: Sep 11 2017 17:40:01
+ProjectName=icecube2
+Vendor=SiliconBlue
+Synthesis=synplify
+ProjectVFiles=../../../../rtl/apple1.v,../../../../rtl/clock.v,../../../../rtl/pwr_reset.v,../../../../rtl/ram.v,../../../../rtl/rom_basic.v,../../../../rtl/rom_wozmon.v,../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v,../../../../rtl/boards/tinyfpga_bx/clock_pll.v,../../../../rtl/cpu/arlet_6502.v,../../../../rtl/cpu/arlet/ALU.v,../../../../rtl/cpu/arlet/cpu.v,../../../../rtl/ps2keyboard/debounce.v,../../../../rtl/ps2keyboard/ps2keyboard.v,../../../../rtl/uart/async_tx_rx.v,../../../../rtl/uart/uart.v,../../../../rtl/vga/font_rom.v,../../../../rtl/vga/vga.v,../../../../rtl/vga/vram.v
+ProjectCFiles=
+CurImplementation=icecube2_Implmnt
+Implementations=icecube2_Implmnt
+StartFromSynthesis=yes
+IPGeneration=false
+
+[icecube2_Implmnt]
+DeviceFamily=iCE40
+Device=LP8K
+DevicePackage=CM81
+DevicePower=
+NetlistFile=icecube2_Implmnt/icecube2.edf
+AdditionalEDIFFile=
+IPEDIFFile=
+DesignLib=icecube2_Implmnt/sbt/netlist/oadb-apple1_top
+DesignView=_rt
+DesignCell=apple1_top
+SynthesisSDCFile=icecube2_Implmnt/icecube2.scf
+UserPinConstraintFile=
+UserSDCFile=
+PhysicalConstraintFile=../tinyfpga_bx.pcf
+BackendImplPathName=
+Devicevoltage=1.14
+DevicevoltagePerformance=+/-5%(datasheet default)
+DeviceTemperature=85
+TimingAnalysisBasedOn=Worst
+OperationRange=Commercial
+TypicalCustomTemperature=25
+WorstCustomTemperature=85
+BestCustomTemperature=0
+IOBankVoltages=topBank,3.3 bottomBank,3.3 leftBank,3.3 rightBank,3.3
+derValue=1.03369
+TimingPathNumberStick=0
+
+[lse options]
+CarryChain=True
+CarryChainLength=0
+CommandLineOptions=
+EBRUtilization=100.00
+FSMEncodingStyle=Auto
+FixGatedClocks=True
+I/OInsertion=True
+IntermediateFileDump=False
+LoopLimit=1950
+MaximalFanout=10000
+MemoryInitialValueFileSearchPath=
+NumberOfCriticalPaths=3
+OptimizationGoal=Area
+PropagateConstants=True
+RAMStyle=Auto
+ROMStyle=Auto
+RWCheckOnRam=False
+RemoveDuplicateRegisters=True
+ResolvedMixedDrivers=False
+ResourceSharing=True
+TargetFrequency=
+TopLevelUnit=
+UseIORegister=Auto
+VHDL2008=False
+VerilogIncludeSearchPath=
+
+[tool options]
+PlacerEffortLevel=std
+PlacerAutoLutCascade=yes
+PlacerAutoRamCascade=yes
+PlacerPowerDriven=no
+PlacerAreaDriven=no
+RouteWithTimingDriven=yes
+RouteWithPinPermutation=yes
+BitmapSPIFlashMode=yes
+BitmapRAM4KInit=yes
+BitmapInitRamBank=1111
+BitmapOscillatorFR=low
+BitmapEnableWarmBoot=yes
+BitmapDisableHeader=no
+BitmapSetSecurity=no
+BitmapSetNoUsedIONoPullup=no
+FloorPlannerShowFanInNets=yes
+FloorPlannerShowFanOutNets=yes
+HookTo3rdPartyTextEditor=
+

boards/tinyfpga_bx/icecube2/icecube2_syn.prj

@@ -0,0 +1,73 @@
+#-- Synopsys, Inc.
+#-- Project file Z:\boards\tinyfpga_bx\\icecube2\icecube2_syn.prj
+#project files
+add_file -verilog -lib work "../../../../rtl/apple1.v"
+add_file -verilog -lib work "../../../../rtl/clock.v"
+add_file -verilog -lib work "../../../../rtl/pwr_reset.v"
+add_file -verilog -lib work "../../../../rtl/ram.v"
+add_file -verilog -lib work "../../../../rtl/rom_basic.v"
+add_file -verilog -lib work "../../../../rtl/rom_wozmon.v"
+add_file -verilog -lib work "../../../../rtl/boards/tinyfpga_bx/apple1_hx8k.v"
+add_file -verilog -lib work "../../../../rtl/boards/tinyfpga_bx/clock_pll.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet_6502.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet/ALU.v"
+add_file -verilog -lib work "../../../../rtl/cpu/arlet/cpu.v"
+add_file -verilog -lib work "../../../../rtl/ps2keyboard/debounce.v"
+add_file -verilog -lib work "../../../../rtl/ps2keyboard/ps2keyboard.v"
+add_file -verilog -lib work "../../../../rtl/uart/async_tx_rx.v"
+add_file -verilog -lib work "../../../../rtl/uart/uart.v"
+add_file -verilog -lib work "../../../../rtl/vga/font_rom.v"
+add_file -verilog -lib work "../../../../rtl/vga/vga.v"
+add_file -verilog -lib work "../../../../rtl/vga/vram.v"
+
+#implementation: "icecube2_Implmnt"
+impl -add icecube2_Implmnt -type fpga
+
+#implementation attributes
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#device options
+set_option -technology SBTiCE40
+set_option -part iCE40LP8K
+set_option -package CM81
+set_option -speed_grade 
+set_option -part_companion ""
+
+#compilation/mapping options
+
+# mapper_options
+set_option -frequency auto
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+# Silicon Blue iCE40
+set_option -maxfan 10000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -retiming 0
+set_option -update_models_cp 0
+set_option -fixgatedclocks 2
+set_option -fixgeneratedclocks 0
+
+# NFilter
+set_option -popfeed 0
+set_option -constprop 0
+set_option -createhierarchy 0
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file ./icecube2_Implmnt/icecube2.edf
+project -log_file "./icecube2_Implmnt/icecube2.srr"
+impl -active "icecube2_Implmnt"
+project -run synthesis -clean

boards/tinyfpga_bx/tinyfpga_bx.pcf

@@ -0,0 +1,17 @@
+## System Clock
+set_io clk B2
+
+## VGA Display
+set_io vga_red A6
+set_io vga_grn B6
+set_io vga_blu A7
+set_io vga_h_sync B7
+set_io vga_v_sync A8
+
+## UART
+set_io uart_rx B1
+set_io uart_tx C2
+
+## Lighthouse
+set_io lt_dat H1
+set_io lt_env J1

boards/tinyfpga_bx/yosys/Makefile

@@ -0,0 +1,82 @@
+DEVICE = 8k
+PACKAGE = cm81
+FREQ_OSC = 16
+FREQ_PLL = 25
+
+PIN_DEF=tinyfpga_bx.pcf
+
+SOURCEDIR = ../../../rtl
+BUILDDIR = build
+
+PLL = $(BUILDDIR)/pll.sv
+
+all: apple1 prog
+
+info:
+	@echo "       To build: make apple1"
+	@echo "     To program: make prog"
+	@echo "To build report: make report"
+	@echo "    To clean up: make clean"
+
+dir:
+	mkdir -p $(BUILDDIR)
+
+# ------ TEMPLATES ------
+$(BUILDDIR)/%.blif: $(SOURCEDIR)/%.v
+	yosys -q -p "synth_ice40 -top apple1_top -blif $@" $^
+
+$(BUILDDIR)/%.asc: $(PIN_DEF) $(BUILDDIR)/%.blif
+	arachne-pnr -d $(DEVICE) -P $(PACKAGE) -o $@ -p $^
+
+$(BUILDDIR)/%.bin: $(BUILDDIR)/%.asc
+	icepack $^ $@
+
+%.rpt: $(BUILDDIR)/%.asc
+	icetime -d $(DEVICE) -mtr $@ $<
+
+%_tb.vvp: %_tb.v %.v
+	iverilog -o $@ $^
+
+%_tb.vcd: %_tb.vvp
+	vvp -N $< +vcd=$@
+
+$(PLL):
+	icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
+
+# ------ APPLE 1 ------
+apple1: dir $(BUILDDIR)/apple1.bin
+report: dir apple1.rpt
+
+$(BUILDDIR)/apple1.bin: $(BUILDDIR)/apple1.asc
+$(BUILDDIR)/apple1.asc: $(BUILDDIR)/apple1.blif
+$(BUILDDIR)/apple1.blif: $(SOURCEDIR)/apple1.v \
+	$(SOURCEDIR)/clock.v \
+	$(SOURCEDIR)/pwr_reset.v \
+	$(SOURCEDIR)/ram.v \
+	$(SOURCEDIR)/rom_wozmon.v \
+	$(SOURCEDIR)/rom_basic.v \
+	$(SOURCEDIR)/cpu/arlet_6502.v \
+	$(SOURCEDIR)/cpu/arlet/ALU.v \
+	$(SOURCEDIR)/cpu/arlet/cpu.v \
+	$(SOURCEDIR)/uart/uart.v \
+	$(SOURCEDIR)/uart/async_tx_rx.v \
+	$(SOURCEDIR)/vga/vga.v \
+	$(SOURCEDIR)/vga/vram.v \
+	$(SOURCEDIR)/vga/font_rom.v \
+	$(SOURCEDIR)/ps2keyboard/debounce.v \
+	$(SOURCEDIR)/ps2keyboard/ps2keyboard.v \
+	$(SOURCEDIR)/boards/tinyfpga_bx/clock_pll.v \
+	$(SOURCEDIR)/boards/tinyfpga_bx/apple1_hx8k.v \
+	$(BUILDDIR)/pll.sv
+
+apple1.rpt: $(BUILDDIR)/apple1.asc
+
+prog: dir $(BUILDDIR)/apple1.bin
+	tinyprog -p $(filter-out $<,$^)
+
+# ------ HELPERS ------
+clean:
+	rm -rf build apple1.rpt
+
+.SECONDARY:
+.PHONY: all info clean prog iceprog

boards/tinyfpga_bx/yosys/tinyfpga_bx.pcf

@@ -0,0 +1 @@
+../tinyfpga_bx.pcf

rtl/apple1.v

@@ -35,7 +35,6 @@ module apple1 #(
     // I/O interface to computer
     input  uart_rx,             // asynchronous serial data input from computer
     output uart_tx,             // asynchronous serial data output to computer
-    output uart_cts,            // clear to send flag to computer
 
     // I/O interface to keyboard
     input ps2_clk,              // PS/2 keyboard serial clock input
@@ -177,9 +176,8 @@ module apple1 #(
 
         .uart_rx(uart_rx),
         .uart_tx(uart_tx),
-        .uart_cts(uart_cts),
 
-        .address(ab[1:0]),        // for uart
+        .address(ab[1:0]),
         .w_en(we & uart_cs),
         .din(dbo),
         .dout(uart_dout)

rtl/boards/tinyfpga_bx/apple1_hx8k.v

@@ -0,0 +1,115 @@
+// Licensed to the Apache Software Foundation (ASF) under one
+// or more contributor license agreements.  See the NOTICE file
+// distributed with this work for additional information
+// regarding copyright ownership.  The ASF licenses this file
+// to you under the Apache License, Version 2.0 (the
+// "License"); you may not use this file except in compliance
+// with the License.  You may obtain a copy of the License at
+//
+//   http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing,
+// software distributed under the License is distributed on an
+// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+// KIND, either express or implied.  See the License for the
+// specific language governing permissions and limitations
+// under the License.
+//
+// Description: Apple 1 implementation for the iCE40HX8K dev
+//              board.
+//
+// Author.....: Alan Garfield
+// Date.......: 21-10-2018
+//
+
+module apple1_top #(
+    parameter BASIC_FILENAME      = "../../../roms/basic.hex",
+    parameter FONT_ROM_FILENAME   = "../../../roms/vga_font_bitreversed.hex",
+    parameter RAM_FILENAME        = "../../../roms/ram.hex",
+    parameter VRAM_FILENAME       = "../../../roms/vga_vram.bin",
+    parameter WOZMON_ROM_FILENAME = "../../../roms/wozmon.hex"
+) (
+    input clk,          // 16 MHz board clock
+
+    // I/O interface to computer
+    input  uart_rx,         // asynchronous serial data input from computer
+    output uart_tx,         // asynchronous serial data output to computer
+
+    // Outputs to VGA display
+    output vga_h_sync,      // hozizontal VGA sync pulse
+    output vga_v_sync,      // vertical VGA sync pulse
+    output vga_red,         // red VGA signal
+    output vga_grn,         // green VGA signal
+    output vga_blu,         // blue VGA signal
+
+    inout lt_dat,
+    inout lt_env
+);
+
+    wire clk25;
+
+    // 16MHz up to 25MHz
+    clock_pll clock_pll_inst(
+            .REFERENCECLK(clk),
+            .PLLOUTGLOBAL(clk25),
+            .RESET(1'b1)
+            );
+
+    // lighthouse sensor
+    wire lt_data_rw;
+    wire lt_data_in, lt_data_out;
+    SB_IO #(
+        .PIN_TYPE(6'b101001),
+        .PULLUP(1'b1)
+    ) lt_dat_io (
+        .PACKAGE_PIN(lt_dat),
+        .OUTPUT_ENABLE(lt_data_rw),
+        .D_IN_0(lt_data_in),
+        .D_OUT_0(lt_data_out)
+    );
+
+    wire lt_env_rw;
+    wire lt_env_in, lt_env_out;
+    SB_IO #(
+        .PIN_TYPE(6'b101001),
+        .PULLUP(1'b1)
+    ) lt_env_io (
+        .PACKAGE_PIN(lt_env),
+        .OUTPUT_ENABLE(lt_env_rw),
+        .D_IN_0(lt_env_in),
+        .D_OUT_0(lt_env_out)
+    );
+
+    assign lt_data_rw = 1'b0;
+    assign lt_data_out = 1'b0;
+    assign lt_env_rw = 1'b0;
+    assign lt_env_out = 1'b0;
+
+    // program counter
+    wire pc_monitor;
+
+    // apple one main system
+    apple1 #(
+        .BASIC_FILENAME (BASIC_FILENAME),
+        .FONT_ROM_FILENAME (FONT_ROM_FILENAME),
+        .RAM_FILENAME (RAM_FILENAME),
+        .VRAM_FILENAME (VRAM_FILENAME),
+        .WOZMON_ROM_FILENAME (WOZMON_ROM_FILENAME)
+    ) my_apple1(
+        .clk25(clk25),
+        .rst_n(1'b1),
+        .uart_rx(uart_rx),
+        .uart_tx(uart_tx),
+        .ps2_clk(1'b0),
+        .ps2_din(1'b0),
+        .ps2_select(1'b1),
+        .vga_h_sync(vga_h_sync),
+        .vga_v_sync(vga_v_sync),
+        .vga_red(vga_red),
+        .vga_grn(vga_grn),
+        .vga_blu(vga_blu),
+        .vga_cls(1'b0),
+        .pc_monitor(pc_monitor)
+    );
+
+endmodule

rtl/boards/tinyfpga_bx/clock_pll.v

@@ -0,0 +1,38 @@
+module clock_pll(REFERENCECLK,
+                 PLLOUTCORE,
+                 PLLOUTGLOBAL,
+                 RESET);
+
+input REFERENCECLK;
+input RESET;    /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ 
+output PLLOUTCORE;
+output PLLOUTGLOBAL;
+
+SB_PLL40_CORE clock_pll_inst(.REFERENCECLK(REFERENCECLK),
+                             .PLLOUTCORE(PLLOUTCORE),
+                             .PLLOUTGLOBAL(PLLOUTGLOBAL),
+                             .EXTFEEDBACK(1'd0),
+                             .DYNAMICDELAY(8'd0),
+                             .RESETB(RESET),
+                             .BYPASS(1'b0),
+                             .LATCHINPUTVALUE(1'd0),
+                             .LOCK(),
+                             .SDI(1'd0),
+                             .SDO(),
+                             .SCLK(1'd0));
+
+//\\ Fin=16, Fout=25;
+defparam clock_pll_inst.DIVR = 4'b0000;
+defparam clock_pll_inst.DIVF = 7'b0110001;
+defparam clock_pll_inst.DIVQ = 3'b101;
+defparam clock_pll_inst.FILTER_RANGE = 3'b001;
+defparam clock_pll_inst.FEEDBACK_PATH = "SIMPLE";
+defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+defparam clock_pll_inst.FDA_FEEDBACK = 4'b0000;
+defparam clock_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
+defparam clock_pll_inst.FDA_RELATIVE = 4'b0000;
+defparam clock_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
+defparam clock_pll_inst.PLLOUT_SELECT = "GENCLK";
+defparam clock_pll_inst.ENABLE_ICEGATE = 1'b0;
+
+endmodule

rtl/uart/uart.v

@@ -32,8 +32,7 @@ module uart(
     output reg [7:0] dout,  // 8-bit data bus (output)
 
     input uart_rx,          // asynchronous serial data input from computer
-    output uart_tx,         // asynchronous serial data output to computer
-    output uart_cts         // clear to send flag to computer
+    output uart_tx          // asynchronous serial data output to computer
     );
 
     parameter ClkFrequency = 25000000;	// 25MHz
@@ -91,8 +90,6 @@ module uart(
         end
     end
 
-    assign uart_cts = ~rx_idle || uart_rx_status;
-
     localparam UART_RX   = 2'b00;
     localparam UART_RXCR = 2'b01;
     localparam UART_TX   = 2'b10;