verilog-apple-one/rtl
2018-01-27 13:40:59 +11:00
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boards/ice40hx8k Cleaned up mess, and added HX8K board top file 2018-01-27 13:40:59 +11:00
cpu Editted CPU and testbench for better simulation 2018-01-27 00:48:05 +01:00
led_and_key move things around. 2018-01-27 00:21:05 +11:00
uart Cleaned up mess, and added HX8K board top file 2018-01-27 13:40:59 +11:00
vga move things around. 2018-01-27 00:21:05 +11:00
apple1.v Cleaned up mess, and added HX8K board top file 2018-01-27 13:40:59 +11:00
ram.v Added iverilog simulation support 2018-01-26 23:32:31 +01:00
rom_wozmon.v Added iverilog simulation support 2018-01-26 23:32:31 +01:00