Apple-1-HW/verilog-apple-one
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2226afe669
verilog-apple-one/rtl/boards
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Olof Kindgren 2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
2018-02-12 14:04:00 +01:00
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ice40hx8k-b-evn Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
terasic_de0 Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
tinyfpga_b2 Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
upduino Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00