Apple-1-HW/verilog-apple-one
1
0
Fork 0
mirror of https://github.com/alangarf/apple-one.git synced 2024-07-09 23:28:59 +00:00
Code Issues Projects Releases Wiki Activity
2226afe669
verilog-apple-one/rtl/boards/tinyfpga_b2
History
Olof Kindgren 2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
2018-02-12 14:04:00 +01:00
..
apple1_hx8k.v Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
clock_pll.v moved tinyfpga rtl to rtl/boards 2018-02-12 08:43:29 +11:00