Apple-1-HW/verilog-apple-one
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verilog-apple-one/rtl
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Niels Moseley 5e3f065223 Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined
2018-01-27 01:21:47 +01:00
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boards/ice40hx8k move things around. 2018-01-27 00:21:05 +11:00
cpu Editted CPU and testbench for better simulation 2018-01-27 00:48:05 +01:00
led_and_key move things around. 2018-01-27 00:21:05 +11:00
uart Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
vga move things around. 2018-01-27 00:21:05 +11:00
apple1_top.v Forced some internal CPU signals at start of simuation to get rid of undefined signals. Also made sure hard_reset signal is never undefined 2018-01-27 01:21:47 +01:00
ram.v Added iverilog simulation support 2018-01-26 23:32:31 +01:00
rom_wozmon.v Added iverilog simulation support 2018-01-26 23:32:31 +01:00