Apple-1-HW/verilog-apple-one
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verilog-apple-one/rtl
History
Niels Moseley 645ec26081 Added missing 7-segment display driver for DE0 board
2018-01-27 18:47:56 +01:00
..
boards
Added missing 7-segment display driver for DE0 board
2018-01-27 18:47:56 +01:00
cpu
Fixed bug in pc_monitor signal
2018-01-27 18:15:19 +01:00
led_and_key
move things around.
2018-01-27 00:21:05 +11:00
uart
added reset logic to uart and CPU
2018-01-28 00:23:09 +11:00
vga
move things around.
2018-01-27 00:21:05 +11:00
apple1.v
Added missing 7-segment display driver for DE0 board
2018-01-27 18:47:56 +01:00
ram.v
Yay got iverilog sim working!
2018-01-27 22:13:52 +11:00
rom_wozmon.v
Yay got iverilog sim working!
2018-01-27 22:13:52 +11:00