Apple-1-HW/verilog-apple-one
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verilog-apple-one/rtl/boards/terasic_de0
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Olof Kindgren 2226afe669 Expose ROM/RAM files as top-level parameters 
This allows file names to be overridden at compile-time.

It also gets rid of the ifdef SIM in the verilog components
2018-02-12 14:04:00 +01:00
..
apple1_de0_top.v Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
segmentdisplay.v Added missing 7-segment display driver for DE0 board 2018-01-27 18:47:56 +01:00