Apple-1-HW/verilog-apple-one
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verilog-apple-one/iverilog
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Alan Garfield 20919fa726 wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok
2018-02-05 00:12:06 +11:00
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apple1_files.txt added basic rom and fix uart issue on HX 2018-01-28 15:02:51 +11:00
apple1_tb.v wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok 2018-02-05 00:12:06 +11:00
run_testbench.bat Added SIM define to run_testbench.bat 2018-01-27 22:32:51 +01:00
run_vga_tb.sh wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok 2018-02-05 00:12:06 +11:00
vga_files.txt wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok 2018-02-05 00:12:06 +11:00
vga_tb.v wip of the pipeline VGA module. stupid yosys bug, but testbench looks ok 2018-02-05 00:12:06 +11:00