Apple-1-HW/verilog-apple-one
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verilog-apple-one/rtl/boards
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Alan Garfield 7ef0df07da
Merge pull request #11 from ironsteel/master 
Support for Olimex iCE40HX8K-EVB fpga board
2018-02-14 11:14:12 +11:00
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ice40hx8k-b-evn Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
olimex_ice40hx8k Initial port to olimex ice40hx8k with ice-40io 2018-02-11 13:28:37 +02:00
spartan3e_starterkit S3E updates. 2018-02-12 16:47:52 +01:00
terasic_de0 Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00
tinyfpga_b2 Remove non-existing port assignments 2018-02-12 15:19:40 +01:00
upduino Expose ROM/RAM files as top-level parameters 2018-02-12 14:04:00 +01:00