Apple-1-HW/verilog-apple-one
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9465e0c14d
verilog-apple-one/rtl
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Niels Moseley 9465e0c14d Added synchronous reset to clk enable divider to avoid undefined logic state in simulation
2018-01-26 23:41:58 +01:00
..
boards/ice40hx8k move things around. 2018-01-27 00:21:05 +11:00
cpu move things around. 2018-01-27 00:21:05 +11:00
led_and_key move things around. 2018-01-27 00:21:05 +11:00
uart Disabled ice40 specific define and clock generation. Added Terasic DE0 Quartus files. 2018-01-26 21:29:12 +01:00
vga move things around. 2018-01-27 00:21:05 +11:00
apple1_top.v Added synchronous reset to clk enable divider to avoid undefined logic state in simulation 2018-01-26 23:41:58 +01:00
ram.v Added iverilog simulation support 2018-01-26 23:32:31 +01:00
rom_wozmon.v Added iverilog simulation support 2018-01-26 23:32:31 +01:00