2017-05-06 17:31:51 +02:00
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cpldfit: version G.38 Xilinx Inc.
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Fitter Report
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2017-07-05 19:22:02 +02:00
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Design Name: spi6502b Date: 5-11-2017, 2:09AM
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2017-05-06 17:31:51 +02:00
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Device Used: XC9572XL-10-PC44
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Fitting Status: Successful
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**************************** Resource Summary ****************************
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Macrocells Product Terms Registers Pins Function Block
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Used Used Used Used Inputs Used
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2017-07-05 19:22:02 +02:00
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56 /72 ( 78%) 209 /360 ( 58%) 38 /72 ( 53%) 32 /34 ( 94%) 116/216 ( 54%)
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2017-05-06 17:31:51 +02:00
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PIN RESOURCES:
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Signal Type Required Mapped | Pin Type Used Remaining
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------------------------------------|---------------------------------------
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2017-07-05 19:22:02 +02:00
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Input : 13 13 | I/O : 26 2
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Output : 10 10 | GCK/IO : 3 0
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Bidirectional : 8 8 | GTS/IO : 2 0
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GCK : 1 1 | GSR/IO : 1 0
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2017-05-06 17:31:51 +02:00
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GTS : 0 0 |
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GSR : 0 0 |
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---- ----
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2017-07-05 19:22:02 +02:00
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Total 32 32
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2017-05-06 17:31:51 +02:00
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MACROCELL RESOURCES:
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Total Macrocells Available 72
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2017-07-05 19:22:02 +02:00
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Registered Macrocells 38
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Non-registered Macrocell driving I/O 15
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2017-05-06 17:31:51 +02:00
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GLOBAL RESOURCES:
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2017-07-05 19:22:02 +02:00
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Signal 'extclk' mapped onto global clock net GCK2.
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2017-05-06 17:31:51 +02:00
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Global output enable net(s) unused.
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Global set/reset net(s) unused.
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POWER DATA:
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2017-07-05 19:22:02 +02:00
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There are 56 macrocells in high performance mode (MCHP).
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2017-05-06 17:31:51 +02:00
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There are 0 macrocells in low power mode (MCLP).
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2017-07-05 19:22:02 +02:00
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There are a total of 56 macrocells used (MC).
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2017-05-06 17:31:51 +02:00
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End of Resource Summary
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*************** Summary of Required Resources ******************
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** LOGIC **
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Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
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Name Pt Used Mode Rate # Type Use State
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2017-07-05 19:22:02 +02:00
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$OpTx$INV$24__$INT 3 5 FB2_6 STD 37 I/O I
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add_dec/XLXN_11 1 4 FB3_17 STD 22 I/O I RESET
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b10 1 2 FB4_8 STD FAST 27 I/O O
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b8 1 2 FB4_2 STD FAST 25 I/O O
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b9 1 2 FB4_5 STD FAST 26 I/O O
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cpha 5 7 FB1_18 STD (b) (b) RESET
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cpol 5 7 FB1_16 STD (b) (b) RESET
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cpu_Nirq 1 1 FB2_9 STD FAST 39 GSR/I/O O
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cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 2 4 FB3_18 STD (b) (b)
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cpu_d<0> 5 9 FB1_5 STD FAST 2 I/O I/O
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cpu_d<1> 4 8 FB1_6 STD FAST 3 I/O I/O
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cpu_d<2> 4 8 FB1_8 STD FAST 4 I/O I/O
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cpu_d<3> 3 7 FB1_15 STD FAST 8 I/O I/O
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cpu_d<4> 5 9 FB1_17 STD FAST 9 I/O I/O
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cpu_d<5> 4 8 FB3_2 STD FAST 11 I/O I/O
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cpu_d<6> 3 7 FB3_5 STD FAST 12 I/O I/O
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cpu_d<7> 3 7 FB3_8 STD FAST 13 I/O I/O
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divisor<0> 5 7 FB1_14 STD 7 GCK/I/O I RESET
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divisor<1> 5 7 FB1_13 STD (b) (b) RESET
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divisor<2> 5 7 FB1_12 STD (b) (b) RESET
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ece 5 7 FB1_11 STD 6 GCK/I/O GCK/I RESET
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frx 5 7 FB1_10 STD (b) (b) RESET
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ier 5 7 FB4_18 STD (b) (b) RESET
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2017-05-06 18:14:04 +02:00
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led 1 3 FB4_14 STD FAST 29 I/O O
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2017-07-05 19:22:02 +02:00
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ng 1 3 FB3_15 STD FAST 20 I/O O
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noe 2 3 FB3_9 STD FAST 14 I/O O
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shiftcnt<0> 3 4 FB2_5 STD 36 I/O I RESET
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shiftcnt<1> 4 5 FB4_16 STD (b) (b) RESET
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shiftcnt<2> 4 6 FB4_15 STD 33 I/O (b) RESET
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shiftcnt<3> 4 7 FB4_13 STD (b) (b) RESET
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shiftdone 3 6 FB4_1 STD (b) (b) RESET
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2017-05-06 18:14:04 +02:00
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shifting2 2 3 FB2_3 STD (b) (b) RESET
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2017-07-05 19:22:02 +02:00
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slaveinten 5 7 FB1_9 STD 5 GCK/I/O I RESET
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spi_Nsel 5 7 FB4_11 STD FAST 28 I/O O RESET
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2017-05-06 17:31:51 +02:00
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spi_mosi 11 16 FB2_2 STD FAST 35 I/O O RESET
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spi_sclk 6 7 FB4_17 STD FAST 34 I/O O RESET
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2017-07-05 19:22:02 +02:00
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spidatain<0> 4 6 FB4_12 STD (b) (b) RESET
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spidatain<1> 4 5 FB4_10 STD (b) (b) RESET
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spidatain<2> 4 5 FB2_13 STD (b) (b) RESET
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spidatain<3> 4 5 FB2_12 STD (b) (b) RESET
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spidatain<4> 4 5 FB2_11 STD 40 GTS/I/O I RESET
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spidatain<5> 4 5 FB2_10 STD (b) (b) RESET
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spidatain<6> 4 5 FB2_8 STD 38 I/O I RESET
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2017-05-06 18:14:04 +02:00
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spidatain<7> 4 5 FB2_7 STD (b) (b) RESET
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2017-07-05 19:22:02 +02:00
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spidataout<0> 4 7 FB1_4 STD (b) (b) RESET
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spidataout<1> 4 7 FB1_3 STD (b) (b) RESET
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spidataout<2> 4 7 FB1_2 STD 1 I/O (b) RESET
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spidataout<3> 4 7 FB1_1 STD (b) (b) RESET
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spidataout<4> 4 7 FB4_9 STD (b) (b) RESET
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spidataout<5> 4 7 FB4_7 STD (b) (b) RESET
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spidataout<6> 4 7 FB4_6 STD (b) (b) RESET
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spidataout<7> 4 7 FB4_4 STD (b) (b) RESET
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start_shifting 4 7 FB4_3 STD (b) (b) RESET
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2017-05-06 18:14:04 +02:00
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start_shifting/start_shifting_RSTF__$INT 1 2 FB2_18 STD (b) (b)
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2017-07-05 19:22:02 +02:00
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tc 3 4 FB2_4 STD (b) (b) RESET
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tmo 5 7 FB1_7 STD (b) (b) RESET
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2017-05-06 17:31:51 +02:00
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** INPUTS **
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Signal Loc Pin Pin Pin
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Name # Type Use
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Ncs2 FB3_11 18 I/O I
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2017-07-05 19:22:02 +02:00
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a10 FB2_8 38 I/O I
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a8 FB2_5 36 I/O I
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a9 FB2_6 37 I/O I
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2017-05-06 17:31:51 +02:00
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cpu_Nphi2 FB1_9 5 GCK/I/O I
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cpu_Nres FB3_14 19 I/O I
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cpu_a<0> FB3_17 22 I/O I
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cpu_a<1> FB3_16 24 I/O I
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cpu_rnw FB1_14 7 GCK/I/O I
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2017-07-05 19:22:02 +02:00
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extclk FB1_11 6 GCK/I/O GCK/I
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nio_sel FB2_11 40 GTS/I/O I
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nio_stb FB2_15 43 I/O I
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2017-05-06 18:14:04 +02:00
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spi_int FB2_14 42 GTS/I/O I
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spi_miso FB2_17 44 I/O I
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2017-05-06 17:31:51 +02:00
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End of Resources
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*********************Function Block Resource Summary***********************
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Function # of FB Inputs Signals Total O/IO IO
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Block Macrocells Used Used Pt Used Req Avail
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2017-07-05 19:22:02 +02:00
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FB1 18 31 31 82 0/5 9
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FB2 13 31 31 48 2/0 9
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FB3 7 20 20 16 2/3 9
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FB4 18 34 34 63 6/0 7
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2017-05-06 17:31:51 +02:00
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---- ----- ----- -----
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2017-07-05 19:22:02 +02:00
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56 209 10/8 34
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2017-05-06 17:31:51 +02:00
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*********************************** FB1 ***********************************
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2017-05-06 18:14:04 +02:00
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Number of function block inputs used/remaining: 31/23
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Number of signals used by logic mapping into function block: 31
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2017-05-06 17:31:51 +02:00
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Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
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Name Pt Pt Pt Pt Mode # Type Use
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2017-07-05 19:22:02 +02:00
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spidataout<3> 4 0 0 1 FB1_1 STD (b) (b)
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2017-05-06 18:14:04 +02:00
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spidataout<2> 4 0 0 1 FB1_2 STD 1 I/O (b)
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2017-05-06 17:31:51 +02:00
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spidataout<1> 4 0 0 1 FB1_3 STD (b) (b)
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spidataout<0> 4 0 0 1 FB1_4 STD (b) (b)
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cpu_d<0> 5 0 0 0 FB1_5 STD 2 I/O I/O
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2017-05-06 18:14:04 +02:00
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cpu_d<1> 4 0 0 1 FB1_6 STD 3 I/O I/O
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2017-05-06 17:31:51 +02:00
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tmo 5 0 0 0 FB1_7 STD (b) (b)
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2017-05-06 18:14:04 +02:00
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cpu_d<2> 4 0 0 1 FB1_8 STD 4 I/O I/O
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slaveinten 5 0 0 0 FB1_9 STD 5 GCK/I/O I
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2017-05-06 17:31:51 +02:00
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frx 5 0 0 0 FB1_10 STD (b) (b)
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2017-07-05 19:22:02 +02:00
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ece 5 0 0 0 FB1_11 STD 6 GCK/I/O GCK/I
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2017-05-06 17:31:51 +02:00
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divisor<2> 5 0 0 0 FB1_12 STD (b) (b)
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divisor<1> 5 0 0 0 FB1_13 STD (b) (b)
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divisor<0> 5 0 0 0 FB1_14 STD 7 GCK/I/O I
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2017-05-06 18:14:04 +02:00
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cpu_d<3> 3 0 0 2 FB1_15 STD 8 I/O I/O
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2017-05-06 17:31:51 +02:00
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cpol 5 0 0 0 FB1_16 STD (b) (b)
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cpu_d<4> 5 0 0 0 FB1_17 STD 9 I/O I/O
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cpha 5 0 0 0 FB1_18 STD (b) (b)
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Signals Used by Logic in Function Block
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2017-07-05 19:22:02 +02:00
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1: cpu_d<0>.PIN 12: cpu_a<1> 22: spidatain<0>
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2: cpu_d<1>.PIN 13: cpu_rnw 23: spidatain<1>
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3: cpu_d<2>.PIN 14: divisor<0> 24: spidatain<2>
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4: cpu_d<3>.PIN 15: divisor<1> 25: spidatain<3>
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5: cpu_d<4>.PIN 16: divisor<2> 26: spidatain<4>
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6: Ncs2 17: ece 27: spidataout<0>
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7: cpha 18: frx 28: spidataout<1>
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8: cpol 19: slaveinten 29: spidataout<2>
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9: cpu_Nphi2 20: spi_Nsel 30: spidataout<3>
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10: cpu_Nres 21: spi_int 31: tmo
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2017-05-06 18:14:04 +02:00
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11: cpu_a<0>
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2017-05-06 17:31:51 +02:00
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Signal 1 2 3 4 Signals FB
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Name 0----+----0----+----0----+----0----+----0 Used Inputs
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2017-07-05 19:22:02 +02:00
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spidataout<3> ...X.X...XXXX................X.......... 7 7
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spidataout<2> ..X..X...XXXX...............X........... 7 7
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spidataout<1> .X...X...XXXX..............X............ 7 7
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spidataout<0> X....X...XXXX.............X............. 7 7
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cpu_d<0> .....XX.X.XXXX.....X.X.................. 9 9
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cpu_d<1> .....X.XX.XXX.X.......X................. 8 8
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tmo ...X.X...XXXX.................X......... 7 7
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cpu_d<2> .....X..X.XXX..XX......X................ 8 8
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slaveinten ....XX...XXXX.....X..................... 7 7
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frx ....XX...XXXX....X...................... 7 7
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ece ..X..X...XXXX...X....................... 7 7
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divisor<2> ..X..X...XXXX..X........................ 7 7
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divisor<1> .X...X...XXXX.X......................... 7 7
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divisor<0> X....X...XXXXX.......................... 7 7
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cpu_d<3> .....X..X.XXX...........X.....X......... 7 7
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cpol .X...X.X.XXXX........................... 7 7
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cpu_d<4> .....X..X.XXX....XX.X....X.............. 9 9
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cpha X....XX..XXXX........................... 7 7
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2017-05-06 17:31:51 +02:00
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0----+----1----+----2----+----3----+----4
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0 0 0 0
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Legend:
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Total Pt - Total product terms used by the macrocell signal
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Imp Pt - Product terms imported from other macrocells
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Exp Pt - Product terms exported to other macrocells
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in direction shown
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Unused Pt - Unused local product terms remaining in macrocell
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Loc - Location where logic was mapped in device
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Pwr Mode - Macrocell power mode
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Pin Type/Use - I - Input GCK - Global Clock
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O - Output GTS - Global Output Enable
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(b) - Buried macrocell GSR - Global Set/Reset
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X(@) - Signal used as input (wire-AND input) to the macrocell logic.
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The number of Signals Used may exceed the number of FB Inputs Used due
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to wire-ANDing in the switch matrix.
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*********************************** FB2 ***********************************
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2017-07-05 19:22:02 +02:00
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Number of function block inputs used/remaining: 31/23
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Number of signals used by logic mapping into function block: 31
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2017-05-06 17:31:51 +02:00
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Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
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Name Pt Pt Pt Pt Mode # Type Use
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2017-05-06 18:14:04 +02:00
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(unused) 0 0 \/5 0 FB2_1 (b) (b)
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2017-05-06 17:31:51 +02:00
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spi_mosi 11 6<- 0 0 FB2_2 STD 35 I/O O
|
2017-05-06 18:14:04 +02:00
|
|
|
|
shifting2 2 0 /\1 2 FB2_3 STD (b) (b)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
tc 3 0 0 2 FB2_4 STD (b) (b)
|
|
|
|
|
|
shiftcnt<0> 3 0 0 2 FB2_5 STD 36 I/O I
|
|
|
|
|
|
$OpTx$INV$24__$INT 3 0 0 2 FB2_6 STD 37 I/O I
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidatain<7> 4 0 0 1 FB2_7 STD (b) (b)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
spidatain<6> 4 0 0 1 FB2_8 STD 38 I/O I
|
|
|
|
|
|
cpu_Nirq 1 0 0 4 FB2_9 STD 39 GSR/I/O O
|
|
|
|
|
|
spidatain<5> 4 0 0 1 FB2_10 STD (b) (b)
|
|
|
|
|
|
spidatain<4> 4 0 0 1 FB2_11 STD 40 GTS/I/O I
|
|
|
|
|
|
spidatain<3> 4 0 0 1 FB2_12 STD (b) (b)
|
|
|
|
|
|
spidatain<2> 4 0 0 1 FB2_13 STD (b) (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB2_14 42 GTS/I/O I
|
|
|
|
|
|
(unused) 0 0 0 5 FB2_15 43 I/O I
|
|
|
|
|
|
(unused) 0 0 0 5 FB2_16 (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB2_17 44 I/O I
|
2017-05-06 18:14:04 +02:00
|
|
|
|
start_shifting/start_shifting_RSTF__$INT
|
|
|
|
|
|
1 0 0 4 FB2_18 STD (b) (b)
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2017-07-05 19:22:02 +02:00
|
|
|
|
1: $OpTx$INV$24__$INT
|
|
|
|
|
|
12: shiftcnt<2> 22: spidataout<0>
|
|
|
|
|
|
2: Ncs2 13: shiftcnt<3> 23: spidataout<1>
|
|
|
|
|
|
3: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
|
|
|
|
|
|
14: shiftdone 24: spidataout<2>
|
|
|
|
|
|
4: cpu_Nphi2 15: shifting2 25: spidataout<3>
|
|
|
|
|
|
5: cpu_Nres 16: spidatain<1> 26: spidataout<4>
|
|
|
|
|
|
6: cpu_a<0> 17: spidatain<2> 27: spidataout<5>
|
|
|
|
|
|
7: cpu_a<1> 18: spidatain<3> 28: spidataout<6>
|
|
|
|
|
|
8: ece 19: spidatain<4> 29: spidataout<7>
|
|
|
|
|
|
9: extclk 20: spidatain<5> 30: start_shifting
|
|
|
|
|
|
10: shiftcnt<0> 21: spidatain<6> 31: tmo
|
|
|
|
|
|
11: shiftcnt<1>
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 Signals FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Used Inputs
|
2017-07-05 19:22:02 +02:00
|
|
|
|
spi_mosi X...X.....XXXXX......XXXXXXXX.X......... 16 16
|
|
|
|
|
|
shifting2 X............X...............X.......... 3 3
|
|
|
|
|
|
tc .X...XX......X.......................... 4 4
|
|
|
|
|
|
shiftcnt<0> X...X....X....X......................... 4 4
|
|
|
|
|
|
$OpTx$INV$24__$INT ...X...XX.....X..............X.......... 5 5
|
|
|
|
|
|
spidatain<7> X...X....X....X.....X................... 5 5
|
|
|
|
|
|
spidatain<6> X...X....X....X....X.................... 5 5
|
|
|
|
|
|
cpu_Nirq ..X..................................... 1 1
|
|
|
|
|
|
spidatain<5> X...X....X....X...X..................... 5 5
|
|
|
|
|
|
spidatain<4> X...X....X....X..X...................... 5 5
|
|
|
|
|
|
spidatain<3> X...X....X....X.X....................... 5 5
|
|
|
|
|
|
spidatain<2> X...X....X....XX........................ 5 5
|
2017-05-06 17:31:51 +02:00
|
|
|
|
start_shifting/start_shifting_RSTF__$INT
|
2017-07-05 19:22:02 +02:00
|
|
|
|
....X........X.......................... 2 2
|
2017-05-06 17:31:51 +02:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
Legend:
|
|
|
|
|
|
Total Pt - Total product terms used by the macrocell signal
|
|
|
|
|
|
Imp Pt - Product terms imported from other macrocells
|
|
|
|
|
|
Exp Pt - Product terms exported to other macrocells
|
|
|
|
|
|
in direction shown
|
|
|
|
|
|
Unused Pt - Unused local product terms remaining in macrocell
|
|
|
|
|
|
Loc - Location where logic was mapped in device
|
|
|
|
|
|
Pwr Mode - Macrocell power mode
|
|
|
|
|
|
Pin Type/Use - I - Input GCK - Global Clock
|
|
|
|
|
|
O - Output GTS - Global Output Enable
|
|
|
|
|
|
(b) - Buried macrocell GSR - Global Set/Reset
|
|
|
|
|
|
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
|
|
|
|
|
|
The number of Signals Used may exceed the number of FB Inputs Used due
|
|
|
|
|
|
to wire-ANDing in the switch matrix.
|
|
|
|
|
|
*********************************** FB3 ***********************************
|
2017-07-05 19:22:02 +02:00
|
|
|
|
Number of function block inputs used/remaining: 20/34
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 20
|
2017-05-06 17:31:51 +02:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt Mode # Type Use
|
2017-05-06 18:14:04 +02:00
|
|
|
|
(unused) 0 0 0 5 FB3_1 (b)
|
|
|
|
|
|
cpu_d<5> 4 0 0 1 FB3_2 STD 11 I/O I/O
|
|
|
|
|
|
(unused) 0 0 0 5 FB3_3 (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB3_4 (b)
|
|
|
|
|
|
cpu_d<6> 3 0 0 2 FB3_5 STD 12 I/O I/O
|
|
|
|
|
|
(unused) 0 0 0 5 FB3_6 (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB3_7 (b)
|
|
|
|
|
|
cpu_d<7> 3 0 0 2 FB3_8 STD 13 I/O I/O
|
2017-07-05 19:22:02 +02:00
|
|
|
|
noe 2 0 0 3 FB3_9 STD 14 I/O O
|
2017-05-06 18:14:04 +02:00
|
|
|
|
(unused) 0 0 0 5 FB3_10 (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB3_11 18 I/O I
|
|
|
|
|
|
(unused) 0 0 0 5 FB3_12 (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB3_13 (b)
|
|
|
|
|
|
(unused) 0 0 0 5 FB3_14 19 I/O I
|
2017-07-05 19:22:02 +02:00
|
|
|
|
ng 1 0 0 4 FB3_15 STD 20 I/O O
|
2017-05-06 18:14:04 +02:00
|
|
|
|
(unused) 0 0 0 5 FB3_16 24 I/O I
|
2017-07-05 19:22:02 +02:00
|
|
|
|
add_dec/XLXN_11 1 0 0 4 FB3_17 STD 22 I/O I
|
|
|
|
|
|
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
|
|
|
|
|
|
2 0 0 3 FB3_18 STD (b) (b)
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2017-07-05 19:22:02 +02:00
|
|
|
|
1: Ncs2 8: cpu_a<1> 15: spi_int
|
|
|
|
|
|
2: a10 9: cpu_rnw 16: spidatain<5>
|
|
|
|
|
|
3: a8 10: ier 17: spidatain<6>
|
|
|
|
|
|
4: a9 11: nio_sel 18: spidatain<7>
|
|
|
|
|
|
5: add_dec/XLXN_11 12: nio_stb 19: start_shifting
|
|
|
|
|
|
6: cpu_Nphi2 13: shifting2 20: tc
|
|
|
|
|
|
7: cpu_a<0> 14: slaveinten
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 Signals FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Used Inputs
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d<5> X....XXXX...X..X..X..................... 8 8
|
|
|
|
|
|
cpu_d<6> X....XXXXX......X....................... 7 7
|
|
|
|
|
|
cpu_d<7> X....XXXX........X.X.................... 7 7
|
|
|
|
|
|
noe ....X.....XX............................ 3 3
|
|
|
|
|
|
ng X.........XX............................ 3 3
|
|
|
|
|
|
add_dec/XLXN_11 .XXX.......X............................ 4 4
|
|
|
|
|
|
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
|
|
|
|
|
|
.........X...XX....X.................... 4 4
|
2017-05-06 17:31:51 +02:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
Legend:
|
|
|
|
|
|
Total Pt - Total product terms used by the macrocell signal
|
|
|
|
|
|
Imp Pt - Product terms imported from other macrocells
|
|
|
|
|
|
Exp Pt - Product terms exported to other macrocells
|
|
|
|
|
|
in direction shown
|
|
|
|
|
|
Unused Pt - Unused local product terms remaining in macrocell
|
|
|
|
|
|
Loc - Location where logic was mapped in device
|
|
|
|
|
|
Pwr Mode - Macrocell power mode
|
|
|
|
|
|
Pin Type/Use - I - Input GCK - Global Clock
|
|
|
|
|
|
O - Output GTS - Global Output Enable
|
|
|
|
|
|
(b) - Buried macrocell GSR - Global Set/Reset
|
|
|
|
|
|
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
|
|
|
|
|
|
The number of Signals Used may exceed the number of FB Inputs Used due
|
|
|
|
|
|
to wire-ANDing in the switch matrix.
|
|
|
|
|
|
*********************************** FB4 ***********************************
|
2017-07-05 19:22:02 +02:00
|
|
|
|
Number of function block inputs used/remaining: 34/20
|
|
|
|
|
|
Number of signals used by logic mapping into function block: 34
|
2017-05-06 17:31:51 +02:00
|
|
|
|
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
|
|
|
|
|
|
Name Pt Pt Pt Pt Mode # Type Use
|
2017-07-05 19:22:02 +02:00
|
|
|
|
shiftdone 3 0 0 2 FB4_1 STD (b) (b)
|
|
|
|
|
|
b8 1 0 0 4 FB4_2 STD 25 I/O O
|
2017-05-06 18:14:04 +02:00
|
|
|
|
start_shifting 4 0 0 1 FB4_3 STD (b) (b)
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidataout<7> 4 0 0 1 FB4_4 STD (b) (b)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
b9 1 0 0 4 FB4_5 STD 26 I/O O
|
|
|
|
|
|
spidataout<6> 4 0 0 1 FB4_6 STD (b) (b)
|
|
|
|
|
|
spidataout<5> 4 0 0 1 FB4_7 STD (b) (b)
|
|
|
|
|
|
b10 1 0 0 4 FB4_8 STD 27 I/O O
|
|
|
|
|
|
spidataout<4> 4 0 0 1 FB4_9 STD (b) (b)
|
|
|
|
|
|
spidatain<1> 4 0 0 1 FB4_10 STD (b) (b)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spi_Nsel 5 0 0 0 FB4_11 STD 28 I/O O
|
2017-07-05 19:22:02 +02:00
|
|
|
|
spidatain<0> 4 0 0 1 FB4_12 STD (b) (b)
|
|
|
|
|
|
shiftcnt<3> 4 0 0 1 FB4_13 STD (b) (b)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
led 1 0 0 4 FB4_14 STD 29 I/O O
|
2017-07-05 19:22:02 +02:00
|
|
|
|
shiftcnt<2> 4 0 0 1 FB4_15 STD 33 I/O (b)
|
|
|
|
|
|
shiftcnt<1> 4 0 \/1 0 FB4_16 STD (b) (b)
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spi_sclk 6 1<- 0 0 FB4_17 STD 34 I/O O
|
2017-07-05 19:22:02 +02:00
|
|
|
|
ier 5 0 0 0 FB4_18 STD (b) (b)
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
Signals Used by Logic in Function Block
|
2017-07-05 19:22:02 +02:00
|
|
|
|
1: $OpTx$INV$24__$INT
|
|
|
|
|
|
13: cpu_Nres 24: shiftdone
|
|
|
|
|
|
2: cpu_d<0>.PIN 14: cpu_a<0> 25: shifting2
|
|
|
|
|
|
3: cpu_d<4>.PIN 15: cpu_a<1> 26: spi_Nsel
|
|
|
|
|
|
4: cpu_d<5>.PIN 16: cpu_rnw 27: spi_miso
|
|
|
|
|
|
5: cpu_d<6>.PIN 17: frx 28: spidatain<0>
|
|
|
|
|
|
6: cpu_d<7>.PIN 18: ier 29: spidataout<4>
|
|
|
|
|
|
7: Ncs2 19: nio_sel 30: spidataout<5>
|
|
|
|
|
|
8: a10 20: shiftcnt<0> 31: spidataout<6>
|
|
|
|
|
|
9: a8 21: shiftcnt<1> 32: spidataout<7>
|
|
|
|
|
|
10: a9 22: shiftcnt<2> 33: start_shifting
|
|
|
|
|
|
11: cpha 23: shiftcnt<3> 34: start_shifting/start_shifting_RSTF__$INT
|
|
|
|
|
|
12: cpol
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
Signal 1 2 3 4 Signals FB
|
|
|
|
|
|
Name 0----+----0----+----0----+----0----+----0 Used Inputs
|
2017-07-05 19:22:02 +02:00
|
|
|
|
shiftdone X...........X......XXXX................. 6 6
|
|
|
|
|
|
b8 ........X.........X..................... 2 2
|
|
|
|
|
|
start_shifting ......X......XXXX...............XX...... 7 7
|
|
|
|
|
|
spidataout<7> .....XX.....XXXX...............X........ 7 7
|
|
|
|
|
|
b9 .........X........X..................... 2 2
|
|
|
|
|
|
spidataout<6> ....X.X.....XXXX..............X......... 7 7
|
|
|
|
|
|
spidataout<5> ...X..X.....XXXX.............X.......... 7 7
|
|
|
|
|
|
b10 .......X..........X..................... 2 2
|
|
|
|
|
|
spidataout<4> ..X...X.....XXXX............X........... 7 7
|
|
|
|
|
|
spidatain<1> X...........X......X....X..X............ 5 5
|
|
|
|
|
|
spi_Nsel .X....X.....XXXX.........X.............. 7 7
|
|
|
|
|
|
spidatain<0> X...........X......X....XXX............. 6 6
|
|
|
|
|
|
shiftcnt<3> X...........X......XXXX.X............... 7 7
|
|
|
|
|
|
led ........................XX......X....... 3 3
|
|
|
|
|
|
shiftcnt<2> X...........X......XXX..X............... 6 6
|
|
|
|
|
|
shiftcnt<1> X...........X......XX...X............... 5 5
|
|
|
|
|
|
spi_sclk X.........XXX......X...XX............... 7 7
|
|
|
|
|
|
ier ....X.X.....XXXX.X...................... 7 7
|
2017-05-06 17:31:51 +02:00
|
|
|
|
0----+----1----+----2----+----3----+----4
|
|
|
|
|
|
0 0 0 0
|
|
|
|
|
|
Legend:
|
|
|
|
|
|
Total Pt - Total product terms used by the macrocell signal
|
|
|
|
|
|
Imp Pt - Product terms imported from other macrocells
|
|
|
|
|
|
Exp Pt - Product terms exported to other macrocells
|
|
|
|
|
|
in direction shown
|
|
|
|
|
|
Unused Pt - Unused local product terms remaining in macrocell
|
|
|
|
|
|
Loc - Location where logic was mapped in device
|
|
|
|
|
|
Pwr Mode - Macrocell power mode
|
|
|
|
|
|
Pin Type/Use - I - Input GCK - Global Clock
|
|
|
|
|
|
O - Output GTS - Global Output Enable
|
|
|
|
|
|
(b) - Buried macrocell GSR - Global Set/Reset
|
|
|
|
|
|
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
|
|
|
|
|
|
The number of Signals Used may exceed the number of FB Inputs Used due
|
|
|
|
|
|
to wire-ANDing in the switch matrix.
|
|
|
|
|
|
;;-----------------------------------------------------------------;;
|
|
|
|
|
|
; Implemented Equations.
|
|
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
$OpTx$INV$24__$INT <= ((ece AND NOT extclk)
|
2017-05-06 17:31:51 +02:00
|
|
|
|
OR (NOT ece AND NOT cpu_Nphi2)
|
|
|
|
|
|
OR (NOT start_shifting AND NOT shifting2));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_add_dec/XLXN_11: FDCPE port map (add_dec/XLXN_11,add_dec/XLXN_11_D,extclk,'0','0');
|
|
|
|
|
|
add_dec/XLXN_11_D <= (NOT nio_stb AND a9 AND a8 AND a10);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
b10 <= (a10 AND nio_sel);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
b8 <= (a8 AND nio_sel);
|
2017-05-06 18:14:04 +02:00
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
b9 <= (a9 AND nio_sel);
|
|
|
|
|
|
|
|
|
|
|
|
FTCPE_cpha: FTCPE port map (cpha,cpha_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpha_T <= ((cpha AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
|
|
|
|
|
|
OR (NOT cpha AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_cpol: FTCPE port map (cpol,cpol_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpol_T <= ((cpol AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(1).PIN)
|
|
|
|
|
|
OR (NOT cpol AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(1).PIN));
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
cpu_Nirq_I <= '0';
|
|
|
|
|
|
cpu_Nirq <= cpu_Nirq_I when cpu_Nirq_OE = '1' else 'Z';
|
|
|
|
|
|
cpu_Nirq_OE <= cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST <= ((ier AND tc)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (slaveinten AND NOT spi_int));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_divisor0: FTCPE port map (divisor(0),divisor_T(0),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
divisor_T(0) <= ((divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(0).PIN)
|
|
|
|
|
|
OR (NOT divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(0).PIN));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_divisor1: FTCPE port map (divisor(1),divisor_T(1),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
divisor_T(1) <= ((divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(1).PIN)
|
|
|
|
|
|
OR (NOT divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(1).PIN));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_divisor2: FTCPE port map (divisor(2),divisor_T(2),Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
divisor_T(2) <= ((divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(2).PIN)
|
|
|
|
|
|
OR (NOT divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(2).PIN));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_ece: FTCPE port map (ece,ece_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
ece_T <= ((ece AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(2).PIN)
|
|
|
|
|
|
OR (NOT ece AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(2).PIN));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_frx: FTCPE port map (frx,frx_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
frx_T <= ((frx AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
|
|
|
|
|
|
OR (NOT frx AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_ier: FTCPE port map (ier,ier_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 18:14:04 +02:00
|
|
|
|
ier_T <= ((ier AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(6).PIN)
|
2017-05-06 17:31:51 +02:00
|
|
|
|
OR (NOT ier AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(6).PIN));
|
|
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_I(0) <= ((NOT Ncs2 AND cpu_rnw AND spi_Nsel AND cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
cpu_a(0) AND cpu_Nphi2)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND cpha AND NOT cpu_a(1) AND cpu_a(0) AND
|
|
|
|
|
|
cpu_Nphi2)
|
|
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND divisor(0) AND cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(0) <= cpu_d_I(0) when cpu_d_OE(0) = '1' else 'Z';
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_OE(0) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_I(1) <= ((NOT Ncs2 AND cpu_rnw AND cpol AND NOT cpu_a(1) AND cpu_a(0) AND
|
|
|
|
|
|
cpu_Nphi2)
|
|
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND divisor(1) AND cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(1) <= cpu_d_I(1) when cpu_d_OE(1) = '1' else 'Z';
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_OE(1) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_I(2) <= ((NOT Ncs2 AND cpu_rnw AND ece AND NOT cpu_a(1) AND cpu_a(0) AND
|
|
|
|
|
|
cpu_Nphi2)
|
|
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND divisor(2) AND cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(2) <= cpu_d_I(2) when cpu_d_OE(2) = '1' else 'Z';
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_OE(2) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_I(3) <= ((NOT Ncs2 AND cpu_rnw AND tmo AND NOT cpu_a(1) AND cpu_a(0) AND
|
|
|
|
|
|
cpu_Nphi2)
|
|
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(3) <= cpu_d_I(3) when cpu_d_OE(3) = '1' else 'Z';
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_OE(3) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_I(4) <= ((NOT Ncs2 AND cpu_rnw AND frx AND NOT cpu_a(1) AND cpu_a(0) AND
|
|
|
|
|
|
cpu_Nphi2)
|
|
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND slaveinten AND cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
cpu_a(0) AND cpu_Nphi2)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND NOT spi_int AND
|
|
|
|
|
|
cpu_Nphi2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(4) <= cpu_d_I(4) when cpu_d_OE(4) = '1' else 'Z';
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_OE(4) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_I(5) <= ((NOT Ncs2 AND cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND start_shifting AND
|
|
|
|
|
|
cpu_a(0) AND cpu_Nphi2)
|
|
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
shifting2 AND cpu_Nphi2));
|
|
|
|
|
|
cpu_d(5) <= cpu_d_I(5) when cpu_d_OE(5) = '1' else 'Z';
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_OE(5) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_I(6) <= ((NOT Ncs2 AND cpu_rnw AND ier AND NOT cpu_a(1) AND cpu_a(0) AND
|
|
|
|
|
|
cpu_Nphi2)
|
|
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(6) <= cpu_d_I(6) when cpu_d_OE(6) = '1' else 'Z';
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_OE(6) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_I(7) <= ((NOT Ncs2 AND cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND
|
2017-05-06 18:14:04 +02:00
|
|
|
|
NOT cpu_a(0) AND cpu_Nphi2)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (NOT Ncs2 AND cpu_rnw AND NOT cpu_a(1) AND tc AND cpu_a(0) AND
|
|
|
|
|
|
cpu_Nphi2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(7) <= cpu_d_I(7) when cpu_d_OE(7) = '1' else 'Z';
|
2017-07-05 19:22:02 +02:00
|
|
|
|
cpu_d_OE(7) <= (NOT Ncs2 AND cpu_rnw AND cpu_Nphi2);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spi_mosi: FDCPE port map (spi_mosi_I,spi_mosi,NOT $OpTx$INV$24__$INT,'0',NOT cpu_Nres);
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spi_mosi <= ((EXP6_.EXP)
|
|
|
|
|
|
OR (shifting2.EXP)
|
2017-07-05 19:22:02 +02:00
|
|
|
|
OR (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(1) AND
|
|
|
|
|
|
NOT shiftdone AND NOT spidataout(0) AND shifting2)
|
|
|
|
|
|
OR (NOT shiftcnt(3) AND shiftcnt(2) AND shiftcnt(1) AND
|
|
|
|
|
|
NOT shiftdone AND NOT spidataout(4) AND shifting2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spi_mosi <= spi_mosi_I when spi_mosi_OE = '1' else 'Z';
|
|
|
|
|
|
spi_mosi_OE <= NOT tmo;
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spi_sclk: FDCPE port map (spi_sclk,spi_sclk_D,NOT $OpTx$INV$24__$INT,spi_sclk_CLR,spi_sclk_PRE);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spi_sclk_D <= cpol
|
|
|
|
|
|
XOR
|
2017-07-05 19:22:02 +02:00
|
|
|
|
spi_sclk_D <= ((shiftcnt(1).EXP)
|
2017-05-06 17:31:51 +02:00
|
|
|
|
OR (cpu_Nres AND NOT cpha AND shiftcnt(0) AND NOT shiftdone AND
|
|
|
|
|
|
shifting2));
|
|
|
|
|
|
spi_sclk_CLR <= (NOT cpu_Nres AND NOT cpol);
|
|
|
|
|
|
spi_sclk_PRE <= (NOT cpu_Nres AND cpol);
|
|
|
|
|
|
|
2017-05-06 18:14:04 +02:00
|
|
|
|
|
|
|
|
|
|
led <= (spi_Nsel AND NOT start_shifting AND NOT shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
|
|
|
|
|
|
ng <= (Ncs2 AND nio_stb AND nio_sel);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
noe <= NOT (((NOT nio_stb AND add_dec/XLXN_11)
|
|
|
|
|
|
OR (NOT nio_sel AND add_dec/XLXN_11)));
|
|
|
|
|
|
|
|
|
|
|
|
FDCPE_shiftcnt0: FDCPE port map (shiftcnt(0),shiftcnt_D(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
|
2017-05-06 17:31:51 +02:00
|
|
|
|
shiftcnt_D(0) <= (NOT shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_shiftcnt1: FDCPE port map (shiftcnt(1),shiftcnt_D(1),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
|
2017-05-06 17:31:51 +02:00
|
|
|
|
shiftcnt_D(1) <= ((shiftcnt(0) AND NOT shiftcnt(1) AND shifting2)
|
|
|
|
|
|
OR (NOT shiftcnt(0) AND shiftcnt(1) AND shifting2));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_shiftcnt2: FTCPE port map (shiftcnt(2),shiftcnt_T(2),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
|
2017-05-06 17:31:51 +02:00
|
|
|
|
shiftcnt_T(2) <= ((shiftcnt(2) AND NOT shifting2)
|
|
|
|
|
|
OR (shiftcnt(0) AND shiftcnt(1) AND shifting2));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_shiftcnt3: FTCPE port map (shiftcnt(3),shiftcnt_T(3),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
|
2017-05-06 17:31:51 +02:00
|
|
|
|
shiftcnt_T(3) <= ((shiftcnt(3) AND NOT shifting2)
|
|
|
|
|
|
OR (shiftcnt(2) AND shiftcnt(0) AND shiftcnt(1) AND
|
|
|
|
|
|
shifting2));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_shiftdone: FDCPE port map (shiftdone,shiftdone_D,NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0');
|
2017-05-06 17:31:51 +02:00
|
|
|
|
shiftdone_D <= (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(0) AND
|
|
|
|
|
|
shiftcnt(1));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_shifting2: FDCPE port map (shifting2,shifting2_D,NOT $OpTx$INV$24__$INT,'0','0');
|
2017-05-06 17:31:51 +02:00
|
|
|
|
shifting2_D <= (NOT shiftdone AND start_shifting);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_slaveinten: FTCPE port map (slaveinten,slaveinten_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 18:14:04 +02:00
|
|
|
|
slaveinten_T <= ((slaveinten AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
|
|
|
|
|
|
OR (NOT slaveinten AND cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spi_Nsel: FTCPE port map (spi_Nsel,spi_Nsel_T,Ncs2,'0',NOT cpu_Nres,NOT cpu_rnw);
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spi_Nsel_T <= ((spi_Nsel AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
|
|
|
|
|
|
OR (NOT spi_Nsel AND cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spidatain0: FDCPE port map (spidatain(0),spidatain_D(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(0));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidatain_D(0) <= (NOT spi_Nsel AND spi_miso);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidatain_CE(0) <= (shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spidatain1: FDCPE port map (spidatain(1),spidatain(0),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(1));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidatain_CE(1) <= (shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spidatain2: FDCPE port map (spidatain(2),spidatain(1),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(2));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidatain_CE(2) <= (shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spidatain3: FDCPE port map (spidatain(3),spidatain(2),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(3));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidatain_CE(3) <= (shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spidatain4: FDCPE port map (spidatain(4),spidatain(3),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(4));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidatain_CE(4) <= (shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spidatain5: FDCPE port map (spidatain(5),spidatain(4),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(5));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidatain_CE(5) <= (shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spidatain6: FDCPE port map (spidatain(6),spidatain(5),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(6));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidatain_CE(6) <= (shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_spidatain7: FDCPE port map (spidatain(7),spidatain(6),NOT $OpTx$INV$24__$INT,NOT cpu_Nres,'0',spidatain_CE(7));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
spidatain_CE(7) <= (shiftcnt(0) AND shifting2);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spidataout0: FTCPE port map (spidataout(0),spidataout_T(0),Ncs2,'0','0',spidataout_CE(0));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidataout_T(0) <= ((NOT cpu_a(1) AND spidataout(0) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
NOT cpu_d(0).PIN)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (NOT cpu_a(1) AND NOT spidataout(0) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(0).PIN));
|
|
|
|
|
|
spidataout_CE(0) <= (cpu_Nres AND NOT cpu_rnw);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spidataout1: FTCPE port map (spidataout(1),spidataout_T(1),Ncs2,'0','0',spidataout_CE(1));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidataout_T(1) <= ((NOT cpu_a(1) AND spidataout(1) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
NOT cpu_d(1).PIN)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (NOT cpu_a(1) AND NOT spidataout(1) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(1).PIN));
|
|
|
|
|
|
spidataout_CE(1) <= (cpu_Nres AND NOT cpu_rnw);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spidataout2: FTCPE port map (spidataout(2),spidataout_T(2),Ncs2,'0','0',spidataout_CE(2));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidataout_T(2) <= ((NOT cpu_a(1) AND spidataout(2) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
NOT cpu_d(2).PIN)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (NOT cpu_a(1) AND NOT spidataout(2) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(2).PIN));
|
|
|
|
|
|
spidataout_CE(2) <= (cpu_Nres AND NOT cpu_rnw);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spidataout3: FTCPE port map (spidataout(3),spidataout_T(3),Ncs2,'0','0',spidataout_CE(3));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidataout_T(3) <= ((NOT cpu_a(1) AND spidataout(3) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
NOT cpu_d(3).PIN)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (NOT cpu_a(1) AND NOT spidataout(3) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(3).PIN));
|
|
|
|
|
|
spidataout_CE(3) <= (cpu_Nres AND NOT cpu_rnw);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spidataout4: FTCPE port map (spidataout(4),spidataout_T(4),Ncs2,'0','0',spidataout_CE(4));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidataout_T(4) <= ((NOT cpu_a(1) AND spidataout(4) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
NOT cpu_d(4).PIN)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (NOT cpu_a(1) AND NOT spidataout(4) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(4).PIN));
|
|
|
|
|
|
spidataout_CE(4) <= (cpu_Nres AND NOT cpu_rnw);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spidataout5: FTCPE port map (spidataout(5),spidataout_T(5),Ncs2,'0','0',spidataout_CE(5));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidataout_T(5) <= ((NOT cpu_a(1) AND spidataout(5) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
NOT cpu_d(5).PIN)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (NOT cpu_a(1) AND NOT spidataout(5) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(5).PIN));
|
|
|
|
|
|
spidataout_CE(5) <= (cpu_Nres AND NOT cpu_rnw);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spidataout6: FTCPE port map (spidataout(6),spidataout_T(6),Ncs2,'0','0',spidataout_CE(6));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidataout_T(6) <= ((NOT cpu_a(1) AND spidataout(6) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
NOT cpu_d(6).PIN)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (NOT cpu_a(1) AND NOT spidataout(6) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(6).PIN));
|
|
|
|
|
|
spidataout_CE(6) <= (cpu_Nres AND NOT cpu_rnw);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_spidataout7: FTCPE port map (spidataout(7),spidataout_T(7),Ncs2,'0','0',spidataout_CE(7));
|
2017-05-06 18:14:04 +02:00
|
|
|
|
spidataout_T(7) <= ((NOT cpu_a(1) AND spidataout(7) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
NOT cpu_d(7).PIN)
|
2017-05-06 18:14:04 +02:00
|
|
|
|
OR (NOT cpu_a(1) AND NOT spidataout(7) AND NOT cpu_a(0) AND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
cpu_d(7).PIN));
|
|
|
|
|
|
spidataout_CE(7) <= (cpu_Nres AND NOT cpu_rnw);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_start_shifting: FTCPE port map (start_shifting,start_shifting_T,Ncs2,NOT start_shifting/start_shifting_RSTF__$INT,'0');
|
2017-05-06 18:14:04 +02:00
|
|
|
|
start_shifting_T <= ((NOT cpu_rnw AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0))
|
|
|
|
|
|
OR (frx AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0)));
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
start_shifting/start_shifting_RSTF__$INT <= (cpu_Nres AND NOT shiftdone);
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FDCPE_tc: FDCPE port map (tc,'0',Ncs2,'0',shiftdone,tc_CE);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
tc_CE <= (NOT cpu_a(1) AND NOT cpu_a(0));
|
|
|
|
|
|
|
2017-07-05 19:22:02 +02:00
|
|
|
|
FTCPE_tmo: FTCPE port map (tmo,tmo_T,Ncs2,NOT cpu_Nres,'0',NOT cpu_rnw);
|
2017-05-06 17:31:51 +02:00
|
|
|
|
tmo_T <= ((tmo AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(3).PIN)
|
|
|
|
|
|
OR (NOT tmo AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(3).PIN));
|
|
|
|
|
|
|
|
|
|
|
|
Register Legend:
|
|
|
|
|
|
FDCPE (Q,D,C,CLR,PRE,CE);
|
|
|
|
|
|
FTCPE (Q,D,C,CLR,PRE,CE);
|
|
|
|
|
|
LDCP (Q,D,G,CLR,PRE);
|
|
|
|
|
|
|
|
|
|
|
|
**************************** Device Pin Out ****************************
|
|
|
|
|
|
|
|
|
|
|
|
Device : XC9572XL-10-PC44
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------
|
|
|
|
|
|
/6 5 4 3 2 1 44 43 42 41 40 \
|
|
|
|
|
|
| 7 39 |
|
|
|
|
|
|
| 8 38 |
|
|
|
|
|
|
| 9 37 |
|
|
|
|
|
|
| 10 36 |
|
|
|
|
|
|
| 11 XC9572XL-10-PC44 35 |
|
|
|
|
|
|
| 12 34 |
|
|
|
|
|
|
| 13 33 |
|
|
|
|
|
|
| 14 32 |
|
|
|
|
|
|
| 15 31 |
|
|
|
|
|
|
| 16 30 |
|
|
|
|
|
|
| 17 29 |
|
|
|
|
|
|
\ 18 19 20 21 22 23 24 25 26 27 28 /
|
|
|
|
|
|
--------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin Signal Pin Signal
|
|
|
|
|
|
No. Name No. Name
|
2017-05-06 18:14:04 +02:00
|
|
|
|
1 TIE 23 GND
|
2017-05-06 17:31:51 +02:00
|
|
|
|
2 cpu_d<0> 24 cpu_a<1>
|
2017-07-05 19:22:02 +02:00
|
|
|
|
3 cpu_d<1> 25 b8
|
|
|
|
|
|
4 cpu_d<2> 26 b9
|
|
|
|
|
|
5 cpu_Nphi2 27 b10
|
2017-05-06 18:14:04 +02:00
|
|
|
|
6 extclk 28 spi_Nsel
|
|
|
|
|
|
7 cpu_rnw 29 led
|
2017-05-06 17:31:51 +02:00
|
|
|
|
8 cpu_d<3> 30 TDO
|
|
|
|
|
|
9 cpu_d<4> 31 GND
|
|
|
|
|
|
10 GND 32 VCC
|
|
|
|
|
|
11 cpu_d<5> 33 TIE
|
|
|
|
|
|
12 cpu_d<6> 34 spi_sclk
|
|
|
|
|
|
13 cpu_d<7> 35 spi_mosi
|
2017-07-05 19:22:02 +02:00
|
|
|
|
14 noe 36 a8
|
|
|
|
|
|
15 TDI 37 a9
|
|
|
|
|
|
16 TMS 38 a10
|
|
|
|
|
|
17 TCK 39 cpu_Nirq
|
|
|
|
|
|
18 Ncs2 40 nio_sel
|
2017-05-06 17:31:51 +02:00
|
|
|
|
19 cpu_Nres 41 VCC
|
2017-07-05 19:22:02 +02:00
|
|
|
|
20 ng 42 spi_int
|
|
|
|
|
|
21 VCC 43 nio_stb
|
2017-05-06 18:14:04 +02:00
|
|
|
|
22 cpu_a<0> 44 spi_miso
|
2017-05-06 17:31:51 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Legend : NC = Not Connected, unbonded pin
|
|
|
|
|
|
PGND = Unused I/O configured as additional Ground pin
|
|
|
|
|
|
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
|
|
|
|
|
|
VCC = Dedicated Power Pin
|
|
|
|
|
|
GND = Dedicated Ground Pin
|
|
|
|
|
|
TDI = Test Data In, JTAG pin
|
|
|
|
|
|
TDO = Test Data Out, JTAG pin
|
|
|
|
|
|
TCK = Test Clock, JTAG pin
|
|
|
|
|
|
TMS = Test Mode Select, JTAG pin
|
|
|
|
|
|
PE = Port Enable pin
|
|
|
|
|
|
PROHIBITED = User reserved pin
|
|
|
|
|
|
**************************** Compiler Options ****************************
|
|
|
|
|
|
|
|
|
|
|
|
Following is a list of all global compiler options used by the fitter run.
|
|
|
|
|
|
|
|
|
|
|
|
Device(s) Specified : xc9572xl-10-PC44
|
|
|
|
|
|
Optimization Method : SPEED
|
|
|
|
|
|
Multi-Level Logic Optimization : ON
|
|
|
|
|
|
Ignore Timing Specifications : OFF
|
|
|
|
|
|
Default Register Power Up Value : LOW
|
|
|
|
|
|
Keep User Location Constraints : ON
|
|
|
|
|
|
What-You-See-Is-What-You-Get : OFF
|
|
|
|
|
|
Exhaustive Fitting : OFF
|
|
|
|
|
|
Keep Unused Inputs : OFF
|
|
|
|
|
|
Slew Rate : FAST
|
|
|
|
|
|
Power Mode : STD
|
|
|
|
|
|
Set Unused I/O Pin Termination : FLOAT
|
|
|
|
|
|
Set I/O Pin Termination : KEEPER
|
|
|
|
|
|
Global Clock Optimization : ON
|
|
|
|
|
|
Global Set/Reset Optimization : ON
|
|
|
|
|
|
Global Ouput Enable Optimization : ON
|
|
|
|
|
|
Input Limit : 54
|
|
|
|
|
|
Pterm Limit : 25
|
