Apple-2-HW/AppleIISd
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additional misos and int removed

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This commit is contained in:
freitz85 2017-05-06 18:14:04 +02:00
parent 125f6d91e1
commit 50d903c980
18 changed files with 3578 additions and 4495 deletions
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17
SPI6502B.ucf
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@ -18,22 +18,13 @@ NET "cpu_Nphi2" LOC = "P5" ;
NET "cpu_Nres" LOC = "P19" ;
NET "cpu_rnw" LOC = "P7" ;
NET "cs1" LOC = "P20" ;
NET "diag" LOC = "P29" ;
NET "led" LOC = "P29" ;
NET "extclk" LOC = "P6" ;
NET "Ncs2" LOC = "P18" ;
NET "spi_int<0>" LOC = "P42" ;
NET "spi_int<1>" LOC = "P40" ;
NET "spi_int<2>" LOC = "P39" ;
NET "spi_int<3>" LOC = "P1" ;
NET "spi_miso<0>" LOC = "P44" ;
NET "spi_miso<1>" LOC = "P43" ;
NET "spi_miso<2>" LOC = "P38" ;
NET "spi_miso<3>" LOC = "P37" ;
NET "spi_int" LOC = "P42" ;
NET "spi_miso" LOC = "P44" ;
NET "spi_mosi" LOC = "P35" ;
NET "spi_Nsel<0>" LOC = "P28" ;
NET "spi_Nsel<1>" LOC = "P27" ;
NET "spi_Nsel<2>" LOC = "P26" ;
NET "spi_Nsel<3>" LOC = "P25" ;
NET "spi_Nsel" LOC = "P28" ;
NET "spi_sclk" LOC = "P34" ;
#PACE: Start of PACE Area Constraints

44
SPI6502B1.1.vhd
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@ -55,12 +55,12 @@ entity SPI6502B is
cs1 : in STD_LOGIC;
Ncs2 : in STD_LOGIC;
extclk : in STD_LOGIC;
spi_miso: in std_logic_vector (3 downto 0);
spi_miso: in std_logic;
spi_mosi : out STD_LOGIC;
spi_sclk : out STD_LOGIC;
spi_Nsel : out STD_LOGIC_VECTOR (3 downto 0);
spi_int : in STD_LOGIC_VECTOR (3 downto 0);
diag : out std_logic
spi_Nsel : out STD_LOGIC;
spi_int : in STD_LOGIC;
led : out std_logic
);
constant DIV_WIDTH : integer := 3;
@ -99,9 +99,9 @@ architecture Behavioral of SPI6502B is
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic_vector(3 downto 0); -- slave select output (0=selected)
signal slaveinten: std_logic_vector(3 downto 0); -- slave interrupt enable (1=enabled)
signal slaveint: std_logic_vector (3 downto 0); -- slave interrupt inputs
signal slavesel: std_logic; -- slave select output (0=selected)
signal slaveinten: std_logic; -- slave interrupt enable (1=enabled)
signal slaveint: std_logic; -- slave interrupt inputs
--------------------------
-- helper signals
@ -120,7 +120,7 @@ architecture Behavioral of SPI6502B is
begin
diag <= not (bsy or not slavesel(0)); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
led <= not (bsy or not slavesel); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
--------------------------
@ -250,10 +250,7 @@ begin
--------------------------
-- interrupt generation
int_out <= spiint
or (slaveint(0) and slaveinten(0))
or (slaveint(1) and slaveinten(1))
or (slaveint(2) and slaveinten(2))
or (slaveint(3) and slaveinten(3));
or (slaveint and slaveinten);
--------------------------
-- interface section
@ -264,11 +261,7 @@ begin
int_din <= cpu_d;
slaveint <= not(spi_int); -- active low interrupt inputs
int_miso <=
(spi_miso(0) and not(slavesel(0)))
or (spi_miso(1) and not(slavesel(1)))
or (spi_miso(2) and not(slavesel(2)))
or (spi_miso(3) and not(slavesel(3)));
int_miso <= (spi_miso and not slavesel);
-- outputs
cpu_d <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
@ -314,10 +307,13 @@ begin
when "10" => -- read sclk divisor
int_dout(DIV_WIDTH-1 downto 0) <= divisor;
int_dout(3) <= '0';
int_dout(7 downto 4) <= slaveint;
int_dout(4) <= slaveint;
int_dout(7 downto 5) <= (others => '0');
when "11" => -- read slave select / slave interrupt state
int_dout(3 downto 0) <= slavesel;
int_dout(7 downto 4) <= slaveinten;
int_dout(0) <= slavesel;
int_dout(3 downto 1) <= (others => '0');
int_dout(4) <= slaveinten;
int_dout(7 downto 5) <= (others => '0');
when others =>
int_dout <= (others => '0');
end case;
@ -336,8 +332,8 @@ begin
tmo <= '0';
frx <= '0';
ier <= '0';
slavesel <= (others => '1');
slaveinten <= (others => '0');
slavesel <= '1';
slaveinten <= '0';
divisor <= (others => '0');
elsif (falling_edge(selected) and cpu_rnw = '0') then
--elsif (falling_edge(cpu_phi2) and selected='1' and cpu_rnw='0') then
@ -356,8 +352,8 @@ begin
when "10" => -- write divisor
divisor <= int_din(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable
slavesel <= int_din(3 downto 0);
slaveinten <= int_din(7 downto 4);
slavesel <= int_din(0);
slaveinten <= int_din(4);
when others =>
end case;
end if;

2
_ngo/netlist.lst
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@ -1,2 +1,2 @@
C:\sources\AppleIISd\spi6502b.ngc 1494084468
C:\sources\AppleIISd\spi6502b.ngc 1494085672
OK

2
spi65.dhp
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@ -1,3 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.2e
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2
spi65.npl
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@ -20,7 +20,5 @@ DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE SPI6502B1.1.vhd
DEPASSOC spi6502b SPI6502B.ucf
[STATUS-ALL]
spi6502b.ngcFile=WARNINGS,1494084467
[STRATEGY-LIST]
Normal=True

2
spi6502b.bld
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@ -16,7 +16,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 58840 kilobytes
Total memory usage is 59352 kilobytes
Writing NGD file "spi6502b.ngd" ...

53
spi6502b.gyd
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@ -9,16 +9,9 @@ cpu_a<1> S:PIN24
cpu_rnw S:PIN7
cs1 S:PIN20
extclk S:PIN6
spi_int<0> S:PIN42
spi_int<1> S:PIN40
spi_int<2> S:PIN39
spi_int<3> S:PIN1
spi_miso<0> S:PIN44
spi_miso<1> S:PIN43
spi_miso<2> S:PIN38
spi_miso<3> S:PIN37
spi_int S:PIN42
spi_miso S:PIN44
cpu_Nirq S:PIN14
diag S:PIN29
cpu_d<0> S:PIN2
cpu_d<1> S:PIN3
cpu_d<2> S:PIN4
@ -29,30 +22,32 @@ cpu_d<6> S:PIN12
cpu_d<7> S:PIN13
spi_mosi S:PIN35
spi_sclk S:PIN34
spi_Nsel<0> S:PIN28
spi_Nsel<1> S:PIN27
spi_Nsel<2> S:PIN26
spi_Nsel<3> S:PIN25
led S:PIN29
spi_Nsel S:PIN28
;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.
PARTITION FB1_1 spidataout<3> spidataout<2> spidataout<1> spidataout<0>
int_dout<0> int_dout<1> tmo int_dout<2>
slaveinten<0> frx ece divisor<2>
divisor<1> divisor<0> int_dout<3> cpol
int_dout<4> cpha
PARTITION FB2_1 start_shifting/start_shifting_RSTF__$INT int_mosi EXP6_
PARTITION FB1_2 spidataout<2> spidataout<1> spidataout<0> int_dout<0>
int_dout<1> tmo int_dout<2> slaveinten
frx ece divisor<2> divisor<1>
divisor<0> int_dout<3> cpol int_dout<4>
cpha
PARTITION FB2_1 EXP6_ int_mosi shifting2 shiftdone
shiftcnt<0> $OpTx$INV$22__$INT spidatain<7> spidatain<6>
spidatain<5> spidatain<4> spidatain<3> spidatain<2>
spidatain<1> spidatain<0> shiftcnt<3> shiftcnt<2>
shiftcnt<1> start_shifting/start_shifting_RSTF__$INT
PARTITION FB3_2 int_dout<5>
PARTITION FB3_5 int_dout<6>
PARTITION FB3_8 int_dout<7> cpu_Nirq_OBUFE
PARTITION FB4_1 cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST tc start_shifting spidataout<7>
spidataout<6> spidataout<5> spidataout<4> spidataout<3>
ier
PARTITION FB4_11 slavesel
PARTITION FB4_14 led_OBUF
PARTITION FB4_16 EXP7_ int_sclk
PARTITION FB3_1 shifting2 int_dout<5> shiftdone $OpTx$INV$22__$INT
int_dout<6> start_shifting spidatain<7> int_dout<7>
cpu_Nirq_OBUFE spidatain<6> spidatain<5> spidatain<4>
spidatain<3> spidatain<2> spidatain<1> shiftcnt<3>
shiftcnt<2> cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
PARTITION FB4_1 tc slavesel<3> shiftcnt<0> spidataout<7>
slavesel<2> spidataout<6> spidataout<5> slavesel<1>
spidataout<4> shiftcnt<1> slavesel<0> slaveinten<3>
slaveinten<2> diag_OBUF slaveinten<1> ier
int_sclk spidatain<0>

1408
spi6502b.jed
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spi6502b.mfd
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2
spi6502b.ngc
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spi6502b.ngd
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spi6502b.ngr
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spi6502b.pnx
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@ -15,4 +15,4 @@
sr (SLOW|FAST|slow|fast) "SLOW"
dir (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part pkg="PC44" spg="-10" arch="xc9500xl" device="XC9572XL"/><pin nm="cpu_Nres" no="19" dir="input"/><pin nm="cpu_rnw" no="7" dir="input"/><pin nm="Ncs2" no="18" dir="input"/><pin nm="cs1" no="20" dir="input"/><pin nm="cpu_a&lt;1&gt;" no="24" dir="input"/><pin nm="cpu_a&lt;0&gt;" no="22" dir="input"/><pin nm="spi_miso&lt;3&gt;" no="37" dir="input"/><pin nm="spi_miso&lt;2&gt;" no="38" dir="input"/><pin nm="spi_miso&lt;1&gt;" no="43" dir="input"/><pin nm="spi_miso&lt;0&gt;" no="44" dir="input"/><pin nm="cpu_Nphi2" no="5" dir="input"/><pin nm="spi_int&lt;0&gt;" no="42" dir="input"/><pin nm="spi_int&lt;1&gt;" no="40" dir="input"/><pin nm="spi_int&lt;2&gt;" no="39" dir="input"/><pin nm="spi_int&lt;3&gt;" no="1" dir="input"/><pin nm="extclk" no="6" dir="input"/><pin nm="spi_mosi" no="35" sr="fast" dir="output"/><pin nm="spi_Nsel&lt;0&gt;" no="28" sr="fast" dir="output"/><pin nm="spi_Nsel&lt;1&gt;" no="27" sr="fast" dir="output"/><pin nm="spi_Nsel&lt;2&gt;" no="26" sr="fast" dir="output"/><pin nm="spi_Nsel&lt;3&gt;" no="25" sr="fast" dir="output"/><pin nm="spi_sclk" no="34" sr="fast" dir="output"/><pin nm="diag" no="29" sr="fast" dir="output"/><pin nm="cpu_Nirq" no="14" sr="fast" dir="output"/><pin nm="cpu_d&lt;0&gt;" no="2" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;1&gt;" no="3" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;2&gt;" no="4" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;3&gt;" no="8" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;4&gt;" no="9" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;5&gt;" no="11" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;6&gt;" no="12" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;7&gt;" no="13" sr="fast" dir="bidir"/></ibis>
<ibis><part pkg="PC44" spg="-10" arch="xc9500xl" device="XC9572XL"/><pin nm="cpu_Nres" no="19" dir="input"/><pin nm="cpu_rnw" no="7" dir="input"/><pin nm="Ncs2" no="18" dir="input"/><pin nm="cs1" no="20" dir="input"/><pin nm="cpu_a&lt;0&gt;" no="22" dir="input"/><pin nm="cpu_a&lt;1&gt;" no="24" dir="input"/><pin nm="spi_miso" no="44" dir="input"/><pin nm="cpu_Nphi2" no="5" dir="input"/><pin nm="spi_int" no="42" dir="input"/><pin nm="extclk" no="6" dir="input"/><pin nm="spi_mosi" no="35" sr="fast" dir="output"/><pin nm="spi_Nsel" no="28" sr="fast" dir="output"/><pin nm="spi_sclk" no="34" sr="fast" dir="output"/><pin nm="led" no="29" sr="fast" dir="output"/><pin nm="cpu_Nirq" no="14" sr="fast" dir="output"/><pin nm="cpu_d&lt;3&gt;" no="8" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;5&gt;" no="11" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;6&gt;" no="12" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;7&gt;" no="13" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;0&gt;" no="2" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;1&gt;" no="3" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;2&gt;" no="4" sr="fast" dir="bidir"/><pin nm="cpu_d&lt;4&gt;" no="9" sr="fast" dir="bidir"/></ibis>

679
spi6502b.rpt
View File

@ -1,7 +1,7 @@
cpldfit: version G.38 Xilinx Inc.
Fitter Report
Design Name: spi6502b Date: 5- 6-2017, 5:27PM
Design Name: spi6502b Date: 5- 6-2017, 5:47PM
Device Used: XC9572XL-10-PC44
Fitting Status: Successful
@ -9,25 +9,25 @@ Fitting Status: Successful
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
56 /72 ( 78%) 247 /360 ( 69%) 43 /72 ( 60%) 32 /34 ( 94%) 127/216 ( 59%)
50 /72 ( 69%) 202 /360 ( 56%) 37 /72 ( 51%) 23 /34 ( 68%) 106/216 ( 49%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 16 16 | I/O : 26 2
Output : 8 8 | GCK/IO : 3 0
Bidirectional : 8 8 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 1 0
Input : 10 10 | I/O : 19 9
Output : 5 5 | GCK/IO : 3 0
Bidirectional : 8 8 | GTS/IO : 1 1
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 32 32
Total 23 23
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 43
Registered Macrocells 37
Non-registered Macrocell driving I/O 10
GLOBAL RESOURCES:
@ -38,9 +38,9 @@ Global set/reset net(s) unused.
POWER DATA:
There are 56 macrocells in high performance mode (MCHP).
There are 50 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 56 macrocells used (MC).
There are a total of 50 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
@ -48,61 +48,55 @@ End of Resource Summary
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
$OpTx$INV$22__$INT 3 5 FB3_4 STD (b) (b)
$OpTx$INV$22__$INT 3 5 FB2_6 STD 37 I/O (b)
cpha 5 8 FB1_18 STD (b) (b) RESET
cpol 5 8 FB1_16 STD (b) (b) RESET
cpu_Nirq 1 1 FB3_9 STD FAST 14 I/O O
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 5 10 FB3_18 STD (b) (b)
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 2 4 FB4_1 STD (b) (b)
cpu_d<0> 5 10 FB1_5 STD FAST 2 I/O I/O
cpu_d<1> 5 10 FB1_6 STD FAST 3 I/O I/O
cpu_d<2> 5 10 FB1_8 STD FAST 4 I/O I/O
cpu_d<3> 4 9 FB1_15 STD FAST 8 I/O I/O
cpu_d<1> 4 9 FB1_6 STD FAST 3 I/O I/O
cpu_d<2> 4 9 FB1_8 STD FAST 4 I/O I/O
cpu_d<3> 3 8 FB1_15 STD FAST 8 I/O I/O
cpu_d<4> 5 10 FB1_17 STD FAST 9 I/O I/O
cpu_d<5> 6 11 FB3_2 STD FAST 11 I/O I/O
cpu_d<6> 5 10 FB3_5 STD FAST 12 I/O I/O
cpu_d<7> 5 10 FB3_8 STD FAST 13 I/O I/O
diag 1 3 FB4_14 STD FAST 29 I/O O
cpu_d<5> 4 9 FB3_2 STD FAST 11 I/O I/O
cpu_d<6> 3 8 FB3_5 STD FAST 12 I/O I/O
cpu_d<7> 3 8 FB3_8 STD FAST 13 I/O I/O
divisor<0> 5 8 FB1_14 STD 7 GCK/I/O I RESET
divisor<1> 5 8 FB1_13 STD (b) (b) RESET
divisor<2> 5 8 FB1_12 STD (b) (b) RESET
ece 5 8 FB1_11 STD 6 GCK/I/O I RESET
frx 5 8 FB1_10 STD (b) (b) RESET
ier 5 8 FB4_16 STD (b) (b) RESET
shiftcnt<0> 3 4 FB4_3 STD (b) (b) RESET
shiftcnt<1> 4 5 FB4_10 STD (b) (b) RESET
shiftcnt<2> 4 6 FB3_17 STD 22 I/O I RESET
shiftcnt<3> 4 7 FB3_16 STD 24 I/O I RESET
shiftdone 3 6 FB3_3 STD (b) (b) RESET
shifting2 2 3 FB3_1 STD (b) (b) RESET
slaveinten<0> 5 8 FB1_9 STD 5 GCK/I/O I RESET
slaveinten<1> 5 8 FB4_15 STD 33 I/O (b) RESET
slaveinten<2> 5 8 FB4_13 STD (b) (b) RESET
slaveinten<3> 5 8 FB4_12 STD (b) (b) RESET
spi_Nsel<0> 5 8 FB4_11 STD FAST 28 I/O O RESET
spi_Nsel<1> 5 8 FB4_8 STD FAST 27 I/O O RESET
spi_Nsel<2> 5 8 FB4_5 STD FAST 26 I/O O RESET
spi_Nsel<3> 5 8 FB4_2 STD FAST 25 I/O O RESET
ier 5 8 FB4_9 STD (b) (b) RESET
led 1 3 FB4_14 STD FAST 29 I/O O
shiftcnt<0> 3 4 FB2_5 STD 36 I/O (b) RESET
shiftcnt<1> 4 5 FB2_17 STD 44 I/O I RESET
shiftcnt<2> 4 6 FB2_16 STD (b) (b) RESET
shiftcnt<3> 4 7 FB2_15 STD 43 I/O (b) RESET
shiftdone 3 6 FB2_4 STD (b) (b) RESET
shifting2 2 3 FB2_3 STD (b) (b) RESET
slaveinten 5 8 FB1_9 STD 5 GCK/I/O I RESET
spi_Nsel 5 8 FB4_11 STD FAST 28 I/O O RESET
spi_mosi 11 16 FB2_2 STD FAST 35 I/O O RESET
spi_sclk 6 7 FB4_17 STD FAST 34 I/O O RESET
spidatain<0> 7 12 FB4_18 STD (b) (b) RESET
spidatain<1> 4 5 FB3_15 STD 20 I/O I RESET
spidatain<2> 4 5 FB3_14 STD 19 I/O I RESET
spidatain<3> 4 5 FB3_13 STD (b) (b) RESET
spidatain<4> 4 5 FB3_12 STD (b) (b) RESET
spidatain<5> 4 5 FB3_11 STD 18 I/O I RESET
spidatain<6> 4 5 FB3_10 STD (b) (b) RESET
spidatain<7> 4 5 FB3_7 STD (b) (b) RESET
spidatain<0> 4 6 FB2_14 STD 42 GTS/I/O I RESET
spidatain<1> 4 5 FB2_13 STD (b) (b) RESET
spidatain<2> 4 5 FB2_12 STD (b) (b) RESET
spidatain<3> 4 5 FB2_11 STD 40 GTS/I/O (b) RESET
spidatain<4> 4 5 FB2_10 STD (b) (b) RESET
spidatain<5> 4 5 FB2_9 STD 39 GSR/I/O (b) RESET
spidatain<6> 4 5 FB2_8 STD 38 I/O (b) RESET
spidatain<7> 4 5 FB2_7 STD (b) (b) RESET
spidataout<0> 4 8 FB1_4 STD (b) (b) RESET
spidataout<1> 4 8 FB1_3 STD (b) (b) RESET
spidataout<2> 4 8 FB1_2 STD 1 I/O I RESET
spidataout<3> 4 8 FB1_1 STD (b) (b) RESET
spidataout<4> 4 8 FB4_9 STD (b) (b) RESET
spidataout<5> 4 8 FB4_7 STD (b) (b) RESET
spidataout<6> 4 8 FB4_6 STD (b) (b) RESET
spidataout<2> 4 8 FB1_2 STD 1 I/O (b) RESET
spidataout<3> 4 8 FB4_8 STD 27 I/O (b) RESET
spidataout<4> 4 8 FB4_7 STD (b) (b) RESET
spidataout<5> 4 8 FB4_6 STD (b) (b) RESET
spidataout<6> 4 8 FB4_5 STD 26 I/O (b) RESET
spidataout<7> 4 8 FB4_4 STD (b) (b) RESET
start_shifting 4 8 FB3_6 STD (b) (b) RESET
start_shifting/start_shifting_RSTF__$INT 1 2 FB2_1 STD (b) (b)
tc 3 5 FB4_1 STD (b) (b) RESET
start_shifting 4 8 FB4_3 STD (b) (b) RESET
start_shifting/start_shifting_RSTF__$INT 1 2 FB2_18 STD (b) (b)
tc 3 5 FB4_2 STD 25 I/O (b) RESET
tmo 5 8 FB1_7 STD (b) (b) RESET
** INPUTS **
@ -116,83 +110,75 @@ cpu_a<1> FB3_16 24 I/O I
cpu_rnw FB1_14 7 GCK/I/O I
cs1 FB3_15 20 I/O I
extclk FB1_11 6 GCK/I/O I
spi_int<0> FB2_14 42 GTS/I/O I
spi_int<1> FB2_11 40 GTS/I/O I
spi_int<2> FB2_9 39 GSR/I/O I
spi_int<3> FB1_2 1 I/O I
spi_miso<0> FB2_17 44 I/O I
spi_miso<1> FB2_15 43 I/O I
spi_miso<2> FB2_8 38 I/O I
spi_miso<3> FB2_6 37 I/O I
spi_int FB2_14 42 GTS/I/O I
spi_miso FB2_17 44 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 18 35 35 85 0/5 9
FB2 2 16 16 12 1/0 9
FB3 18 38 38 70 1/3 9
FB4 18 38 38 80 6/0 7
FB1 17 31 31 78 0/5 9
FB2 17 30 30 67 1/0 9
FB3 4 14 14 11 1/3 9
FB4 12 31 31 46 3/0 7
---- ----- ----- -----
56 247 8/8 34
50 202 5/8 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 35/19
Number of signals used by logic mapping into function block: 35
Number of function block inputs used/remaining: 31/23
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
spidataout<3> 4 0 0 1 FB1_1 STD (b) (b)
spidataout<2> 4 0 0 1 FB1_2 STD 1 I/O I
(unused) 0 0 0 5 FB1_1 (b)
spidataout<2> 4 0 0 1 FB1_2 STD 1 I/O (b)
spidataout<1> 4 0 0 1 FB1_3 STD (b) (b)
spidataout<0> 4 0 0 1 FB1_4 STD (b) (b)
cpu_d<0> 5 0 0 0 FB1_5 STD 2 I/O I/O
cpu_d<1> 5 0 0 0 FB1_6 STD 3 I/O I/O
cpu_d<1> 4 0 0 1 FB1_6 STD 3 I/O I/O
tmo 5 0 0 0 FB1_7 STD (b) (b)
cpu_d<2> 5 0 0 0 FB1_8 STD 4 I/O I/O
slaveinten<0> 5 0 0 0 FB1_9 STD 5 GCK/I/O I
cpu_d<2> 4 0 0 1 FB1_8 STD 4 I/O I/O
slaveinten 5 0 0 0 FB1_9 STD 5 GCK/I/O I
frx 5 0 0 0 FB1_10 STD (b) (b)
ece 5 0 0 0 FB1_11 STD 6 GCK/I/O I
divisor<2> 5 0 0 0 FB1_12 STD (b) (b)
divisor<1> 5 0 0 0 FB1_13 STD (b) (b)
divisor<0> 5 0 0 0 FB1_14 STD 7 GCK/I/O I
cpu_d<3> 4 0 0 1 FB1_15 STD 8 I/O I/O
cpu_d<3> 3 0 0 2 FB1_15 STD 8 I/O I/O
cpol 5 0 0 0 FB1_16 STD (b) (b)
cpu_d<4> 5 0 0 0 FB1_17 STD 9 I/O I/O
cpha 5 0 0 0 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: cpu_d<0>.PIN 13: cpu_rnw 25: spi_int<0>
2: cpu_d<1>.PIN 14: cs1 26: spidatain<0>
3: cpu_d<2>.PIN 15: divisor<0> 27: spidatain<1>
4: cpu_d<3>.PIN 16: divisor<1> 28: spidatain<2>
5: cpu_d<4>.PIN 17: divisor<2> 29: spidatain<3>
6: Ncs2 18: ece 30: spidatain<4>
7: cpha 19: frx 31: spidataout<0>
8: cpol 20: slaveinten<0> 32: spidataout<1>
9: cpu_Nphi2 21: spi_Nsel<0> 33: spidataout<2>
10: cpu_Nres 22: spi_Nsel<1> 34: spidataout<3>
11: cpu_a<0> 23: spi_Nsel<2> 35: tmo
12: cpu_a<1> 24: spi_Nsel<3>
1: cpu_d<0>.PIN 12: cpu_a<1> 22: spi_int
2: cpu_d<1>.PIN 13: cpu_rnw 23: spidatain<0>
3: cpu_d<2>.PIN 14: cs1 24: spidatain<1>
4: cpu_d<3>.PIN 15: divisor<0> 25: spidatain<2>
5: cpu_d<4>.PIN 16: divisor<1> 26: spidatain<3>
6: Ncs2 17: divisor<2> 27: spidatain<4>
7: cpha 18: ece 28: spidataout<0>
8: cpol 19: frx 29: spidataout<1>
9: cpu_Nphi2 20: slaveinten 30: spidataout<2>
10: cpu_Nres 21: spi_Nsel 31: tmo
11: cpu_a<0>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
spidataout<3> ...X.X...XXXXX...................X...... 8 8
spidataout<2> ..X..X...XXXXX..................X....... 8 8
spidataout<1> .X...X...XXXXX.................X........ 8 8
spidataout<0> X....X...XXXXX................X......... 8 8
cpu_d<0> .....XX.X.XXXXX.....X....X.............. 10 10
cpu_d<1> .....X.XX.XXXX.X.....X....X............. 10 10
tmo ...X.X...XXXXX....................X..... 8 8
cpu_d<2> .....X..X.XXXX..XX....X....X............ 10 10
slaveinten<0> ....XX...XXXXX.....X.................... 8 8
spidataout<2> ..X..X...XXXXX...............X.......... 8 8
spidataout<1> .X...X...XXXXX..............X........... 8 8
spidataout<0> X....X...XXXXX.............X............ 8 8
cpu_d<0> .....XX.X.XXXXX.....X.X................. 10 10
cpu_d<1> .....X.XX.XXXX.X.......X................ 9 9
tmo ...X.X...XXXXX................X......... 8 8
cpu_d<2> .....X..X.XXXX..XX......X............... 9 9
slaveinten ....XX...XXXXX.....X.................... 8 8
frx ....XX...XXXXX....X..................... 8 8
ece ..X..X...XXXXX...X...................... 8 8
divisor<2> ..X..X...XXXXX..X....................... 8 8
divisor<1> .X...X...XXXXX.X........................ 8 8
divisor<0> X....X...XXXXXX......................... 8 8
cpu_d<3> .....X..X.XXXX.........X....X.....X..... 9 9
cpu_d<3> .....X..X.XXXX...........X....X......... 8 8
cpol .X...X.X.XXXXX.......................... 8 8
cpu_d<4> .....X..X.XXXX....XX....X....X.......... 10 10
cpu_d<4> .....X..X.XXXX....XX.X....X............. 10 10
cpha X....XX..XXXXX.......................... 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
@ -211,44 +197,63 @@ X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 16/38
Number of signals used by logic mapping into function block: 16
Number of function block inputs used/remaining: 30/24
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
start_shifting/start_shifting_RSTF__$INT
1 0 \/2 2 FB2_1 STD (b) (b)
(unused) 0 0 \/5 0 FB2_1 (b) (b)
spi_mosi 11 6<- 0 0 FB2_2 STD 35 I/O O
(unused) 0 0 /\4 1 FB2_3 (b) (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 36 I/O
(unused) 0 0 0 5 FB2_6 37 I/O I
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 38 I/O I
(unused) 0 0 0 5 FB2_9 39 GSR/I/O I
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 40 GTS/I/O I
(unused) 0 0 0 5 FB2_12 (b)
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 42 GTS/I/O I
(unused) 0 0 0 5 FB2_15 43 I/O I
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 44 I/O I
(unused) 0 0 0 5 FB2_18 (b)
shifting2 2 0 /\1 2 FB2_3 STD (b) (b)
shiftdone 3 0 0 2 FB2_4 STD (b) (b)
shiftcnt<0> 3 0 0 2 FB2_5 STD 36 I/O (b)
$OpTx$INV$22__$INT 3 0 0 2 FB2_6 STD 37 I/O (b)
spidatain<7> 4 0 0 1 FB2_7 STD (b) (b)
spidatain<6> 4 0 0 1 FB2_8 STD 38 I/O (b)
spidatain<5> 4 0 0 1 FB2_9 STD 39 GSR/I/O (b)
spidatain<4> 4 0 0 1 FB2_10 STD (b) (b)
spidatain<3> 4 0 0 1 FB2_11 STD 40 GTS/I/O (b)
spidatain<2> 4 0 0 1 FB2_12 STD (b) (b)
spidatain<1> 4 0 0 1 FB2_13 STD (b) (b)
spidatain<0> 4 0 0 1 FB2_14 STD 42 GTS/I/O I
shiftcnt<3> 4 0 0 1 FB2_15 STD 43 I/O (b)
shiftcnt<2> 4 0 0 1 FB2_16 STD (b) (b)
shiftcnt<1> 4 0 0 1 FB2_17 STD 44 I/O I
start_shifting/start_shifting_RSTF__$INT
1 0 0 4 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$22__$INT
7: shifting2 12: spidataout<4>
2: cpu_Nres 8: spidataout<0> 13: spidataout<5>
3: shiftcnt<1> 9: spidataout<1> 14: spidataout<6>
4: shiftcnt<2> 10: spidataout<2> 15: spidataout<7>
5: shiftcnt<3> 11: spidataout<3> 16: tmo
6: shiftdone
11: shifting2 21: spidataout<0>
2: cpu_Nphi2 12: spi_Nsel 22: spidataout<1>
3: cpu_Nres 13: spi_miso 23: spidataout<2>
4: ece 14: spidatain<0> 24: spidataout<3>
5: extclk 15: spidatain<1> 25: spidataout<4>
6: shiftcnt<0> 16: spidatain<2> 26: spidataout<5>
7: shiftcnt<1> 17: spidatain<3> 27: spidataout<6>
8: shiftcnt<2> 18: spidatain<4> 28: spidataout<7>
9: shiftcnt<3> 19: spidatain<5> 29: start_shifting
10: shiftdone 20: spidatain<6> 30: tmo
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
spi_mosi X.X...XXXXX.........XXXXXXXX.X.......... 16 16
shifting2 X........X..................X........... 3 3
shiftdone X.X..XXXX............................... 6 6
shiftcnt<0> X.X..X....X............................. 4 4
$OpTx$INV$22__$INT .X.XX.....X.................X........... 5 5
spidatain<7> X.X..X....X........X.................... 5 5
spidatain<6> X.X..X....X.......X..................... 5 5
spidatain<5> X.X..X....X......X...................... 5 5
spidatain<4> X.X..X....X.....X....................... 5 5
spidatain<3> X.X..X....X....X........................ 5 5
spidatain<2> X.X..X....X...X......................... 5 5
spidatain<1> X.X..X....X..X.......................... 5 5
spidatain<0> X.X..X....XXX........................... 6 6
shiftcnt<3> X.X..XXXX.X............................. 7 7
shiftcnt<2> X.X..XXX..X............................. 6 6
shiftcnt<1> X.X..XX...X............................. 5 5
start_shifting/start_shifting_RSTF__$INT
.X...X.................................. 2 2
spi_mosi XXXXXXXXXXXXXXXX........................ 16 16
..X......X.............................. 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
@ -266,68 +271,43 @@ X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 38/16
Number of signals used by logic mapping into function block: 38
Number of function block inputs used/remaining: 14/40
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
shifting2 2 0 \/1 2 FB3_1 STD (b) (b)
cpu_d<5> 6 1<- 0 0 FB3_2 STD 11 I/O I/O
shiftdone 3 0 0 2 FB3_3 STD (b) (b)
$OpTx$INV$22__$INT 3 0 0 2 FB3_4 STD (b) (b)
cpu_d<6> 5 0 0 0 FB3_5 STD 12 I/O I/O
start_shifting 4 0 0 1 FB3_6 STD (b) (b)
spidatain<7> 4 0 0 1 FB3_7 STD (b) (b)
cpu_d<7> 5 0 0 0 FB3_8 STD 13 I/O I/O
(unused) 0 0 0 5 FB3_1 (b)
cpu_d<5> 4 0 0 1 FB3_2 STD 11 I/O I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
cpu_d<6> 3 0 0 2 FB3_5 STD 12 I/O I/O
(unused) 0 0 0 5 FB3_6 (b)
(unused) 0 0 0 5 FB3_7 (b)
cpu_d<7> 3 0 0 2 FB3_8 STD 13 I/O I/O
cpu_Nirq 1 0 0 4 FB3_9 STD 14 I/O O
spidatain<6> 4 0 0 1 FB3_10 STD (b) (b)
spidatain<5> 4 0 0 1 FB3_11 STD 18 I/O I
spidatain<4> 4 0 0 1 FB3_12 STD (b) (b)
spidatain<3> 4 0 0 1 FB3_13 STD (b) (b)
spidatain<2> 4 0 0 1 FB3_14 STD 19 I/O I
spidatain<1> 4 0 0 1 FB3_15 STD 20 I/O I
shiftcnt<3> 4 0 0 1 FB3_16 STD 24 I/O I
shiftcnt<2> 4 0 0 1 FB3_17 STD 22 I/O I
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
5 0 0 0 FB3_18 STD (b) (b)
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 18 I/O I
(unused) 0 0 0 5 FB3_12 (b)
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 19 I/O I
(unused) 0 0 0 5 FB3_15 20 I/O I
(unused) 0 0 0 5 FB3_16 24 I/O I
(unused) 0 0 0 5 FB3_17 22 I/O I
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$22__$INT
14: shiftcnt<0> 27: spi_int<3>
2: Ncs2 15: shiftcnt<1> 28: spidatain<0>
3: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
16: shiftcnt<2> 29: spidatain<1>
4: cpu_Nphi2 17: shiftcnt<3> 30: spidatain<2>
5: cpu_Nres 18: shiftdone 31: spidatain<3>
6: cpu_a<0> 19: shifting2 32: spidatain<4>
7: cpu_a<1> 20: slaveinten<0> 33: spidatain<5>
8: cpu_rnw 21: slaveinten<1> 34: spidatain<6>
9: cs1 22: slaveinten<2> 35: spidatain<7>
10: ece 23: slaveinten<3> 36: start_shifting
11: extclk 24: spi_int<0> 37: start_shifting/start_shifting_RSTF__$INT
12: frx 25: spi_int<1> 38: tc
13: ier 26: spi_int<2>
1: Ncs2 6: cpu_rnw 11: spidatain<6>
2: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
7: cs1 12: spidatain<7>
3: cpu_Nphi2 8: ier 13: start_shifting
4: cpu_a<0> 9: shifting2 14: tc
5: cpu_a<1> 10: spidatain<5>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
shifting2 X................X.................X.... 3 3
cpu_d<5> .X.X.XXXX.........X.X...X.......X..X.... 11 11
shiftdone X...X........XXXX....................... 6 6
$OpTx$INV$22__$INT ...X.....XX.......X................X.... 5 5
cpu_d<6> .X.X.XXXX...X........X...X.......X...... 10 10
start_shifting .X...XXXX..X.......................XX... 8 8
spidatain<7> X...X........X....X..............X...... 5 5
cpu_d<7> .X.X.XXXX.............X...X.......X..X.. 10 10
cpu_Nirq ..X..................................... 1 1
spidatain<6> X...X........X....X.............X....... 5 5
spidatain<5> X...X........X....X............X........ 5 5
spidatain<4> X...X........X....X...........X......... 5 5
spidatain<3> X...X........X....X..........X.......... 5 5
spidatain<2> X...X........X....X.........X........... 5 5
spidatain<1> X...X........X....X........X............ 5 5
shiftcnt<3> X...X........XXXX.X..................... 7 7
shiftcnt<2> X...X........XXX..X..................... 6 6
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
............X......XXXXXXXX..........X.. 10 10
cpu_d<5> X.XXXXX.XX..X........................... 9 9
cpu_d<6> X.XXXXXX..X............................. 8 8
cpu_d<7> X.XXXXX....X.X.......................... 8 8
cpu_Nirq .X...................................... 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
@ -345,65 +325,59 @@ X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 38/16
Number of signals used by logic mapping into function block: 38
Number of function block inputs used/remaining: 31/23
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
tc 3 0 /\2 0 FB4_1 STD (b) (b)
spi_Nsel<3> 5 0 0 0 FB4_2 STD 25 I/O O
shiftcnt<0> 3 0 0 2 FB4_3 STD (b) (b)
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
2 0 0 3 FB4_1 STD (b) (b)
tc 3 0 0 2 FB4_2 STD 25 I/O (b)
start_shifting 4 0 0 1 FB4_3 STD (b) (b)
spidataout<7> 4 0 0 1 FB4_4 STD (b) (b)
spi_Nsel<2> 5 0 0 0 FB4_5 STD 26 I/O O
spidataout<6> 4 0 0 1 FB4_6 STD (b) (b)
spidataout<5> 4 0 0 1 FB4_7 STD (b) (b)
spi_Nsel<1> 5 0 0 0 FB4_8 STD 27 I/O O
spidataout<4> 4 0 0 1 FB4_9 STD (b) (b)
shiftcnt<1> 4 0 0 1 FB4_10 STD (b) (b)
spi_Nsel<0> 5 0 0 0 FB4_11 STD 28 I/O O
slaveinten<3> 5 0 0 0 FB4_12 STD (b) (b)
slaveinten<2> 5 0 0 0 FB4_13 STD (b) (b)
diag 1 0 \/1 3 FB4_14 STD 29 I/O O
slaveinten<1> 5 1<- \/1 0 FB4_15 STD 33 I/O (b)
ier 5 1<- \/1 0 FB4_16 STD (b) (b)
spidataout<6> 4 0 0 1 FB4_5 STD 26 I/O (b)
spidataout<5> 4 0 0 1 FB4_6 STD (b) (b)
spidataout<4> 4 0 0 1 FB4_7 STD (b) (b)
spidataout<3> 4 0 0 1 FB4_8 STD 27 I/O (b)
ier 5 0 0 0 FB4_9 STD (b) (b)
(unused) 0 0 0 5 FB4_10 (b)
spi_Nsel 5 0 0 0 FB4_11 STD 28 I/O O
(unused) 0 0 0 5 FB4_12 (b)
(unused) 0 0 0 5 FB4_13 (b)
led 1 0 0 4 FB4_14 STD 29 I/O O
(unused) 0 0 0 5 FB4_15 33 I/O
(unused) 0 0 \/1 4 FB4_16 (b) (b)
spi_sclk 6 1<- 0 0 FB4_17 STD 34 I/O O
spidatain<0> 7 2<- 0 0 FB4_18 STD (b) (b)
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: $OpTx$INV$22__$INT
14: cpu_a<0> 27: spi_Nsel<1>
2: cpu_d<0>.PIN 15: cpu_a<1> 28: spi_Nsel<2>
3: cpu_d<1>.PIN 16: cpu_rnw 29: spi_Nsel<3>
4: cpu_d<2>.PIN 17: cs1 30: spi_miso<0>
5: cpu_d<3>.PIN 18: ier 31: spi_miso<1>
6: cpu_d<4>.PIN 19: shiftcnt<0> 32: spi_miso<2>
7: cpu_d<5>.PIN 20: shiftcnt<1> 33: spi_miso<3>
8: cpu_d<6>.PIN 21: shiftdone 34: spidataout<4>
9: cpu_d<7>.PIN 22: shifting2 35: spidataout<5>
10: Ncs2 23: slaveinten<1> 36: spidataout<6>
11: cpha 24: slaveinten<2> 37: spidataout<7>
12: cpol 25: slaveinten<3> 38: start_shifting
13: cpu_Nres 26: spi_Nsel<0>
12: cpu_a<0> 22: spi_Nsel
2: cpu_d<0>.PIN 13: cpu_a<1> 23: spi_int
3: cpu_d<3>.PIN 14: cpu_rnw 24: spidataout<3>
4: cpu_d<4>.PIN 15: cs1 25: spidataout<4>
5: cpu_d<5>.PIN 16: frx 26: spidataout<5>
6: cpu_d<6>.PIN 17: ier 27: spidataout<6>
7: cpu_d<7>.PIN 18: shiftcnt<0> 28: spidataout<7>
8: Ncs2 19: shiftdone 29: start_shifting
9: cpha 20: shifting2 30: start_shifting/start_shifting_RSTF__$INT
10: cpol 21: slaveinten 31: tc
11: cpu_Nres
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
tc .........X...XX.X...X................... 5 5
spi_Nsel<3> ....X....X..XXXXX...........X........... 8 8
shiftcnt<0> X...........X.....X..X.................. 4 4
spidataout<7> ........XX..XXXXX...................X... 8 8
spi_Nsel<2> ...X.....X..XXXXX..........X............ 8 8
spidataout<6> .......X.X..XXXXX..................X.... 8 8
spidataout<5> ......X..X..XXXXX.................X..... 8 8
spi_Nsel<1> ..X......X..XXXXX.........X............. 8 8
spidataout<4> .....X...X..XXXXX................X...... 8 8
shiftcnt<1> X...........X.....XX.X.................. 5 5
spi_Nsel<0> .X.......X..XXXXX........X.............. 8 8
slaveinten<3> ........XX..XXXXX.......X............... 8 8
slaveinten<2> .......X.X..XXXXX......X................ 8 8
diag .....................X...X...........X.. 3 3
slaveinten<1> ......X..X..XXXXX.....X................. 8 8
ier .......X.X..XXXXXX...................... 8 8
spi_sclk X.........XXX.....X.XX.................. 7 7
spidatain<0> X...........X.....X..X...XXXXXXXX....... 12 12
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST
................X...X.X.......X......... 4 4
tc .......X...XX.X...X..................... 5 5
start_shifting .......X...XXXXX............XX.......... 8 8
spidataout<7> ......XX..XXXXX............X............ 8 8
spidataout<6> .....X.X..XXXXX...........X............. 8 8
spidataout<5> ....X..X..XXXXX..........X.............. 8 8
spidataout<4> ...X...X..XXXXX.........X............... 8 8
spidataout<3> ..X....X..XXXXX........X................ 8 8
ier .....X.X..XXXXX.X....................... 8 8
spi_Nsel .X.....X..XXXXX......X.................. 8 8
led ...................X.X......X........... 3 3
spi_sclk X.......XXX......XXX.................... 7 7
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
@ -430,6 +404,8 @@ $OpTx$INV$22__$INT <= ((ece AND NOT extclk)
FTCPE_cpha: FTCPE port map (cpha,cpha_T,cpha_C,NOT cpu_Nres,'0',NOT cpu_rnw);
cpha_T <= ((cpha AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
OR (NOT cpha AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
@ -447,13 +423,7 @@ cpu_Nirq_OE <= cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST;
cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST <= ((ier AND tc)
OR (slaveinten(0) AND NOT spi_int(0))
OR (slaveinten(1) AND NOT spi_int(1))
OR (slaveinten(2) AND NOT spi_int(2))
OR (slaveinten(3) AND NOT spi_int(3)));
diag <= (spi_Nsel(0) AND NOT start_shifting AND NOT shifting2);
OR (slaveinten AND NOT spi_int));
FTCPE_divisor0: FTCPE port map (divisor(0),divisor_T(0),divisor_C(0),NOT cpu_Nres,'0',NOT cpu_rnw);
divisor_T(0) <= ((divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(0).PIN)
@ -481,108 +451,91 @@ frx_T <= ((frx AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
frx_C <= NOT ((cs1 AND NOT Ncs2));
FTCPE_ier: FTCPE port map (ier,ier_T,ier_C,NOT cpu_Nres,'0',NOT cpu_rnw);
ier_T <= ((slaveinten(1).EXP)
ier_T <= ((ier AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(6).PIN)
OR (NOT ier AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(6).PIN));
ier_C <= NOT ((cs1 AND NOT Ncs2));
cpu_d_I(0) <= ((cpu_rnw AND spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpha AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2));
cpu_d_I(0) <= ((cpu_rnw AND spi_Nsel AND cpu_a(1) AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND cpha AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND divisor(0) AND cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(0) <= cpu_d_I(0) when cpu_d_OE(0) = '1' else 'Z';
cpu_d_OE(0) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(1) <= ((cpu_rnw AND spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpol AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2));
cpu_d_I(1) <= ((cpu_rnw AND cpol AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND divisor(1) AND cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(1) <= cpu_d_I(1) when cpu_d_OE(1) = '1' else 'Z';
cpu_d_OE(1) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(2) <= ((cpu_rnw AND spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND ece AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2));
cpu_d_I(2) <= ((cpu_rnw AND ece AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND divisor(2) AND cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(2) <= cpu_d_I(2) when cpu_d_OE(2) = '1' else 'Z';
cpu_d_OE(2) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(3) <= ((cpu_rnw AND spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND tmo AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2));
cpu_d_I(3) <= ((cpu_rnw AND tmo AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(3) <= cpu_d_I(3) when cpu_d_OE(3) = '1' else 'Z';
cpu_d_OE(3) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(4) <= ((cpu_rnw AND frx AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND
NOT spi_int(0) AND cpu_Nphi2));
cpu_d_I(4) <= ((cpu_rnw AND frx AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND slaveinten AND cpu_a(1) AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND cpu_a(1) AND cs1 AND NOT Ncs2 AND NOT cpu_a(0) AND
NOT spi_int AND cpu_Nphi2));
cpu_d(4) <= cpu_d_I(4) when cpu_d_OE(4) = '1' else 'Z';
cpu_d_OE(4) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(5) <= ((shifting2.EXP)
OR (cpu_rnw AND slaveinten(1) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND start_shifting AND NOT cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND NOT Ncs2 AND
cpu_d_I(5) <= ((cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND NOT cpu_a(1) AND start_shifting AND cs1 AND
NOT Ncs2 AND cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND cpu_a(0) AND
shifting2 AND cpu_Nphi2));
cpu_d(5) <= cpu_d_I(5) when cpu_d_OE(5) = '1' else 'Z';
cpu_d_OE(5) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(6) <= ((cpu_rnw AND ier AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND
NOT spi_int(2) AND cpu_Nphi2));
cpu_d_I(6) <= ((cpu_rnw AND ier AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2));
cpu_d(6) <= cpu_d_I(6) when cpu_d_OE(6) = '1' else 'Z';
cpu_d_OE(6) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
cpu_d_I(7) <= ((cpu_rnw AND slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
cs1 AND NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND tc AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND
NOT Ncs2 AND cpu_Nphi2)
OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND
NOT spi_int(3) AND cpu_Nphi2));
cpu_d_I(7) <= ((cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND cs1 AND NOT Ncs2 AND
NOT cpu_a(0) AND cpu_Nphi2)
OR (cpu_rnw AND NOT cpu_a(1) AND tc AND cs1 AND NOT Ncs2 AND
cpu_a(0) AND cpu_Nphi2));
cpu_d(7) <= cpu_d_I(7) when cpu_d_OE(7) = '1' else 'Z';
cpu_d_OE(7) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2);
FDCPE_spi_mosi: FDCPE port map (spi_mosi_I,spi_mosi,NOT $OpTx$INV$22__$INT,'0',NOT cpu_Nres);
spi_mosi <= ((start_shifting/start_shifting_RSTF__$INT.EXP)
OR (EXP6_.EXP)
spi_mosi <= ((EXP6_.EXP)
OR (shifting2.EXP)
OR (shiftcnt(3) AND shiftcnt(2) AND NOT shiftcnt(1) AND
NOT shiftdone AND NOT spidataout(1) AND shifting2)
OR (NOT shiftcnt(3) AND shiftcnt(2) AND NOT shiftcnt(1) AND
@ -593,12 +546,15 @@ spi_mosi_OE <= NOT tmo;
FDCPE_spi_sclk: FDCPE port map (spi_sclk,spi_sclk_D,NOT $OpTx$INV$22__$INT,spi_sclk_CLR,spi_sclk_PRE);
spi_sclk_D <= cpol
XOR
spi_sclk_D <= ((ier.EXP)
spi_sclk_D <= ((EXP7_.EXP)
OR (cpu_Nres AND NOT cpha AND shiftcnt(0) AND NOT shiftdone AND
shifting2));
spi_sclk_CLR <= (NOT cpu_Nres AND NOT cpol);
spi_sclk_PRE <= (NOT cpu_Nres AND cpol);
led <= (spi_Nsel AND NOT start_shifting AND NOT shifting2);
FDCPE_shiftcnt0: FDCPE port map (shiftcnt(0),shiftcnt_D(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0');
shiftcnt_D(0) <= (NOT shiftcnt(0) AND shifting2);
@ -622,65 +578,18 @@ shiftdone_D <= (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(0) AND
FDCPE_shifting2: FDCPE port map (shifting2,shifting2_D,NOT $OpTx$INV$22__$INT,'0','0');
shifting2_D <= (NOT shiftdone AND start_shifting);
FTCPE_slaveinten0: FTCPE port map (slaveinten(0),slaveinten_T(0),slaveinten_C(0),NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T(0) <= ((slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(4).PIN)
OR (NOT slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(4).PIN));
slaveinten_C(0) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_slaveinten: FTCPE port map (slaveinten,slaveinten_T,slaveinten_C,NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T <= ((slaveinten AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN)
OR (NOT slaveinten AND cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN));
slaveinten_C <= NOT ((cs1 AND NOT Ncs2));
FTCPE_slaveinten1: FTCPE port map (slaveinten(1),slaveinten_T(1),slaveinten_C(1),NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T(1) <= ((diag_OBUF.EXP)
OR (NOT slaveinten(1) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(5).PIN));
slaveinten_C(1) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_slaveinten2: FTCPE port map (slaveinten(2),slaveinten_T(2),slaveinten_C(2),NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T(2) <= ((slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(6).PIN)
OR (NOT slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(6).PIN));
slaveinten_C(2) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_slaveinten3: FTCPE port map (slaveinten(3),slaveinten_T(3),slaveinten_C(3),NOT cpu_Nres,'0',NOT cpu_rnw);
slaveinten_T(3) <= ((slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(7).PIN)
OR (NOT slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(7).PIN));
slaveinten_C(3) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel0: FTCPE port map (spi_Nsel(0),spi_Nsel_T(0),spi_Nsel_C(0),'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T(0) <= ((spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(0).PIN)
OR (NOT spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(0).PIN));
spi_Nsel_C(0) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel1: FTCPE port map (spi_Nsel(1),spi_Nsel_T(1),spi_Nsel_C(1),'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T(1) <= ((spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(1).PIN)
OR (NOT spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(1).PIN));
spi_Nsel_C(1) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel2: FTCPE port map (spi_Nsel(2),spi_Nsel_T(2),spi_Nsel_C(2),'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T(2) <= ((spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(2).PIN)
OR (NOT spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(2).PIN));
spi_Nsel_C(2) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel3: FTCPE port map (spi_Nsel(3),spi_Nsel_T(3),spi_Nsel_C(3),'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T(3) <= ((spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND
NOT cpu_d(3).PIN)
OR (NOT spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND
cpu_d(3).PIN));
spi_Nsel_C(3) <= NOT ((cs1 AND NOT Ncs2));
FTCPE_spi_Nsel: FTCPE port map (spi_Nsel,spi_Nsel_T,spi_Nsel_C,'0',NOT cpu_Nres,NOT cpu_rnw);
spi_Nsel_T <= ((spi_Nsel AND cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN)
OR (NOT spi_Nsel AND cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN));
spi_Nsel_C <= NOT ((cs1 AND NOT Ncs2));
FDCPE_spidatain0: FDCPE port map (spidatain(0),spidatain_D(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(0));
spidatain_D(0) <= ((tc.EXP)
OR (NOT spi_Nsel(2) AND spi_miso(2))
OR (NOT spi_Nsel(3) AND spi_miso(3)));
spidatain_D(0) <= (NOT spi_Nsel AND spi_miso);
spidatain_CE(0) <= (shiftcnt(0) AND shifting2);
FDCPE_spidatain1: FDCPE port map (spidatain(1),spidatain(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(1));
@ -705,72 +614,72 @@ FDCPE_spidatain7: FDCPE port map (spidatain(7),spidatain(6),NOT $OpTx$INV$22__$I
spidatain_CE(7) <= (shiftcnt(0) AND shifting2);
FTCPE_spidataout0: FTCPE port map (spidataout(0),spidataout_T(0),spidataout_C(0),'0','0',spidataout_CE(0));
spidataout_T(0) <= ((spidataout(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
spidataout_T(0) <= ((NOT cpu_a(1) AND spidataout(0) AND NOT cpu_a(0) AND
NOT cpu_d(0).PIN)
OR (NOT spidataout(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
OR (NOT cpu_a(1) AND NOT spidataout(0) AND NOT cpu_a(0) AND
cpu_d(0).PIN));
spidataout_C(0) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(0) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout1: FTCPE port map (spidataout(1),spidataout_T(1),spidataout_C(1),'0','0',spidataout_CE(1));
spidataout_T(1) <= ((spidataout(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
spidataout_T(1) <= ((NOT cpu_a(1) AND spidataout(1) AND NOT cpu_a(0) AND
NOT cpu_d(1).PIN)
OR (NOT spidataout(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
OR (NOT cpu_a(1) AND NOT spidataout(1) AND NOT cpu_a(0) AND
cpu_d(1).PIN));
spidataout_C(1) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(1) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout2: FTCPE port map (spidataout(2),spidataout_T(2),spidataout_C(2),'0','0',spidataout_CE(2));
spidataout_T(2) <= ((spidataout(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
spidataout_T(2) <= ((NOT cpu_a(1) AND spidataout(2) AND NOT cpu_a(0) AND
NOT cpu_d(2).PIN)
OR (NOT spidataout(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
OR (NOT cpu_a(1) AND NOT spidataout(2) AND NOT cpu_a(0) AND
cpu_d(2).PIN));
spidataout_C(2) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(2) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout3: FTCPE port map (spidataout(3),spidataout_T(3),spidataout_C(3),'0','0',spidataout_CE(3));
spidataout_T(3) <= ((spidataout(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
spidataout_T(3) <= ((NOT cpu_a(1) AND spidataout(3) AND NOT cpu_a(0) AND
NOT cpu_d(3).PIN)
OR (NOT spidataout(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
OR (NOT cpu_a(1) AND NOT spidataout(3) AND NOT cpu_a(0) AND
cpu_d(3).PIN));
spidataout_C(3) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(3) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout4: FTCPE port map (spidataout(4),spidataout_T(4),spidataout_C(4),'0','0',spidataout_CE(4));
spidataout_T(4) <= ((spidataout(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
spidataout_T(4) <= ((NOT cpu_a(1) AND spidataout(4) AND NOT cpu_a(0) AND
NOT cpu_d(4).PIN)
OR (NOT spidataout(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
OR (NOT cpu_a(1) AND NOT spidataout(4) AND NOT cpu_a(0) AND
cpu_d(4).PIN));
spidataout_C(4) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(4) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout5: FTCPE port map (spidataout(5),spidataout_T(5),spidataout_C(5),'0','0',spidataout_CE(5));
spidataout_T(5) <= ((spidataout(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
spidataout_T(5) <= ((NOT cpu_a(1) AND spidataout(5) AND NOT cpu_a(0) AND
NOT cpu_d(5).PIN)
OR (NOT spidataout(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
OR (NOT cpu_a(1) AND NOT spidataout(5) AND NOT cpu_a(0) AND
cpu_d(5).PIN));
spidataout_C(5) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(5) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout6: FTCPE port map (spidataout(6),spidataout_T(6),spidataout_C(6),'0','0',spidataout_CE(6));
spidataout_T(6) <= ((spidataout(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
spidataout_T(6) <= ((NOT cpu_a(1) AND spidataout(6) AND NOT cpu_a(0) AND
NOT cpu_d(6).PIN)
OR (NOT spidataout(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
OR (NOT cpu_a(1) AND NOT spidataout(6) AND NOT cpu_a(0) AND
cpu_d(6).PIN));
spidataout_C(6) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(6) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_spidataout7: FTCPE port map (spidataout(7),spidataout_T(7),spidataout_C(7),'0','0',spidataout_CE(7));
spidataout_T(7) <= ((spidataout(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
spidataout_T(7) <= ((NOT cpu_a(1) AND spidataout(7) AND NOT cpu_a(0) AND
NOT cpu_d(7).PIN)
OR (NOT spidataout(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND
OR (NOT cpu_a(1) AND NOT spidataout(7) AND NOT cpu_a(0) AND
cpu_d(7).PIN));
spidataout_C(7) <= NOT ((cs1 AND NOT Ncs2));
spidataout_CE(7) <= (cpu_Nres AND NOT cpu_rnw);
FTCPE_start_shifting: FTCPE port map (start_shifting,start_shifting_T,start_shifting_C,NOT start_shifting/start_shifting_RSTF__$INT,'0');
start_shifting_T <= ((NOT cpu_rnw AND NOT start_shifting AND NOT cpu_a(1) AND NOT cpu_a(0))
OR (frx AND NOT start_shifting AND NOT cpu_a(1) AND NOT cpu_a(0)));
start_shifting_T <= ((NOT cpu_rnw AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0))
OR (frx AND NOT cpu_a(1) AND NOT start_shifting AND NOT cpu_a(0)));
start_shifting_C <= NOT ((cs1 AND NOT Ncs2));
@ -814,13 +723,13 @@ Device : XC9572XL-10-PC44
Pin Signal Pin Signal
No. Name No. Name
1 spi_int<3> 23 GND
1 TIE 23 GND
2 cpu_d<0> 24 cpu_a<1>
3 cpu_d<1> 25 spi_Nsel<3>
4 cpu_d<2> 26 spi_Nsel<2>
5 cpu_Nphi2 27 spi_Nsel<1>
6 extclk 28 spi_Nsel<0>
7 cpu_rnw 29 diag
3 cpu_d<1> 25 TIE
4 cpu_d<2> 26 TIE
5 cpu_Nphi2 27 TIE
6 extclk 28 spi_Nsel
7 cpu_rnw 29 led
8 cpu_d<3> 30 TDO
9 cpu_d<4> 31 GND
10 GND 32 VCC
@ -828,14 +737,14 @@ No. Name No. Name
12 cpu_d<6> 34 spi_sclk
13 cpu_d<7> 35 spi_mosi
14 cpu_Nirq 36 TIE
15 TDI 37 spi_miso<3>
16 TMS 38 spi_miso<2>
17 TCK 39 spi_int<2>
18 Ncs2 40 spi_int<1>
15 TDI 37 TIE
16 TMS 38 TIE
17 TCK 39 TIE
18 Ncs2 40 TIE
19 cpu_Nres 41 VCC
20 cs1 42 spi_int<0>
21 VCC 43 spi_miso<1>
22 cpu_a<0> 44 spi_miso<0>
20 cs1 42 spi_int
21 VCC 43 TIE
22 cpu_a<0> 44 spi_miso
Legend : NC = Not Connected, unbonded pin

54
spi6502b.syr
View File

@ -1,10 +1,10 @@
Release 6.3.03i - xst G.38
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s
CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
--> Reading design: spi6502b.prj
@ -67,14 +67,14 @@ wysiwyg : NO
* HDL Compilation *
=========================================================================
Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work.
Architecture behavioral of Entity spi6502b is up to date.
Entity <spi6502b> (Architecture <behavioral>) compiled.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <spi6502b> (Architecture <behavioral>).
INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 203: Mux is complete : default of case is discarded
INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 320: Mux is complete : default of case is discarded
INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 316: Mux is complete : default of case is discarded
Entity <spi6502b> analyzed. Unit <spi6502b> generated.
@ -101,17 +101,17 @@ Synthesizing Unit <spi6502b>.
Found 4-bit register for signal <shiftcnt>.
Found 1-bit register for signal <shiftdone>.
Found 1-bit register for signal <shifting2>.
Found 4-bit register for signal <slaveinten>.
Found 4-bit register for signal <slavesel>.
Found 1-bit register for signal <slaveinten>.
Found 1-bit register for signal <slavesel>.
Found 8-bit register for signal <spidatain>.
Found 8-bit register for signal <spidataout>.
Found 1-bit register for signal <start_shifting>.
Found 1-bit register for signal <tc>.
Found 1-bit register for signal <tmo>.
Found 30 1-bit 2-to-1 multiplexers.
Found 24 1-bit 2-to-1 multiplexers.
Summary:
inferred 1 Counter(s).
inferred 18 D-type flip-flop(s).
inferred 20 D-type flip-flop(s).
inferred 1 Adder/Subtracter(s).
inferred 10 Tristate(s).
Unit <spi6502b> synthesized.
@ -133,10 +133,10 @@ Macro Statistics
# Adders/Subtractors : 1
4-bit adder : 1
# Registers : 25
1-bit register : 20
1-bit register : 22
8-bit register : 1
3-bit register : 1
4-bit register : 3
4-bit register : 1
# Multiplexers : 12
2-to-1 multiplexer : 12
# Tristates : 3
@ -169,11 +169,11 @@ Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 32
# IOs : 23
Macro Statistics :
# Registers : 74
# 1-bit register : 74
# Registers : 60
# 1-bit register : 60
# Tristates : 3
# 1-bit tristate buffer : 2
# 8-bit tristate buffer : 1
@ -181,35 +181,33 @@ Macro Statistics :
# 1-bit xor2 : 5
Cell Usage :
# BELS : 320
# AND2 : 156
# AND3 : 2
# BELS : 252
# AND2 : 119
# AND3 : 5
# AND4 : 1
# GND : 1
# INV : 95
# OR2 : 56
# INV : 77
# OR2 : 42
# OR3 : 1
# OR4 : 1
# OR5 : 1
# VCC : 1
# XOR2 : 5
# FlipFlops/Latches : 43
# FlipFlops/Latches : 37
# FD : 1
# FDC : 5
# FDCE : 30
# FDCE : 27
# FDCP : 1
# FDP : 1
# FDPE : 5
# IO Buffers : 32
# IBUF : 16
# FDPE : 2
# IO Buffers : 23
# IBUF : 10
# IOBUFE : 8
# OBUF : 6
# OBUF : 3
# OBUFE : 2
=========================================================================
CPU : 0.67 / 1.11 s | Elapsed : 1.00 / 1.00 s
CPU : 0.65 / 1.07 s | Elapsed : 0.00 / 1.00 s
-->
Total memory usage is 68952 kilobytes
Total memory usage is 68376 kilobytes

5061
spi6502b.vm6
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File diff suppressed because it is too large Load Diff

2
spi6502b.xml
View File

File diff suppressed because one or more lines are too long

28
spi6502b_pad.csv
View File

@ -1,7 +1,7 @@
Release 6.1i - Fit G.38
Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
5- 6-2017 5:27PM
5- 6-2017 5:47PM
NOTE: This file is designed to be imported into a spreadsheet program
such as Microsoft Excel for viewing, printing and sorting. The comma ','
@ -18,7 +18,7 @@ Pinout by Pin Number:
-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint,
P1,spi_int<3>,I,I/O,INPUT,,,,,,,,,
P1,TIE,,I/O,,,,,,,,,,
P2,cpu_d<0>,I/O,I/O,BIDIR,,,,,,,,,
P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,,
P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,,
@ -42,11 +42,11 @@ P21,VCC,,VCCINT,,,,,,,,,,
P22,cpu_a<0>,I,I/O,INPUT,,,,,,,,,
P23,GND,,GND,,,,,,,,,,
P24,cpu_a<1>,I,I/O,INPUT,,,,,,,,,
P25,spi_Nsel<3>,O,I/O,OUTPUT,,,,,,,,,
P26,spi_Nsel<2>,O,I/O,OUTPUT,,,,,,,,,
P27,spi_Nsel<1>,O,I/O,OUTPUT,,,,,,,,,
P28,spi_Nsel<0>,O,I/O,OUTPUT,,,,,,,,,
P29,diag,O,I/O,OUTPUT,,,,,,,,,
P25,TIE,,I/O,,,,,,,,,,
P26,TIE,,I/O,,,,,,,,,,
P27,TIE,,I/O,,,,,,,,,,
P28,spi_Nsel,O,I/O,OUTPUT,,,,,,,,,
P29,led,O,I/O,OUTPUT,,,,,,,,,
P30,TDO,,TDO,,,,,,,,,,
P31,GND,,GND,,,,,,,,,,
P32,VCC,,VCCIO,,,,,,,,,,
@ -54,14 +54,14 @@ P33,TIE,,I/O,,,,,,,,,,
P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,,
P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,,
P36,TIE,,I/O,,,,,,,,,,
P37,spi_miso<3>,I,I/O,INPUT,,,,,,,,,
P38,spi_miso<2>,I,I/O,INPUT,,,,,,,,,
P39,spi_int<2>,I,I/O/GSR,INPUT,,,,,,,,,
P40,spi_int<1>,I,I/O/GTS2,INPUT,,,,,,,,,
P37,TIE,,I/O,,,,,,,,,,
P38,TIE,,I/O,,,,,,,,,,
P39,TIE,,I/O/GSR,,,,,,,,,,
P40,TIE,,I/O/GTS2,,,,,,,,,,
P41,VCC,,VCCINT,,,,,,,,,,
P42,spi_int<0>,I,I/O/GTS1,INPUT,,,,,,,,,
P43,spi_miso<1>,I,I/O,INPUT,,,,,,,,,
P44,spi_miso<0>,I,I/O,INPUT,,,,,,,,,
P42,spi_int,I,I/O/GTS1,INPUT,,,,,,,,,
P43,TIE,,I/O,,,,,,,,,,
P44,spi_miso,I,I/O,INPUT,,,,,,,,,
To preserve the pinout above for future design iterations in
Project Navigator simply execute the (Lock Pins) process

1 Release 6.1i - Fit G.38
2 Copyright(c) 1995-2003 Xilinx Inc. All rights reserved
3 5- 6-2017 5:27PM 5- 6-2017 5:47PM
4 NOTE: This file is designed to be imported into a spreadsheet program
5 such as Microsoft Excel for viewing, printing and sorting. The comma ','
6 character is used as the data field separator.
7 This file is also designed to support parsing.
18 P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,,
19 P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,,
20 P5,cpu_Nphi2,I,I/O/GCK1,INPUT,,,,,,,,,
21 P6,extclk,I,I/O/GCK2,INPUT,,,,,,,,,
22 P7,cpu_rnw,I,I/O/GCK3,INPUT,,,,,,,,,
23 P8,cpu_d<3>,I/O,I/O,BIDIR,,,,,,,,,
24 P9,cpu_d<4>,I/O,I/O,BIDIR,,,,,,,,,
42 P27,spi_Nsel<1>,O,I/O,OUTPUT,,,,,,,,, P27,TIE,,I/O,,,,,,,,,,
43 P28,spi_Nsel<0>,O,I/O,OUTPUT,,,,,,,,, P28,spi_Nsel,O,I/O,OUTPUT,,,,,,,,,
44 P29,diag,O,I/O,OUTPUT,,,,,,,,, P29,led,O,I/O,OUTPUT,,,,,,,,,
45 P30,TDO,,TDO,,,,,,,,,,
46 P31,GND,,GND,,,,,,,,,,
47 P32,VCC,,VCCIO,,,,,,,,,,
48 P33,TIE,,I/O,,,,,,,,,,
49 P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,,
50 P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,,
51 P36,TIE,,I/O,,,,,,,,,,
52 P37,spi_miso<3>,I,I/O,INPUT,,,,,,,,, P37,TIE,,I/O,,,,,,,,,,
54 P39,spi_int<2>,I,I/O/GSR,INPUT,,,,,,,,, P39,TIE,,I/O/GSR,,,,,,,,,,
55 P40,spi_int<1>,I,I/O/GTS2,INPUT,,,,,,,,, P40,TIE,,I/O/GTS2,,,,,,,,,,
56 P41,VCC,,VCCINT,,,,,,,,,,
57 P42,spi_int<0>,I,I/O/GTS1,INPUT,,,,,,,,, P42,spi_int,I,I/O/GTS1,INPUT,,,,,,,,,
58 P43,spi_miso<1>,I,I/O,INPUT,,,,,,,,, P43,TIE,,I/O,,,,,,,,,,
59 P44,spi_miso<0>,I,I/O,INPUT,,,,,,,,, P44,spi_miso,I,I/O,INPUT,,,,,,,,,
60 To preserve the pinout above for future design iterations in
61 Project Navigator simply execute the (Lock Pins) process
62 located under the (Implement Design) process in a toolbox named
63 (Optional Implementation Tools) or invoke PIN2UCF from the
64 command line. The location constraints will be written into your
65 specified UCF file
66
67