mirror of
https://github.com/freitz85/AppleIISd.git
synced 2024-11-25 02:32:14 +00:00
Expected results added to AddressDecoder simulation
This commit is contained in:
Florian Reitz
parent
7a0480f05e
commit
70c0c118fc
@ -68,7 +68,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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signal CLK : std_logic := '0';
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signal PHI0 : std_logic := '1';
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--Outputs
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--Outputs
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signal B : std_logic_vector(10 downto 8);
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signal DATA_EN : std_logic;
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signal NG : std_logic;
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@ -80,7 +80,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: AddressDecoder PORT MAP (
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A => A,
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B => B,
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@ -100,10 +100,10 @@ BEGIN
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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PHI0_process :process(CLK)
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@ -120,7 +120,7 @@ BEGIN
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-- Stimulus process
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stim_proc: process
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begin
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begin
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-- hold reset state.
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wait for CLK_period * 10;
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NRESET <= '0';
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@ -128,8 +128,10 @@ BEGIN
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NRESET <= '1';
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wait for CLK_period * 10;
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-- insert stimulus here
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-- C0nX access
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-- NG must be '0"
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-- NOE must be '1'
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-- NWE must be '1'
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A <= "0000"; -- must become "000"
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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@ -137,7 +139,10 @@ BEGIN
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NDEV_SEL <= '1';
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wait until rising_edge(PHI0);
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-- CnXX access
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-- CnXX access, select
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-- NG must be '0'
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-- NOE must be '0'
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-- NWE must be '1'
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A <= "0100"; -- must become "000"
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wait until rising_edge(PHI0);
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NIO_SEL <= '0';
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@ -146,14 +151,20 @@ BEGIN
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wait until rising_edge(PHI0);
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-- C8xx access, selected
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-- NG must be '0'
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-- NOE must be '0'
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-- NWE must be '1'
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A <= "1000"; -- must become "001"
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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-- C8xx write access, selected
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-- C8xx write access, selected
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-- NG must be '0'
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-- NOE must be '1'
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-- NWE must be '0'
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RNW <= '0';
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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@ -162,6 +173,9 @@ BEGIN
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wait until rising_edge(PHI0);
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-- C9xx access, selected
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-- NG must be '0'
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-- NOE must be '0'
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-- NWE must be '1'
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RNW <= '1';
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A <= "1001"; -- must become "010"
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wait until rising_edge(PHI0);
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@ -169,8 +183,11 @@ BEGIN
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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-- C9xx access write, selected
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-- C9xx access write, selected
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-- NG must be '0'
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-- NOE must be '1'
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-- NWE must be '0'
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RNW <= '0';
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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@ -179,6 +196,9 @@ BEGIN
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wait until rising_edge(PHI0);
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-- CPLD access
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-- NG must be '0'
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-- NOE must be '1'
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-- NWE must be '1'
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RNW <= '1';
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A <= "0101"; -- must become "000"
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wait until rising_edge(PHI0);
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@ -188,6 +208,9 @@ BEGIN
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wait until rising_edge(PHI0);
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-- CFFF access
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-- NG must be '1'
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-- NOE must be '1'
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-- NWE must be '1'
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A <= "1111"; -- must become "111"
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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@ -196,6 +219,9 @@ BEGIN
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wait until rising_edge(PHI0);
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-- C8xx access, unselected
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-- NG must be '1'
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-- NOE must be '1'
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-- NWE must be '1'
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A <= "1000"; -- must become "001"
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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@ -16,35 +16,28 @@
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<files>
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<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
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</file>
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<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
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</file>
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<file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="AddressDecoder_old_Test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="52"/>
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</file>
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</files>
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<properties>
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@ -159,8 +152,8 @@
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<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -170,7 +163,7 @@
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<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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@ -205,7 +198,7 @@
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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