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AppleIISd
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Fix in VQ44 pinning

This commit is contained in:
Florian Reitz 2019-06-02 19:28:51 +02:00
parent 26909735ae
commit 93cd52b99c
7 changed files with 1110 additions and 1130 deletions
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4
.gitignore vendored
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@ -215,3 +215,7 @@ Hardware/SD_A2\.b\$1
VHDL/_pace\.ucf
VHDL/AppleIISd\.tim
VHDL/AppleIISd\.jed

1046
VHDL/AppleIISd_PC44.jed → AppleIISd_PC44.jed
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File diff suppressed because it is too large Load Diff

1074
VHDL/AppleIISd_VQ44.jed → AppleIISd_VQ44.jed
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File diff suppressed because it is too large Load Diff

BIN
VHDL/AppleIISd.ipf
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Binary file not shown.

4
VHDL/AppleIISd_VQ44.ucf Normal file → Executable file
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@ -5,8 +5,8 @@ NET "ADD_HIGH<10>" LOC = "P32" ;
NET "ADD_HIGH<11>" LOC = "P38" ;
NET "ADD_HIGH<8>" LOC = "P30" ;
NET "ADD_HIGH<9>" LOC = "P31" ;
NET "ADD_LOW<0>" LOC = "P12" ;
NET "ADD_LOW<1>" LOC = "P13" ;
NET "ADD_LOW<0>" LOC = "P13" ;
NET "ADD_LOW<1>" LOC = "P12" ;
NET "B<10>" LOC = "P16" ;
NET "B<8>" LOC = "P20" ;
NET "B<9>" LOC = "P21" ;

12
VHDL/AppleIISd_VQ44.xise Normal file → Executable file
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@ -105,7 +105,7 @@
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="non-default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
@ -114,7 +114,7 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@ -177,9 +177,9 @@
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
@ -194,7 +194,7 @@
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="AppleIISd.ipf" xil_pn:valueState="non-default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="AppleIISd_VQ44.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->

32
VHDL/SpiController.vhd Normal file → Executable file
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@ -28,9 +28,6 @@ Port (
pgm_en : out STD_LOGIC;
led : out STD_LOGIC
);
constant DIV_WIDTH : integer := 3;
end SpiController;
architecture Behavioral of SpiController is
@ -49,7 +46,6 @@ architecture Behavioral of SpiController is
signal frx: std_logic; -- fast receive mode
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic := '1'; -- slave select output (0=selected)
signal int_miso: std_logic;
--------------------------
@ -63,8 +59,6 @@ architecture Behavioral of SpiController is
-- spi clock
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
-- TODO divcnt is not used at all??
--signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic;
begin
@ -172,22 +166,8 @@ begin
clksrc <= phi0 when (ece = '0') else clk;
-- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0';
shiftclk <= clksrc when bsy = '1' else '0';
-- clkgen: process(nreset, divisor, clksrc)
-- begin
-- if (nreset = '0') then
-- divcnt <= divisor;
-- elsif (falling_edge(clksrc)) then
-- if (shiftclk = '1') then
-- divcnt <= divisor;
-- else
-- divcnt <= divcnt - 1;
-- end if;
-- end if;
-- end process;
--------------------------
-- interface section
-- inputs
@ -210,7 +190,7 @@ begin
-- cpu register section
-- cpu read
cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen,
ece, divisor, slavesel, wp, card, sdhc, inited)
ece, slavesel, wp, card, sdhc, inited)
begin
case addr is
when "00" => -- read SPI data in
@ -224,9 +204,7 @@ begin
data_out(5) <= bsy;
data_out(6) <= '0';
data_out(7) <= tc;
when "10" => -- read sclk divisor
data_out(DIV_WIDTH-1 downto 0) <= divisor;
data_out(7 downto 3) <= (others => '0');
-- no register 2
when "11" => -- read slave select / slave interrupt state
data_out(0) <= slavesel;
data_out(3 downto 1) <= (others => '0');
@ -246,7 +224,6 @@ begin
ece <= '0';
frx <= '0';
slavesel <= '1';
divisor <= (others => '0');
spidataout <= (others => '1');
sdhc <= '0';
inited <= '0';
@ -263,9 +240,8 @@ begin
ece <= data_in(2);
frx <= data_in(4);
-- no bit 5 - 7
when "10" => -- write divisor
divisor <= data_in(DIV_WIDTH-1 downto 0);
when "11" => -- write slave select / slave interrupt enable
-- no register 2
when "11" => -- write slave select
slavesel <= data_in(0);
-- no bit 1 - 3
sdhc <= data_in(4);