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Merge branch 'master' into flasher
This commit is contained in:
commit
a5e673888f
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.gitignore
vendored
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.gitignore
vendored
@ -219,3 +219,5 @@ VHDL/_pace\.ucf
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VHDL/AppleIISd\.tim
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VHDL/AppleIISd\.jed
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Firmware/AppleIISd.bin
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@ -48,7 +48,6 @@ KNOWNRTS := $FF58
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OAPPLE := $C061 ; open apple key
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DATA := $C080
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CTRL := DATA+1
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DIV := DATA+2
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SS := DATA+3
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; Constants
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@ -1,10 +1,10 @@
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;*******************************
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;
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; Apple][Sd Firmware
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; Version 1.2.1
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; Version 1.2.2
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; Main source
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;
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; (c) Florian Reitz, 2017 - 2018
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; (c) Florian Reitz, 2017 - 2020
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;
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; X register usually contains SLOT16
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; Y register is used for counting or SLOT
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@ -228,13 +228,9 @@ DRIVER: CLC ; ProDOS entry
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;*******************************
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.segment "EXTROM"
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INIT: LDA #$03 ; set SPI mode 3
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STA CTRL,X
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LDA SS,X
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ORA #SS0 ; set CS high
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INIT: STZ CTRL,X ; reset SPI controller
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LDA #SS0 ; set CS high
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STA SS,X
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LDA #7 ; set 400 kHz
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STA DIV,X
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LDY #10
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LDA #DUMMY
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@ -362,13 +358,13 @@ INIT: LDA #$03 ; set SPI mode 3
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@END1: LDA SS,X ; set CS high
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ORA #SS0
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STA SS,X
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LDA #0 ; set div to 2
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STA DIV,X
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TYA ; retval in A
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RTS
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TEXT: .asciiz " Apple][Sd v1.2.1 (c)2018 Florian Reitz "
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TEXT: .asciiz " Apple][Sd v1.2.2 (c)2020 Florian Reitz"
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.assert(*-TEXT)=40, error, "TEXT must be 40 bytes long"
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CMD0: .byt $40, $00, $00
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.byt $00, $00, $95
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@ -112,6 +112,8 @@ The control registers of the *AppleIISd* are mapped to the usual I/O space at **
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**DATA** SPI data register - Is used for both input and output. When the register is written to, the controller will output the byte on the SPI bus. When it is read from, it reflects the data that was received over the SPI bus.
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**PGMEN** Program Enable - Enable programing of the internal firmware eeprom. Should be reset immediately after writing to the device.
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**ECE** External Clock Enable - This bit enables the the external clock input to the SPI controller. In the *AppleIISd*, this effectively switches the SPI clock between 500kHz (ECE = 0) and 3.5MHz (ECE = 1).
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**FRX** Fast Receive mode - When set to 1, fast receive mode triggers shifting upon reading or writing the SPI Data register. When set to 0, shifting is only triggered by writing the SPI data register.
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||||
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