Apple-2-HW
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Apple_II_vhdl
mirror of https://github.com/mandl/Apple_II_vhdl.git
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update scripts 

add testbench
This commit is contained in:
Stefan 2016-01-09 20:01:56 +01:00
parent e8b646bcbd
commit a906b119f4
13 changed files with 351 additions and 107 deletions
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1
.gitignore vendored
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@ -58,6 +58,7 @@ xlnx_auto_0_xdb/
xst/
_ngo/
_xmsgs/
.Xil/
# cmake
build/

120
Apple2.xise
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@ -16,114 +16,139 @@
<files>
<file xil_pn:name="src/cpu6502.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="src/character_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="src/disk_ii_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="src/character_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="build/disk_ii_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="src/disk_ii.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="src/spi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="src/vga_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="src/video_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="src/apple2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="src/timing_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="src/papilio_duo.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="src/cpu_hexy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="src/disk_disp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="src/grp_debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="build/apple_II_auto_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="src/keyboard_apple.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="src/PS2/Debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="src/PS2/Keyboard.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="src/PS2/KeyboardMapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="src/PS2/PS2Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="src/apple2_top_papilio_duo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="src/dcm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="build/bios_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="src/cpu/t65/T65_ALU.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="src/cpu/t65/T65_MCode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="src/cpu/t65/T65_Pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="src/cpu/t65/T65.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="src/timing_tb2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<file xil_pn:name="src/tb/timing_tb2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="src/tb/apple2_tb2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="105"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="105"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="src/tb/spi_controller_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="src/papilio-clock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="src/dcm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="vga_controller_tb.bmm" xil_pn:type="FILE_BMM">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="vga_controller_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="94"/>
@ -177,6 +202,7 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="simspi.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
@ -245,7 +271,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|apple2_papilio|datapath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="src/apple2_top_papilio_duo.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../src/apple2_top_papilio_duo.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/apple2_papilio" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -371,8 +397,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/timing_tb2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.timing_tb2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/apple2_papilio_tb/uut/vga" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.vga_controller" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -390,7 +416,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.timing_tb2" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.vga_controller" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -426,7 +452,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/media/mandl/99916a97-93e2-4803-8152-a3f6a3a25698/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
@ -435,12 +461,12 @@
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Working Directory" xil_pn:value="build" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|timing_tb2|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|apple2_papilio_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="Apple2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
@ -451,8 +477,8 @@
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-12-11T12:57:49" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8145CE1F3680A276E84E2AE2A10EAC94" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnderProjDir" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
</properties>
<bindings/>

0
disks/place_disk_here.txt Normal file
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38
make_roms.sh
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@ -1,38 +0,0 @@
#!/bin/sh
# SHA1 checksum
export rom_path_src=./roms
export rom_path=./build
#export tools_path=../build2/romgen
export romgen_path=./romgen_src
#mkdir $rom_path
sha1sum $rom_path_src/apple_II.rom
sha1sum $rom_path_src/APPLE2.ROM
sha1sum $rom_path_src/bios.rom
#341-011-D0 Applesoft BASIC D0
#341-012-D8 Applesoft BASIC D8
#341-013-E0 Applesoft BASIC E0
#341-014-E8 Applesoft BASIC E8
#341-015-F0 Applesoft BASIC F0
#341-020-F8 Autostart Monitor
rm $rom_path_src/apple_II_auto.bin
# autostart rom
cat $rom_path_src/341011d0.bin $rom_path_src/341012d8.bin $rom_path_src/341013e0.bin $rom_path_src/341014e8.bin $rom_path_src/341015f0.bin $rom_path_src/341020f8.bin >> $rom_path_src/apple_II_auto.bin
$romgen_path/romgen $rom_path_src/apple_II_auto.bin apple_II_auto_rom 14 a r > $rom_path/apple_II_auto_rom.vhd
$romgen_path/romgen $rom_path_src/apple_II.rom apple_II_rom 14 a r > $rom_path/apple_II_rom.vhd
$romgen_path/romgen $rom_path_src/APPLE2.ROM APPLE2_ROM 14 a r > $rom_path/APPLE2_ROM.vhd
# test rom
$romgen_path/romgen $rom_path_src/bios.rom bios_rom 14 a r > $rom_path/bios_rom.vhd

0
roms/place_roms_here.txt Normal file
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14
scripts/make_disk_dos33.sh Executable file
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@ -0,0 +1,14 @@
#!/bin/sh
echo Build a SD Card....
export rom_disk_src=../disks
export sd_disk_path=/dev/mmcblk0
echo Copy $rom_path_src/dos33master.nib to $sd_disk_path CD Card
#sudo dd if=$rom_path_src/dos33master.nib of=/dev/mmcblk0
sync

49
scripts/make_roms.sh Executable file
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@ -0,0 +1,49 @@
#!/bin/sh
# 6e36ae20c211cdc8aad36b2ea757fec95874b499 bios.rom
# 0287ebcef2c1ce11dc71be15a99d2d7e0e128b1e 341011d0.bin
# a75ce5aab6401355bf1ab01b04e4946a424879b5 341012d8.bin
# 8d82a1da63224859bd619005fab62c4714b25dd7 341013e0.bin
# 37501be96d36d041667c15d63e0c1eff2f7dd4e9 341014e8.bin
# e6bf91ed28464f42b807f798fc6422e5948bf581 341015f0.bin
# 07a3bdce3e34bbed5246fe09a9938d8f334a8225 341020f8.bin
# SHA1 checksum
export rom_path_src=../roms
export rom_path=../build
export romgen_path=../romgen_src
#mkdir $rom_path
sha1sum $rom_path_src/bios.rom
#341-011-D0 Applesoft BASIC D0
#341-012-D8 Applesoft BASIC D8
#341-013-E0 Applesoft BASIC E0
#341-014-E8 Applesoft BASIC E8
#341-015-F0 Applesoft BASIC F0
#341-020-F8 Autostart Monitor
#3420028A.BIN Disk slot 6
sha1sum $rom_path_src/341011d0.bin
sha1sum $rom_path_src/341012d8.bin
sha1sum $rom_path_src/341013e0.bin
sha1sum $rom_path_src/341014e8.bin
sha1sum $rom_path_src/341015f0.bin
sha1sum $rom_path_src/341020f8.bin
sha1sum $rom_path_src/slot6.rom
rm $rom_path_src/apple_II_auto.bin
# autostart rom
cat $rom_path_src/341011d0.bin $rom_path_src/341012d8.bin $rom_path_src/341013e0.bin $rom_path_src/341014e8.bin $rom_path_src/341015f0.bin $rom_path_src/341020f8.bin >> $rom_path_src/apple_II_auto.bin
$romgen_path/romgen $rom_path_src/apple_II_auto.bin apple_II_auto_rom 14 a r > $rom_path/apple_II_auto_rom.vhd
# test rom
$romgen_path/romgen $rom_path_src/bios.rom bios_rom 14 a r > $rom_path/bios_rom.vhd
# disk rom
$romgen_path/romgen $rom_path_src/slot6.rom slot6_rom 8 a r > $rom_path/slot6_rom1.vhd

28
src/apple2.bmm
View File

@ -1,47 +1,47 @@
ADDRESS_MAP avrmap PPC405 0
ADDRESS_SPACE rom_apple RAMB16 [0x00000000:0x00003fff]
BUS_BLOCK
core/roms/Mram_ROM1 [7:0];
core_auto_rom.roms/Mram_ROM1 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM2 [7:0];
core_auto_rom.roms/Mram_ROM2 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM3 [7:0];
core_auto_rom.roms/Mram_ROM3 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM4 [7:0];
core_auto_rom.roms/Mram_ROM4 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM5 [7:0];
core_auto_rom.roms/Mram_ROM5 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM6 [7:0];
core_auto_rom.roms/Mram_ROM6 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM7 [7:0];
core_auto_rom.roms/Mram_ROM7 [7:0];
END_BUS_BLOCK;
BUS_BLOCK
core/roms/Mram_ROM8 [7:0];
core_auto_rom.roms/Mram_ROM8 [7:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_SPACE;
ADDRESS_SPACE rom_disk RAMB16 [0x00000000:0x000007ff]
BUS_BLOCK
disk/rom/Mram_ROM [7:0];
disk_rom/Mram_ROM [7:0];
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
END_ADDRESS_MAP;

25
src/apple2.vhd
View File

@ -8,6 +8,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.T65_Pack.all;
entity apple2 is
generic (
@ -104,6 +105,8 @@ architecture rtl of apple2 is
signal speaker_sig : std_logic := '0';
signal DL : unsigned(7 downto 0); -- Latched RAM data
signal DEBUG : T_t65_dbg;
begin
@ -301,7 +304,7 @@ end generate;
T65_core: if use_T65_core generate
cpu : entity work.T65 port map (
Mode => "01",
Mode => "00",
Abort_n => '1',
SO_n => '1',
Res_n => not reset,
@ -312,13 +315,29 @@ T65_core: if use_T65_core generate
NMI_n => '1',
R_W_n => R_W_n,
Sync => open,
EF => open,
MF => open,
XF => open,
ML_n => open,
VP_n => open,
VDA => open,
VPA => open,
unsigned(A(23 downto 0)) => A_BIG,
DI(7 downto 0) => std_logic_vector(D_IN),
unsigned(DO(7 downto 0)) => D
DI(7 downto 0) => std_logic_vector(D_IN),
unsigned(DO(7 downto 0)) => D,
DEBUG => DEBUG
);
A <= A_BIG( 15 downto 0);
we <= not R_W_n;
debugOpcode <= unsigned(DEBUG.I); -- instruction
debugA <= unsigned(DEBUG.A); -- A reg
debugX <= unsigned(DEBUG.X); -- X reg
debugY <= unsigned(DEBUG.Y); -- Y reg
debugS <= unsigned(DEBUG.S); -- stack pointer
--<= DEBUG.P; -- processor flags
end generate;
-- Original Apple had asynchronous ROMs. We use a synchronous ROM

2
src/keyboard_apple.vhd
View File

@ -194,7 +194,7 @@ begin
X"3d" when X"145", -- =
X"3e" when X"1C2", -- >
X"3f" when X"14a", -- ?
--X"40" when X"11e", -- @
X"40" when X"215", -- @
X"41" when X"11c", -- A
X"42" when X"132", -- B
X"43" when X"121", -- C

163
src/tb/apple2_tb2.vhd Normal file
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@ -0,0 +1,163 @@
-- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY apple2_papilio_tb IS
END apple2_papilio_tb;
ARCHITECTURE behavior OF apple2_papilio_tb IS
-- Component Declaration
COMPONENT apple2_papilio
port (
-- Clocks
CLK : in std_logic; -- 32 MHz
RESET_I : in std_logic; -- reset positiv
-- SRAM
SRAM_DQ : inout unsigned(7 downto 0); -- Data bus 8 Bits
SRAM_ADDR : out unsigned(20 downto 0); -- Address bus 21 Bits
SRAM_WE_N, -- Write Enable
SRAM_CE_N, -- Chip Enable
SRAM_OE_N : out std_logic; -- Output Enable
-- SD card interface
SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
-- Led
LED : out std_logic_vector(3 downto 0);
-- PS/2 port
PS2_DAT, -- Data
PS2_CLK : inout std_logic; -- Clock
O_AUDIO_L : out std_logic; -- Audio out
O_AUDIO_R : out std_logic; -- Ausdio out
-- VGA output
VGA_HS, -- H_SYNC
VGA_VS : out std_logic; -- V_SYNC
VGA_R, -- Red[3:0]
VGA_G, -- Green[3:0]
VGA_B : out unsigned(3 downto 0) -- Blue[3:0]
);
END COMPONENT;
signal CLK_32M : std_logic;
signal RESET_I : std_logic := '0'; -- reset positiv
-- SRAM
signal SRAM_DQ : unsigned(7 downto 0); -- Data bus 8 Bits
signal SRAM_ADDR : unsigned(20 downto 0); -- Address bus 21 Bits
signal SRAM_WE_N, -- Write Enable
SRAM_CE_N, -- Chip Enable
SRAM_OE_N : std_logic; -- Output Enable
-- SD card interface
signal SD_DAT : std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
signal SD_DAT3 : std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
signal SD_CMD : std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
signal SD_CLK : std_logic; -- SD Card Clock SD pin 5 "CLK"
-- Led
signal LED : std_logic_vector(3 downto 0);
-- PS/2 port
signal PS2_DAT, -- Data
PS2_CLK : std_logic; -- Clock
signal O_AUDIO_L : std_logic; -- Audio out
signal O_AUDIO_R : std_logic; -- Ausdio out
-- VGA output
signal VGA_HS, -- H_SYNC
VGA_VS : std_logic; -- V_SYNC
signal VGA_R, -- Red[3:0]
VGA_G, -- Green[3:0]
VGA_B : unsigned(3 downto 0); -- Blue[3:0]
-- Clock period definitions
constant CLK_32M_period : time := 32.25 ns;
BEGIN
-- Component Instantiation
uut:apple2_papilio PORT MAP(
-- Clocks
CLK => CLK_32M, -- 32 MHz
RESET_I => RESET_I, -- reset positiv
-- SRAM
SRAM_DQ => SRAM_DQ, -- Data bus 8 Bits
SRAM_ADDR => SRAM_ADDR, -- Address bus 21 Bits
SRAM_WE_N => SRAM_WE_N, -- Write Enable
SRAM_CE_N => SRAM_CE_N, -- Chip Enable
SRAM_OE_N => SRAM_OE_N, -- Output Enable
-- SD card interface
SD_DAT => SD_DAT, -- SD Card Data SD pin 7 "DAT 0/DataOut"
SD_DAT3 => SD_DAT3, -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
SD_CMD => SD_CMD, -- SD Card Command SD pin 2 "CMD/DataIn"
SD_CLK => SD_CLK, -- SD Card Clock SD pin 5 "CLK"
-- Led
LED => LED,
-- PS/2 port
PS2_DAT => PS2_DAT,
PS2_CLK => PS2_CLK,
O_AUDIO_L => O_AUDIO_L,
O_AUDIO_R => O_AUDIO_R,
-- VGA output
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_R => VGA_R,
VGA_G => VGA_G, -- Green[3:0]
VGA_B => VGA_B
);
-- Clock process definitions
CLK_32M_process :process
begin
CLK_32M <= '0';
wait for CLK_32M_period/2;
CLK_32M <= '1';
wait for CLK_32M_period/2;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
wait for 100 ns; -- wait until global set/reset completes
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS tb;
-- End Test Bench
END;

0
src/timing_tb2.vhd → src/tb/timing_tb2.vhd
View File

18
src/timing_generator.vhd
View File

@ -139,7 +139,9 @@ begin
end if;
end process;
test : process (CLK_14M)
begin
if rising_edge(CLK_14M) then
H0 <= H(0);
VA <= V(0);
VB <= V(1);
@ -164,11 +166,19 @@ begin
VIDEO_ADDRESS(6 downto 3) <= (not H(5) & V(6) & H(4) & H(3)) +
( V(7) & not H(5) & V(7) & '1') +
( "000" & V(6));
VIDEO_ADDRESS(9 downto 7) <= V(5 downto 3);
VIDEO_ADDRESS(14 downto 10) <=
( "00" & HBL & PAGE2 & not PAGE2) when HIRES = '0' else
(PAGE2 & not PAGE2 & V(2 downto 0));
if HIRES = '0' then
VIDEO_ADDRESS(14 downto 10) <= ("00" & HBL & PAGE2 & not PAGE2);
else
VIDEO_ADDRESS(14 downto 10) <= (PAGE2 & not PAGE2 & V(2 downto 0));
end if;
VIDEO_ADDRESS(15) <= '0';
end if;
end process;
end rtl;