GR8RAM/cpld/db/GR8RAM.tmw_info

start_full_compilation:s:00:00:06
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:01-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation
Fixed previous problem, working again 2020-02-16 00:11:12 -05:00			`start_full_compilation:s:00:00:06`
			`start_analysis_synthesis:s:00:00:02-start_full_compilation`
Made AddrH high bit variable with mode input 2019-09-07 21:16:23 -04:00			`start_analysis_elaboration:s-start_full_compilation`
Fixed previous problem, working again 2020-02-16 00:11:12 -05:00			`start_fitter:s:00:00:01-start_full_compilation`
			`start_assembler:s:00:00:02-start_full_compilation`
Fixed bugs in new PLD stuff 2019-10-20 22:41:24 -04:00			`start_timing_analyzer:s:00:00:01-start_full_compilation`