2019-09-01 02:55:04 +00:00
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|GR8RAM
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2019-10-12 00:34:51 +00:00
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C7M => CAS1r.CLK
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C7M => CAS0r.CLK
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2019-09-01 02:55:04 +00:00
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C7M => RASr.CLK
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C7M => ASel.CLK
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2019-10-12 00:34:51 +00:00
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C7M => IncAddrH.CLK
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C7M => IncAddrM.CLK
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C7M => IncAddrL.CLK
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C7M => FullIOEN.CLK
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C7M => Bank[0].CLK
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C7M => Bank[1].CLK
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C7M => Bank[2].CLK
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C7M => Bank[3].CLK
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C7M => Bank[4].CLK
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C7M => Bank[5].CLK
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C7M => Bank[6].CLK
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C7M => Bank[7].CLK
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C7M => Addr[0].CLK
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C7M => Addr[1].CLK
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C7M => Addr[2].CLK
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C7M => Addr[3].CLK
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C7M => Addr[4].CLK
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C7M => Addr[5].CLK
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C7M => Addr[6].CLK
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C7M => Addr[7].CLK
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C7M => Addr[8].CLK
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C7M => Addr[9].CLK
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C7M => Addr[10].CLK
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C7M => Addr[11].CLK
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C7M => Addr[12].CLK
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C7M => Addr[13].CLK
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C7M => Addr[14].CLK
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C7M => Addr[15].CLK
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C7M => Addr[16].CLK
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C7M => Addr[17].CLK
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C7M => Addr[18].CLK
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C7M => Addr[19].CLK
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C7M => Addr[20].CLK
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C7M => Addr[21].CLK
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C7M => Addr[22].CLK
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C7M => Addr[23].CLK
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2019-09-01 02:55:04 +00:00
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C7M => CSDBEN.CLK
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C7M => IOROMEN.CLK
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C7M => REGEN.CLK
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C7M => Ref[0].CLK
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C7M => Ref[1].CLK
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C7M => Ref[2].CLK
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C7M => Ref[3].CLK
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C7M => S[0].CLK
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C7M => S[1].CLK
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C7M => S[2].CLK
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C7M => PHI0seen.CLK
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C7M => PHI1reg.CLK
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2019-10-12 00:34:51 +00:00
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C7M_2 => always2.IN0
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2019-09-01 02:55:04 +00:00
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Q3 => ~NO_FANOUT~
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PHI0in => ~NO_FANOUT~
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PHI1in => comb.IN0
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PHI1in => PHI1b0_MC.DATAIN
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nRES => always0.IN0
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2019-10-12 00:34:51 +00:00
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nMode => ~NO_FANOUT~
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2019-09-02 01:18:44 +00:00
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A[0] => Equal0.IN7
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A[0] => Equal1.IN7
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A[0] => Equal2.IN7
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2019-09-01 02:55:04 +00:00
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A[0] => Equal3.IN7
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A[0] => Equal4.IN7
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A[0] => Equal5.IN7
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2019-09-02 01:18:44 +00:00
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A[0] => Equal10.IN21
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A[1] => Equal0.IN6
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A[1] => Equal1.IN6
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A[1] => Equal2.IN6
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2019-09-01 02:55:04 +00:00
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A[1] => Equal3.IN6
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A[1] => Equal4.IN6
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A[1] => Equal5.IN6
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2019-09-02 01:18:44 +00:00
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A[1] => Equal10.IN20
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A[2] => Equal0.IN5
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A[2] => Equal1.IN5
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A[2] => Equal2.IN5
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2019-09-01 02:55:04 +00:00
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A[2] => Equal3.IN5
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A[2] => Equal4.IN5
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A[2] => Equal5.IN5
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2019-09-02 01:18:44 +00:00
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A[2] => Equal10.IN19
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A[3] => Equal0.IN4
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A[3] => Equal1.IN4
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A[3] => Equal2.IN4
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2019-09-01 02:55:04 +00:00
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A[3] => Equal3.IN4
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A[3] => Equal4.IN4
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A[3] => Equal5.IN4
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2019-09-02 01:18:44 +00:00
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A[3] => Equal10.IN18
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A[4] => Equal10.IN17
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A[5] => Equal10.IN16
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A[6] => Equal10.IN15
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A[7] => Equal10.IN14
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A[8] => Equal10.IN13
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A[9] => Equal10.IN12
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A[10] => Equal10.IN11
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A[11] => ~NO_FANOUT~
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A[12] => ~NO_FANOUT~
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A[13] => ~NO_FANOUT~
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A[14] => ~NO_FANOUT~
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A[15] => ~NO_FANOUT~
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2019-09-01 02:55:04 +00:00
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RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[10] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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nWE => comb.IN0
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2019-09-02 01:18:44 +00:00
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nWE => comb.IN0
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nWE => comb.IN0
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nWE => comb.IN0
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nWE => comb.IN0
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2019-09-01 02:55:04 +00:00
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nWE => comb.IN0
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2019-09-08 01:16:23 +00:00
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nWE => comb.IN1
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2019-09-01 02:55:04 +00:00
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nWE => CASf.IN1
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D[0] <> D[0]
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D[1] <> D[1]
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D[2] <> D[2]
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D[3] <> D[3]
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D[4] <> D[4]
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D[5] <> D[5]
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D[6] <> D[6]
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D[7] <> D[7]
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RD[0] <> RD[0]
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RD[1] <> RD[1]
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RD[2] <> RD[2]
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RD[3] <> RD[3]
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RD[4] <> RD[4]
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RD[5] <> RD[5]
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RD[6] <> RD[6]
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RD[7] <> RD[7]
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nDEVSEL => comb.IN0
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nDEVSEL => comb.IN0
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nDEVSEL => comb.IN0
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2019-09-02 01:18:44 +00:00
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nDEVSEL => comb.IN0
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nDEVSEL => comb.IN0
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nDEVSEL => comb.IN0
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nDEVSEL => comb.IN0
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nDEVSEL => comb.IN0
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nIOSEL => RA.IN1
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nIOSEL => RA.IN0
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2019-09-01 02:55:04 +00:00
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nIOSEL => comb.IN0
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2019-09-02 01:18:44 +00:00
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nIOSEL => comb.IN1
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nIOSTRB => RA.IN0
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nIOSTRB => RA.IN1
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nIOSTRB => RA.IN1
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2019-09-01 02:55:04 +00:00
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nIOSTRB => comb.IN1
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2019-09-08 01:16:23 +00:00
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nINH <= nINH.DB_MAX_OUTPUT_PORT_TYPE
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2019-09-01 02:55:04 +00:00
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nRAS <= comb.DB_MAX_OUTPUT_PORT_TYPE
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nCAS0 <= comb.DB_MAX_OUTPUT_PORT_TYPE
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nCAS1 <= comb.DB_MAX_OUTPUT_PORT_TYPE
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nRCS <= comb.DB_MAX_OUTPUT_PORT_TYPE
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nROE <= comb.DB_MAX_OUTPUT_PORT_TYPE
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nRWE <= comb.DB_MAX_OUTPUT_PORT_TYPE
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