Apple-2-HW/GR8RAM
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This commit is contained in:
Zane Kaminski 2021-03-19 16:38:48 -04:00
parent e4bfc93b1f
commit 763861e444
51 changed files with 1663 additions and 1640 deletions
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11
cpld/GR8RAM.qsf
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@ -56,4 +56,13 @@ set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name SAFE_STATE_MACHINE ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH

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cpld/GR8RAM.qws Executable file
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cpld/GR8RAM.v
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@ -230,78 +230,81 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
reg RTPBr = 0; // RTPBusy registered to sync with C25M reg RTPBr = 0; // RTPBusy registered to sync with C25M
always @(negedge C25M) begin UFMBr0 <= UFMB; RTPBr0 <= RTPB; end always @(negedge C25M) begin UFMBr0 <= UFMB; RTPBr0 <= RTPB; end
always @(posedge C25M) begin UFMBr <= UFMBr0; RTPBr <= RTPBr0; end always @(posedge C25M) begin UFMBr <= UFMBr0; RTPBr <= RTPBr0; end
reg SetLoaded = 0; reg [1:0] SS = 0;
reg SetFW; reg SetFW;
reg SetLim8M; reg SetLim8M;
always @(posedge C25M) begin always @(posedge C25M) begin
if (~SetLoaded) begin if (SS[1:0]!=2'b11) begin
if (LS[15:0]<=16'h0FB0) begin if (SS[1:0]==2'b10 && LS[3:0]==4'h2 && DRDOut) SS[1:0] <= 2'b11;
ARCLK <= 0; else if (LS[15:0]==16'h0FB0) SS[1:0] <= 2'b01;
ARShift <= 1; else if (LS[15:0]==16'h0FFF) SS[1:0] <= 2'b10;
DRCLK <= 0; else if (LS[15:0]==16'h1FFF) SS[1:0] <= 2'b11;
DRShift <= 0; end
end else if (LS[15:0]<=16'h0FFF) begin end
ARCLK <= ~LS[1]; always @(posedge C25M) begin
ARShift <= 1; if (SS[1:0]==2'b00 /* LS[15:0]<=16'h0FB0 */) begin
DRCLK <= 0; ARCLK <= 0;
DRShift <= 0; ARShift <= 1;
SetFW <= 1'b1; DRCLK <= 0;
SetLim8M <= 1'b1; DRShift <= 0;
end else if (LS[15:0]<=16'h1FFF) begin end else if (SS[1:0]==2'b01 /* LS[15:0]<=16'h0FFF */) begin
case (LS[3:1]) ARCLK <= ~LS[1];
3'h0: begin ARShift <= 1;
ARCLK <= 0; DRCLK <= 0;
ARShift <= 0; DRShift <= 0;
DRCLK <= 1; SetFW <= 1'b1;
DRShift <= 0; SetLim8M <= 1'b1;
end 3'h1: begin end else if (SS[1:0]==2'b10 /* LS[15:0]<=16'h1FFF */) begin
ARCLK <= 0; case (LS[3:1])
ARShift <= 0; 3'h0: begin
DRCLK <= 0; ARCLK <= 0;
DRShift <= 1; ARShift <= 0;
end 3'h2: begin DRCLK <= 1;
ARCLK <= 0; DRShift <= 0;
ARShift <= 0; end 3'h1: begin
DRCLK <= 1; ARCLK <= 0;
DRShift <= 1; ARShift <= 0;
if (LS[3:0]==4'h2 && DRDOut) SetLoaded <= 1; DRCLK <= 0;
end 3'h3: begin DRShift <= 1;
ARCLK <= 0; end 3'h2: begin
ARShift <= 0; ARCLK <= 0;
DRCLK <= 0; ARShift <= 0;
DRShift <= 1; DRCLK <= 1;
end 3'h4: begin DRShift <= 1;
ARCLK <= 0; end 3'h3: begin
ARShift <= 0; ARCLK <= 0;
DRCLK <= 1; ARShift <= 0;
DRShift <= 1; DRCLK <= 0;
if (LS[3:0]==4'h4) SetFW <= DRDOut; DRShift <= 1;
end 3'h5: begin end 3'h4: begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRCLK <= 0; DRCLK <= 1;
DRShift <= 1; DRShift <= 1;
end 3'h6: begin if (LS[3:0]==4'h4) SetFW <= DRDOut;
ARCLK <= 1; end 3'h5: begin
ARShift <= 0; ARCLK <= 0;
DRCLK <= 0; ARShift <= 0;
DRShift <= 1; DRCLK <= 0;
if (LS[3:0]==4'h6) SetLim8M <= DRDOut; DRShift <= 1;
end 3'h7: begin end 3'h6: begin
ARCLK <= 0; ARCLK <= 1;
ARShift <= 0; ARShift <= 0;
DRCLK <= 0; DRCLK <= 0;
DRShift <= 0; DRShift <= 1;
end if (LS[3:0]==4'h6) SetLim8M <= DRDOut;
endcase end 3'h7: begin
end else SetLoaded <= 1; ARCLK <= 0;
ARShift <= 0;
DRCLK <= 0;
DRShift <= 0;
end
endcase
DRDIn <= 0; DRDIn <= 0;
end else if (PS==7 /* && ... FIXME */) begin end else begin
ARCLK <= 0; ARCLK <= 0;
ARShift <= 0; ARShift <= 0;
DRShift <= 1; DRShift <= 1;
DRCLK <= 0; DRCLK <= 0;
DRDIn <= 0; DRDIn <= 0;
end end
@ -337,22 +340,25 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
/* SDRAM address/command */ /* SDRAM address/command */
output [1:0] SBA; assign SBA[1:0] = output [1:0] SBA; assign SBA[1:0] =
Amux[2:0]==2'h0 ? 2'b00 : // mode register / "all" Amux[2:1]==2'h0 ? 2'b00 : // mode register / "all"
Amux[2:0]==2'h1 ? 2'b00 : // FIXME: init row / col Amux[2:1]==2'h1 ? 2'b00 : // FIXME: init row / col
Amux[2:0]==2'h2 ? 2'b10 : // ROM row / col Amux[2:1]==2'h2 ? 2'b10 : // ROM row / col
/* 2'h3 */ { 1'b0, Addr[23] & SetFW & ~SetLim8M }; // RAM col /* 2'h3 */ { 1'b0, Addr[23] & SetFW & ~SetLim8M }; // RAM row/col
output [12:0] SA; assign SA[12:0] = output [12:0] SA;
Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register assign SA[12] = Amux[2:0]==3'h6 && Addr[22] && SetFW;
Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all" /*assign SA[12:0] =
Amux[2:0]==3'h2 ? 13'b0011000100000 : // FIXME: init row Amux[2:0]==3'h0 ? 13'b0001000100000 : // mode register
Amux[2:0]==3'h3 ? 13'b0011000100000 : // FIXME: init col Amux[2:0]==3'h1 ? 13'b0011000100000 : // "all"
Amux[2:0]==3'h2 ? { 9'b001100010, LS[16:13] } : // init row
Amux[2:0]==3'h3 ? { 4'b0011, LS[12:4] } : // init col
Amux[2:0]==3'h4 ? { 9'b000000000, Bank[1:0], RAcur[11:10] } : // ROM row Amux[2:0]==3'h4 ? { 9'b000000000, Bank[1:0], RAcur[11:10] } : // ROM row
Amux[2:0]==3'h5 ? { 4'b0000, RAcur[9:1]} : // ROM col Amux[2:0]==3'h5 ? { 4'b0000, RAcur[9:1]} : // ROM col
Amux[2:0]==3'h6 ? { Addr[22] & SetFW, Amux[2:0]==3'h6 ? { Addr[22] & SetFW,
Addr[21] & SetFW, Addr[21] & SetFW,
Addr[20] & SetFW, Addr[20] & SetFW,
Addr[19:10] } : // RAM row Addr[19:10] } : // RAM row
/* 3'h7 */ { 4'b0000, Addr[9:1] }; // RAM col { 4'b0000, Addr[9:1] }; // RAM col
*/
output DQML; assign DQML = output DQML; assign DQML =
Amux[2:0]==3'h0 ? 1'b1 : // mode register Amux[2:0]==3'h0 ? 1'b1 : // mode register
Amux[2:0]==3'h1 ? 1'b1 : // "all" Amux[2:0]==3'h1 ? 1'b1 : // "all"
@ -362,7 +368,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout,
Amux[2:0]==3'h5 ? RAcur[0]: // ROM col Amux[2:0]==3'h5 ? RAcur[0]: // ROM col
Amux[2:0]==3'h6 ? 1'b1 : // RAM row Amux[2:0]==3'h6 ? 1'b1 : // RAM row
/* 3'h7 */ Addr[0]; // RAM col /* 3'h7 */ Addr[0]; // RAM col
output DQMH; assign DQMH = output DQMH; assign DQMH =
Amux[2:0]==3'h0 ? 1'b1 : // mode register Amux[2:0]==3'h0 ? 1'b1 : // mode register
Amux[2:0]==3'h1 ? 1'b1 : // "all" Amux[2:0]==3'h1 ? 1'b1 : // "all"
Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row Amux[2:0]==3'h2 ? 1'b1 : // FIXME: init row

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cpld/db/GR8RAM.asm.qmsg
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@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153593678 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186128983 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153593694 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:33:13 2021 " "Processing started: Fri Mar 19 07:33:13 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153593694 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616153593694 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186128983 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:28 2021 " "Processing started: Fri Mar 19 16:35:28 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186128983 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1616186128983 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616153593694 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1616186128983 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616153594788 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1616186130343 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616153594819 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1616186130390 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:33:15 2021 " "Processing ended: Fri Mar 19 07:33:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153595398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616153595398 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:31 2021 " "Processing ended: Fri Mar 19 16:35:31 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186131124 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1616186131124 ""}

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cpld/db/GR8RAM.hier_info
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@ -15,20 +15,19 @@ C25M => SDOE.CLK
C25M => WRD[6].CLK C25M => WRD[6].CLK
C25M => WRD[7].CLK C25M => WRD[7].CLK
C25M => DRDIn.CLK C25M => DRDIn.CLK
C25M => SetLoaded.CLK
C25M => SetLim8M.CLK C25M => SetLim8M.CLK
C25M => SetFW.CLK C25M => SetFW.CLK
C25M => DRShift.CLK C25M => DRShift.CLK
C25M => DRCLK.CLK C25M => DRCLK.CLK
C25M => ARShift.CLK C25M => ARShift.CLK
C25M => ARCLK.CLK C25M => ARCLK.CLK
C25M => SS[0].CLK
C25M => SS[1].CLK
C25M => MOSIOE.CLK C25M => MOSIOE.CLK
C25M => MOSIout.CLK C25M => MOSIout.CLK
C25M => FCKEN.CLK C25M => FCKEN.CLK
C25M => FCS.CLK C25M => FCS.CLK
C25M => FCK~reg0.CLK C25M => FCK~reg0.CLK
C25M => Bank[0].CLK
C25M => Bank[1].CLK
C25M => Addr[0].CLK C25M => Addr[0].CLK
C25M => Addr[1].CLK C25M => Addr[1].CLK
C25M => Addr[2].CLK C25M => Addr[2].CLK
@ -139,18 +138,18 @@ RD[7] <> RD[7]
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
SBA[0] <= SBA.DB_MAX_OUTPUT_PORT_TYPE SBA[0] <= SBA.DB_MAX_OUTPUT_PORT_TYPE
SBA[1] <= SBA.DB_MAX_OUTPUT_PORT_TYPE SBA[1] <= SBA.DB_MAX_OUTPUT_PORT_TYPE
SA[0] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[0] <= <GND>
SA[1] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[1] <= <GND>
SA[2] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[2] <= <GND>
SA[3] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[3] <= <GND>
SA[4] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[4] <= <GND>
SA[5] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[5] <= <GND>
SA[6] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[6] <= <GND>
SA[7] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[7] <= <GND>
SA[8] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[8] <= <GND>
SA[9] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[9] <= <GND>
SA[10] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[10] <= <GND>
SA[11] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[11] <= <GND>
SA[12] <= SA.DB_MAX_OUTPUT_PORT_TYPE SA[12] <= SA.DB_MAX_OUTPUT_PORT_TYPE
nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE

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cpld/db/GR8RAM.map.qmsg
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@ -1,31 +1,34 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153574982 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186109748 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:32:54 2021 " "Processing started: Fri Mar 19 07:32:54 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:09 2021 " "Processing started: Fri Mar 19 16:35:09 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153574998 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616186109764 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153576561 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616186111186 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153576764 ""} { "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616186111498 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616153576764 ""} { "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1616186111498 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616153576780 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_0ep " "Found entity 1: UFM_altufm_none_0ep" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1616186111498 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153577046 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(85) " "Verilog HDL warning at gr8ram.v(85): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616186111717 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(311) " "Verilog HDL warning at gr8ram.v(311): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 311 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616153577046 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "gr8ram.v(314) " "Verilog HDL warning at gr8ram.v(314): extended using \"x\" or \"z\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 314 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1616186111733 ""}
{ "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616153577061 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616153577061 ""} { "Warning" "WSGN_SEARCH_FILE" "gr8ram.v 1 1 " "Using design file gr8ram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1616186111733 ""} } { } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Quartus II" 0 -1 1616186111733 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153577061 ""} { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "UFMB gr8ram.v(223) " "Verilog HDL Implicit Net warning at gr8ram.v(223): created implicit net for \"UFMB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 223 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616186111733 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616153577061 ""} { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "RTPB gr8ram.v(226) " "Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for \"RTPB\"" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1616186111733 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616153577093 ""} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1616186111764 ""}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(86) " "Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} { "Warning" "WVRFX_VERI_2106_UNCONVERTED" "RDout gr8ram.v(86) " "Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(228) " "Verilog HDL or VHDL warning at gr8ram.v(228): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 228 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "Bank gr8ram.v(118) " "Verilog HDL or VHDL warning at gr8ram.v(118): object \"Bank\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 118 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(230) " "Verilog HDL or VHDL warning at gr8ram.v(230): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "UFMBr gr8ram.v(228) " "Verilog HDL or VHDL warning at gr8ram.v(228): object \"UFMBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 228 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(332) " "Verilog HDL or VHDL warning at gr8ram.v(332): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 332 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RTPBr gr8ram.v(230) " "Verilog HDL or VHDL warning at gr8ram.v(230): object \"RTPBr\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 230 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(24) " "Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "RefReady gr8ram.v(335) " "Verilog HDL or VHDL warning at gr8ram.v(335): object \"RefReady\" assigned a value but never read" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 335 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(100) " "Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 gr8ram.v(24) " "Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 24 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(104) " "Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 gr8ram.v(100) " "Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(109) " "Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577093 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 gr8ram.v(104) " "Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(327) " "Verilog HDL assignment warning at gr8ram.v(327): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 327 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616153577108 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 gr8ram.v(109) " "Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111764 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(86) " "Net \"RDout\" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153577124 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 gr8ram.v(330) " "Verilog HDL assignment warning at gr8ram.v(330): truncated value with size 32 to match size of target (3)" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 330 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(312) " "Net \"WRD\[5..0\]\" at gr8ram.v(312) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 312 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616153577124 "|GR8RAM"} { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "RDout 0 gr8ram.v(86) " "Net \"RDout\" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 86 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153577249 ""} { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "WRD\[5..0\] 0 gr8ram.v(315) " "Net \"WRD\[5..0\]\" at gr8ram.v(315) has no driver or initial value, using a default initial value '0'" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 315 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1616186111780 "|GR8RAM"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616153577280 ""} { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "SA\[11..0\] gr8ram.v(347) " "Output port \"SA\[11..0\]\" at gr8ram.v(347) has no driver" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1616186111795 "|GR8RAM"}
{ "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616153578484 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616153578484 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "gr8ram.v" "UFM_inst" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 226 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616186111967 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153578734 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 339 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616153578734 "|GR8RAM|SBA[0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616153578734 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_0ep UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component " "Elaborating entity \"UFM_altufm_none_0ep\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component\"" { } { { "UFM.v" "UFM_altufm_none_0ep_component" { Text "Z:/Repos/GR8RAM/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1616186112030 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "329 " "Implemented 329 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Implemented 24 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_LCELLS" "260 " "Implemented 260 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616153579297 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616153579297 ""} { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1616186113280 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616153579562 ""} { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR_HDR" "" "Tri-state node(s) do not directly drive top-level pin(s)" { { "Warning" "WMLS_MLS_CONVERT_TRI_TO_OR" "MOSI WRD\[6\] " "Converted the fan-out from the tri-state buffer \"MOSI\" to the node \"WRD\[6\]\" into an OR gate" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 132 -1 0 } } } 0 13047 "Converted the fan-out from the tri-state buffer \"%1!s!\" to the node \"%2!s!\" into an OR gate" 0 0 "Quartus II" 0 -1 1616186113327 ""} } { } 0 13046 "Tri-state node(s) do not directly drive top-level pin(s)" 0 0 "Quartus II" 0 -1 1616186113327 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:32:59 2021 " "Processing ended: Fri Mar 19 07:32:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153579797 ""} { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 53 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SBA\[0\] GND " "Pin \"SBA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 342 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SBA[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[0\] GND " "Pin \"SA\[0\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[1\] GND " "Pin \"SA\[1\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[2\] GND " "Pin \"SA\[2\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[3\] GND " "Pin \"SA\[3\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[4\] GND " "Pin \"SA\[4\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[5\] GND " "Pin \"SA\[5\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[6\] GND " "Pin \"SA\[6\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[7\] GND " "Pin \"SA\[7\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[8\] GND " "Pin \"SA\[8\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[9\] GND " "Pin \"SA\[9\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[10\] GND " "Pin \"SA\[10\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[10]"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[11\] GND " "Pin \"SA\[11\]\" is stuck at GND" { } { { "gr8ram.v" "" { Text "Z:/Repos/GR8RAM/cpld/gr8ram.v" 347 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1616186113608 "|GR8RAM|SA[11]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1616186113608 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "306 " "Implemented 306 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "24 " "Implemented 24 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_OPINS" "28 " "Implemented 28 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_LCELLS" "237 " "Implemented 237 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1616186113983 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1616186113983 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1616186113983 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1616186114420 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 33 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 33 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:14 2021 " "Processing ended: Fri Mar 19 16:35:14 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616186114655 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616153598352 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1616186134749 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 07:33:17 2021 " "Processing started: Fri Mar 19 07:33:17 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616153598368 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 19 16:35:33 2021 " "Processing started: Fri Mar 19 16:35:33 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616153598383 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1616186134780 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616153598555 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1616186134968 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616153599509 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1616186135733 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153599790 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616186135937 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616153599790 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1616186135937 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616153600103 ""} { "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1616186136155 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616153600759 ""} { "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1616186136718 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616153601103 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1616186136905 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616153601119 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1616186136905 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601135 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601135 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1616186136921 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616153601197 ""} { "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1616186136952 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616153601432 ""} { "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1616186137124 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.506 " "Worst-case setup slack is -9.506" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.506 -540.769 C25M " " -9.506 -540.769 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601447 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.555 -547.115 C25M " " -9.555 -547.115 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137187 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.639 " "Worst-case hold slack is 1.639" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.639 0.000 C25M " " 1.639 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601463 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold -16.276 " "Worst-case hold slack is -16.276" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.256 -16.256 DRCLK " " -16.256 -16.256 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.377 0.000 C25M " " 1.377 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137218 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153601478 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616186137312 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616153601494 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1616186137343 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616153601510 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1616186137358 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616153601635 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1616186137671 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153601901 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616186137827 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616153601901 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1616186137843 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 07:33:22 2021 " "Processing ended: Fri Mar 19 07:33:22 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616153602213 ""} { "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 19 16:35:38 2021 " "Processing ended: Fri Mar 19 16:35:38 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1616186138155 ""}

BIN
cpld/db/GR8RAM.sta.rdb
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cpld/db/GR8RAM.sta_cmp.5_slow.tdb
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cpld/db/GR8RAM.tmw_info Executable file
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@ -0,0 +1,6 @@
start_full_compilation:s:00:00:32
start_analysis_synthesis:s:00:00:08-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:11-start_full_compilation
start_assembler:s:00:00:05-start_full_compilation
start_timing_analyzer:s:00:00:08-start_full_compilation

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cpld/db/GR8RAM.vpr.ammdb
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cpld/db/logic_util_heursitic.dat
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cpld/db/prev_cmp_GR8RAM.qmsg
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cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
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14
cpld/output_files/GR8RAM.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for GR8RAM Assembler report for GR8RAM
Fri Mar 19 07:33:15 2021 Fri Mar 19 16:35:30 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Mar 19 07:33:15 2021 ; ; Assembler Status ; Successful - Fri Mar 19 16:35:30 2021 ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
@ -90,8 +90,8 @@ applicable agreement for further details.
; Option ; Setting ; ; Option ; Setting ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; JTAG usercode ; 0x00164F11 ; ; JTAG usercode ; 0x0016B2B7 ;
; Checksum ; 0x00165309 ; ; Checksum ; 0x0016B52F ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
@ -101,14 +101,14 @@ applicable agreement for further details.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Mar 19 07:33:13 2021 Info: Processing started: Fri Mar 19 16:35:28 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 293 megabytes Info: Peak virtual memory: 293 megabytes
Info: Processing ended: Fri Mar 19 07:33:15 2021 Info: Processing ended: Fri Mar 19 16:35:31 2021
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02 Info: Total CPU time (on all processors): 00:00:02

2
cpld/output_files/GR8RAM.done
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@ -1 +1 @@
Fri Mar 19 07:33:23 2021 Fri Mar 19 16:35:39 2021

1304
cpld/output_files/GR8RAM.fit.rpt
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4
cpld/output_files/GR8RAM.fit.summary
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@ -1,11 +1,11 @@
Fitter Status : Successful - Fri Mar 19 07:33:10 2021 Fitter Status : Successful - Fri Mar 19 16:35:25 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Device : EPM240T100C5 Device : EPM240T100C5
Timing Models : Final Timing Models : Final
Total logic elements : 235 / 240 ( 98 % ) Total logic elements : 217 / 240 ( 90 % )
Total pins : 68 / 80 ( 85 % ) Total pins : 68 / 80 ( 85 % )
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % ) UFM blocks : 1 / 1 ( 100 % )

57
cpld/output_files/GR8RAM.flow.rpt
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@ -1,5 +1,5 @@
Flow report for GR8RAM Flow report for GR8RAM
Fri Mar 19 07:33:22 2021 Fri Mar 19 16:35:37 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,14 +40,14 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+---------------------------+-------------------------------------------------+ +---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Fri Mar 19 07:33:15 2021 ; ; Flow Status ; Successful - Fri Mar 19 16:35:30 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 235 / 240 ( 98 % ) ; ; Total logic elements ; 217 / 240 ( 90 % ) ;
; Total pins ; 68 / 80 ( 85 % ) ; ; Total pins ; 68 / 80 ( 85 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ; ; UFM blocks ; 1 / 1 ( 100 % ) ;
@ -59,28 +59,37 @@ applicable agreement for further details.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/19/2021 07:32:56 ; ; Start date & time ; 03/19/2021 16:35:10 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
+-------------------+---------------------+ +-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ; ; Flow Non-Default Global Settings ;
+---------------------------------------+--------------------------------+---------------+-------------+------------+ +-------------------------------------------------+--------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+--------------------------------+---------------+-------------+------------+ +-------------------------------------------------+--------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 44085571633675.161615357603936 ; -- ; -- ; -- ; ; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Always ; Auto ; -- ; -- ;
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 44085571633675.161618611002356 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; ; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ; MAXII_OPTIMIZATION_TECHNIQUE ; Area ; Balanced ; -- ; -- ;
+---------------------------------------+--------------------------------+---------------+-------------+------------+ ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PLACEMENT_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; On ; Off ; -- ; -- ;
; ROUTER_EFFORT_MULTIPLIER ; 2.0 ; 1.0 ; -- ; -- ;
; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
+-------------------------------------------------+--------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------+
@ -88,11 +97,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:05 ; ; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:04 ;
; Fitter ; 00:00:09 ; 1.3 ; 373 MB ; 00:00:08 ; ; Fitter ; 00:00:09 ; 1.5 ; 376 MB ; 00:00:08 ;
; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ; ; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 275 MB ; 00:00:05 ; ; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 275 MB ; 00:00:04 ;
; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ; ; Total ; 00:00:20 ; -- ; -- ; 00:00:18 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +---------------------------+--------------+-------------------------+---------------------+------------------------------------+

2
cpld/output_files/GR8RAM.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info> <sld_project_info>
<project> <project>
<hash md5_digest_80b="ebf91a8d56f02dc1205e"/> <hash md5_digest_80b="4e85f6d7379987575f53"/>
</project> </project>
<file_info> <file_info>
<file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/> <file device="EPM240T100C5" path="GR8RAM.sof" usercode="0xFFFFFFFF"/>

89
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM Analysis & Synthesis report for GR8RAM
Fri Mar 19 07:32:59 2021 Fri Mar 19 16:35:14 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -47,12 +47,12 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+ +-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Mar 19 07:32:59 2021 ; ; Analysis & Synthesis Status ; Successful - Fri Mar 19 16:35:14 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Total logic elements ; 260 ; ; Total logic elements ; 237 ;
; Total pins ; 68 ; ; Total pins ; 68 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ; ; UFM blocks ; 1 / 1 ( 100 % ) ;
@ -67,7 +67,12 @@ applicable agreement for further details.
; Device ; EPM240T100C5 ; ; ; Device ; EPM240T100C5 ; ;
; Top-level entity name ; GR8RAM ; GR8RAM ; ; Top-level entity name ; GR8RAM ; GR8RAM ;
; Family name ; MAX II ; Cyclone IV GX ; ; Family name ; MAX II ; Cyclone IV GX ;
; Safe State Machine ; On ; Off ;
; Remove Redundant Logic Cells ; On ; Off ;
; Optimization Technique ; Area ; Balanced ; ; Optimization Technique ; Area ; Balanced ;
; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
; Allow Shift Register Merging across Hierarchies ; Always ; Auto ;
; Auto Resource Sharing ; On ; Off ;
; Use smart compilation ; Off ; Off ; ; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ; ; Enable compact report table ; Off ; Off ;
@ -78,7 +83,6 @@ applicable agreement for further details.
; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ; ; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ; ; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ; ; Ignore Verilog initial constructs ; Off ; Off ;
@ -89,7 +93,6 @@ applicable agreement for further details.
; Parallel Synthesis ; On ; On ; ; Parallel Synthesis ; On ; On ;
; NOT Gate Push-Back ; On ; On ; ; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ; ; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ; ; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ;
@ -101,13 +104,10 @@ applicable agreement for further details.
; Carry Chain Length ; 70 ; 70 ; ; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ; ; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ; ; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto Shift Register Replacement ; Auto ; Auto ; ; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ; ; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ; ; Report Parameter Settings ; On ; On ;
@ -164,34 +164,34 @@ applicable agreement for further details.
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Total logic elements ; 260 ; ; Total logic elements ; 237 ;
; -- Combinational with no register ; 164 ; ; -- Combinational with no register ; 142 ;
; -- Register only ; 29 ; ; -- Register only ; 29 ;
; -- Combinational with a register ; 67 ; ; -- Combinational with a register ; 66 ;
; ; ; ; ; ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 96 ; ; -- 4 input functions ; 80 ;
; -- 3 input functions ; 45 ; ; -- 3 input functions ; 45 ;
; -- 2 input functions ; 80 ; ; -- 2 input functions ; 71 ;
; -- 1 input functions ; 9 ; ; -- 1 input functions ; 11 ;
; -- 0 input functions ; 1 ; ; -- 0 input functions ; 1 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 202 ; ; -- normal mode ; 179 ;
; -- arithmetic mode ; 58 ; ; -- arithmetic mode ; 58 ;
; -- qfbk mode ; 0 ; ; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ; ; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 25 ; ; -- synchronous clear/load mode ; 25 ;
; -- asynchronous clear/load mode ; 0 ; ; -- asynchronous clear/load mode ; 0 ;
; ; ; ; ; ;
; Total registers ; 96 ; ; Total registers ; 95 ;
; Total logic cells in carry chains ; 62 ; ; Total logic cells in carry chains ; 62 ;
; I/O pins ; 68 ; ; I/O pins ; 68 ;
; UFM blocks ; 1 ; ; UFM blocks ; 1 ;
; Maximum fan-out node ; C25M ; ; Maximum fan-out node ; C25M ;
; Maximum fan-out ; 96 ; ; Maximum fan-out ; 95 ;
; Total fan-out ; 933 ; ; Total fan-out ; 836 ;
; Average fan-out ; 2.84 ; ; Average fan-out ; 2.73 ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
@ -200,7 +200,7 @@ applicable agreement for further details.
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
; |GR8RAM ; 260 (260) ; 96 ; 1 ; 68 ; 0 ; 164 (164) ; 29 (29) ; 67 (67) ; 62 (62) ; 0 (0) ; |GR8RAM ; work ; ; |GR8RAM ; 237 (237) ; 95 ; 1 ; 68 ; 0 ; 142 (142) ; 29 (29) ; 66 (66) ; 62 (62) ; 0 (0) ; |GR8RAM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst ; work ;
; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ; ; |UFM_altufm_none_0ep:UFM_altufm_none_0ep_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |GR8RAM|UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+ +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+--------------+
@ -243,12 +243,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Statistic ; Value ; ; Statistic ; Value ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
; Total registers ; 96 ; ; Total registers ; 95 ;
; Number of registers using Synchronous Clear ; 25 ; ; Number of registers using Synchronous Clear ; 25 ;
; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 45 ; ; Number of registers using Clock Enable ; 41 ;
; Number of registers using Preset ; 0 ; ; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+ +----------------------------------------------+-------+
@ -273,15 +273,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ; ; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[0] ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |GR8RAM|Bank[1] ; ; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[0] ;
; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |GR8RAM|Addr[4] ; ; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |GR8RAM|SS[0] ;
; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[8] ; ; 7:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |GR8RAM|Addr[13] ;
; 13:1 ; 2 bits ; 16 LEs ; 12 LEs ; 4 LEs ; Yes ; |GR8RAM|DRCLK ; ; 9:1 ; 8 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |GR8RAM|Addr[17] ;
; 9:1 ; 8 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |GR8RAM|Addr[19] ; ; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|DQML ;
; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|SA ;
; 8:1 ; 5 bits ; 25 LEs ; 15 LEs ; 10 LEs ; No ; |GR8RAM|SA ;
; 8:1 ; 4 bits ; 20 LEs ; 12 LEs ; 8 LEs ; No ; |GR8RAM|SA ;
; 8:1 ; 2 bits ; 10 LEs ; 6 LEs ; 4 LEs ; No ; |GR8RAM|DQMH ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
@ -304,7 +300,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Mar 19 07:32:54 2021 Info: Processing started: Fri Mar 19 16:35:09 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
@ -316,33 +312,48 @@ Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(223): created impl
Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for "RTPB" Warning (10236): Verilog HDL Implicit Net warning at gr8ram.v(226): created implicit net for "RTPB"
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10858): Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned Warning (10858): Verilog HDL warning at gr8ram.v(86): object RDout used but never assigned
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(118): object "Bank" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(228): object "UFMBr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(228): object "UFMBr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(230): object "RTPBr" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(230): object "RTPBr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(332): object "RefReady" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at gr8ram.v(335): object "RefReady" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18) Warning (10230): Verilog HDL assignment warning at gr8ram.v(24): truncated value with size 32 to match size of target (18)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24) Warning (10230): Verilog HDL assignment warning at gr8ram.v(100): truncated value with size 32 to match size of target (24)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at gr8ram.v(104): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8) Warning (10230): Verilog HDL assignment warning at gr8ram.v(109): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at gr8ram.v(327): truncated value with size 32 to match size of target (3) Warning (10230): Verilog HDL assignment warning at gr8ram.v(330): truncated value with size 32 to match size of target (3)
Warning (10030): Net "RDout" at gr8ram.v(86) has no driver or initial value, using a default initial value '0' Warning (10030): Net "RDout" at gr8ram.v(86) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "WRD[5..0]" at gr8ram.v(312) has no driver or initial value, using a default initial value '0' Warning (10030): Net "WRD[5..0]" at gr8ram.v(315) has no driver or initial value, using a default initial value '0'
Warning (10034): Output port "SA[11..0]" at gr8ram.v(347) has no driver
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component" Info (12128): Elaborating entity "UFM_altufm_none_0ep" for hierarchy "UFM:UFM_inst|UFM_altufm_none_0ep:UFM_altufm_none_0ep_component"
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD[6]" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "MOSI" to the node "WRD[6]" into an OR gate
Warning (13024): Output pins are stuck at VCC or GND Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "RAdir" is stuck at VCC Warning (13410): Pin "RAdir" is stuck at VCC
Warning (13410): Pin "SBA[0]" is stuck at GND Warning (13410): Pin "SBA[0]" is stuck at GND
Info (21057): Implemented 329 device resources after synthesis - the final resource count might be different Warning (13410): Pin "SA[0]" is stuck at GND
Warning (13410): Pin "SA[1]" is stuck at GND
Warning (13410): Pin "SA[2]" is stuck at GND
Warning (13410): Pin "SA[3]" is stuck at GND
Warning (13410): Pin "SA[4]" is stuck at GND
Warning (13410): Pin "SA[5]" is stuck at GND
Warning (13410): Pin "SA[6]" is stuck at GND
Warning (13410): Pin "SA[7]" is stuck at GND
Warning (13410): Pin "SA[8]" is stuck at GND
Warning (13410): Pin "SA[9]" is stuck at GND
Warning (13410): Pin "SA[10]" is stuck at GND
Warning (13410): Pin "SA[11]" is stuck at GND
Info (21057): Implemented 306 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 24 input pins Info (21058): Implemented 24 input pins
Info (21059): Implemented 28 output pins Info (21059): Implemented 28 output pins
Info (21060): Implemented 16 bidirectional pins Info (21060): Implemented 16 bidirectional pins
Info (21061): Implemented 260 logic cells Info (21061): Implemented 237 logic cells
Info (21070): Implemented 1 User Flash Memory blocks Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 19 warnings Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 33 warnings
Info: Peak virtual memory: 301 megabytes Info: Peak virtual memory: 301 megabytes
Info: Processing ended: Fri Mar 19 07:32:59 2021 Info: Processing ended: Fri Mar 19 16:35:14 2021
Info: Elapsed time: 00:00:05 Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:05 Info: Total CPU time (on all processors): 00:00:05

2
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,4 +1,4 @@
Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword
Warning (10273): Verilog HDL warning at gr8ram.v(85): extended using "x" or "z" Warning (10273): Verilog HDL warning at gr8ram.v(85): extended using "x" or "z"
Warning (10273): Verilog HDL warning at gr8ram.v(311): extended using "x" or "z" Warning (10273): Verilog HDL warning at gr8ram.v(314): extended using "x" or "z"

4
cpld/output_files/GR8RAM.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Fri Mar 19 07:32:59 2021 Analysis & Synthesis Status : Successful - Fri Mar 19 16:35:14 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Total logic elements : 260 Total logic elements : 237
Total pins : 68 Total pins : 68
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % ) UFM blocks : 1 / 1 ( 100 % )

148
cpld/output_files/GR8RAM.pin
View File

@ -62,103 +62,103 @@ CHIP "GR8RAM" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------
RA[12] : 1 : input : 3.3-V LVTTL : : 2 : N SA[0] : 1 : output : 3.3-V LVTTL : : 2 : N
RD[0] : 2 : bidir : 3.3-V LVTTL : : 1 : N GND* : 2 : : : : 1 :
RD[3] : 3 : bidir : 3.3-V LVTTL : : 1 : N SA[8] : 3 : output : 3.3-V LVTTL : : 1 : N
RD[6] : 4 : bidir : 3.3-V LVTTL : : 1 : N SA[2] : 4 : output : 3.3-V LVTTL : : 1 : N
RD[4] : 5 : bidir : 3.3-V LVTTL : : 1 : N RAdir : 5 : output : 3.3-V LVTTL : : 1 : N
RD[7] : 6 : bidir : 3.3-V LVTTL : : 1 : N SD[5] : 6 : bidir : 3.3-V LVTTL : : 1 : N
RD[1] : 7 : bidir : 3.3-V LVTTL : : 1 : N SD[4] : 7 : bidir : 3.3-V LVTTL : : 1 : N
nWE : 8 : input : 3.3-V LVTTL : : 1 : N SD[1] : 8 : bidir : 3.3-V LVTTL : : 1 : N
VCCIO1 : 9 : power : : 3.3V : 1 : VCCIO1 : 9 : power : : 3.3V : 1 :
GNDIO : 10 : gnd : : : : GNDIO : 10 : gnd : : : :
GNDINT : 11 : gnd : : : : GNDINT : 11 : gnd : : : :
PHI0 : 12 : input : 3.3-V LVTTL : : 1 : N RA[3] : 12 : input : 3.3-V LVTTL : : 1 : N
VCCINT : 13 : power : : 2.5V/3.3V : : VCCINT : 13 : power : : 2.5V/3.3V : :
C25M : 14 : input : 3.3-V LVTTL : : 1 : N C25M : 14 : input : 3.3-V LVTTL : : 1 : N
RA[8] : 15 : input : 3.3-V LVTTL : : 1 : N RA[5] : 15 : input : 3.3-V LVTTL : : 1 : N
RA[10] : 16 : input : 3.3-V LVTTL : : 1 : N RA[2] : 16 : input : 3.3-V LVTTL : : 1 : N
RA[9] : 17 : input : 3.3-V LVTTL : : 1 : N RA[0] : 17 : input : 3.3-V LVTTL : : 1 : N
SA[8] : 18 : output : 3.3-V LVTTL : : 1 : N SD[6] : 18 : bidir : 3.3-V LVTTL : : 1 : N
SA[7] : 19 : output : 3.3-V LVTTL : : 1 : N nRESout : 19 : output : 3.3-V LVTTL : : 1 : N
RA[11] : 20 : input : 3.3-V LVTTL : : 1 : N SD[7] : 20 : bidir : 3.3-V LVTTL : : 1 : N
SA[1] : 21 : output : 3.3-V LVTTL : : 1 : N MOSI : 21 : output : 3.3-V LVTTL : : 1 : N
TMS : 22 : input : : : 1 : TMS : 22 : input : : : 1 :
TDI : 23 : input : : : 1 : TDI : 23 : input : : : 1 :
TCK : 24 : input : : : 1 : TCK : 24 : input : : : 1 :
TDO : 25 : output : : : 1 : TDO : 25 : output : : : 1 :
SD[7] : 26 : bidir : 3.3-V LVTTL : : 1 : N SD[3] : 26 : bidir : 3.3-V LVTTL : : 1 : N
SD[6] : 27 : bidir : 3.3-V LVTTL : : 1 : N SD[2] : 27 : bidir : 3.3-V LVTTL : : 1 : N
MOSI : 28 : output : 3.3-V LVTTL : : 1 : N MISO : 28 : input : 3.3-V LVTTL : : 1 : N
FCK : 29 : output : 3.3-V LVTTL : : 1 : N SD[0] : 29 : bidir : 3.3-V LVTTL : : 1 : N
RA[0] : 30 : input : 3.3-V LVTTL : : 1 : N FCK : 30 : output : 3.3-V LVTTL : : 1 : N
VCCIO1 : 31 : power : : 3.3V : 1 : VCCIO1 : 31 : power : : 3.3V : 1 :
GNDIO : 32 : gnd : : : : GNDIO : 32 : gnd : : : :
MISO : 33 : input : 3.3-V LVTTL : : 1 : N RA[8] : 33 : input : 3.3-V LVTTL : : 1 : N
RA[7] : 34 : input : 3.3-V LVTTL : : 1 : N RA[10] : 34 : input : 3.3-V LVTTL : : 1 : N
RA[2] : 35 : input : 3.3-V LVTTL : : 1 : N RA[7] : 35 : input : 3.3-V LVTTL : : 1 : N
RA[14] : 36 : input : 3.3-V LVTTL : : 1 : N RA[4] : 36 : input : 3.3-V LVTTL : : 1 : N
nRESout : 37 : output : 3.3-V LVTTL : : 1 : N RA[9] : 37 : input : 3.3-V LVTTL : : 1 : N
nFCS : 38 : output : 3.3-V LVTTL : : 1 : N RA[1] : 38 : input : 3.3-V LVTTL : : 1 : N
SA[3] : 39 : output : 3.3-V LVTTL : : 1 : N RA[11] : 39 : input : 3.3-V LVTTL : : 1 : N
SD[1] : 40 : bidir : 3.3-V LVTTL : : 1 : N GND* : 40 : : : : 1 :
SD[4] : 41 : bidir : 3.3-V LVTTL : : 1 : N GND* : 41 : : : : 1 :
SD[0] : 42 : bidir : 3.3-V LVTTL : : 1 : N SA[11] : 42 : output : 3.3-V LVTTL : : 1 : N
SBA[0] : 43 : output : 3.3-V LVTTL : : 1 : N nFCS : 43 : output : 3.3-V LVTTL : : 1 : N
GND* : 44 : : : : 1 : SA[12] : 44 : output : 3.3-V LVTTL : : 1 : N
VCCIO1 : 45 : power : : 3.3V : 1 : VCCIO1 : 45 : power : : 3.3V : 1 :
GNDIO : 46 : gnd : : : : GNDIO : 46 : gnd : : : :
GND* : 47 : : : : 1 : GND* : 47 : : : : 1 :
GND* : 48 : : : : 1 : DQMH : 48 : output : 3.3-V LVTTL : : 1 : N
GND* : 49 : : : : 1 : GND* : 49 : : : : 1 :
GND* : 50 : : : : 1 : GND* : 50 : : : : 1 :
SD[3] : 51 : bidir : 3.3-V LVTTL : : 1 : N GND* : 51 : : : : 1 :
SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : N SA[9] : 52 : output : 3.3-V LVTTL : : 2 : N
SD[2] : 53 : bidir : 3.3-V LVTTL : : 2 : N GND* : 53 : : : : 2 :
GND* : 54 : : : : 2 : SA[4] : 54 : output : 3.3-V LVTTL : : 2 : N
GND* : 55 : : : : 2 : SA[10] : 55 : output : 3.3-V LVTTL : : 2 : N
GND* : 56 : : : : 2 : GND* : 56 : : : : 2 :
nRCS : 57 : output : 3.3-V LVTTL : : 2 : N RA[13] : 57 : input : 3.3-V LVTTL : : 2 : N
nCAS : 58 : output : 3.3-V LVTTL : : 2 : N RA[12] : 58 : input : 3.3-V LVTTL : : 2 : N
VCCIO2 : 59 : power : : 3.3V : 2 : VCCIO2 : 59 : power : : 3.3V : 2 :
GNDIO : 60 : gnd : : : : GNDIO : 60 : gnd : : : :
SA[2] : 61 : output : 3.3-V LVTTL : : 2 : N RA[14] : 61 : input : 3.3-V LVTTL : : 2 : N
SA[10] : 62 : output : 3.3-V LVTTL : : 2 : N RA[15] : 62 : input : 3.3-V LVTTL : : 2 : N
VCCINT : 63 : power : : 2.5V/3.3V : : VCCINT : 63 : power : : 2.5V/3.3V : :
nRES : 64 : input : 3.3-V LVTTL : : 2 : N nIOSTRB : 64 : input : 3.3-V LVTTL : : 2 : N
GNDINT : 65 : gnd : : : : GNDINT : 65 : gnd : : : :
RCKE : 66 : output : 3.3-V LVTTL : : 2 : N DQML : 66 : output : 3.3-V LVTTL : : 2 : N
SA[9] : 67 : output : 3.3-V LVTTL : : 2 : N nDEVSEL : 67 : input : 3.3-V LVTTL : : 2 : N
nRAS : 68 : output : 3.3-V LVTTL : : 2 : N SBA[1] : 68 : output : 3.3-V LVTTL : : 2 : N
nSWE : 69 : output : 3.3-V LVTTL : : 2 : N nRAS : 69 : output : 3.3-V LVTTL : : 2 : N
SA[12] : 70 : output : 3.3-V LVTTL : : 2 : N RCKE : 70 : output : 3.3-V LVTTL : : 2 : N
nIOSEL : 71 : input : 3.3-V LVTTL : : 2 : N nIOSEL : 71 : input : 3.3-V LVTTL : : 2 : N
nIOSTRB : 72 : input : 3.3-V LVTTL : : 2 : N PHI0 : 72 : input : 3.3-V LVTTL : : 2 : N
SA[0] : 73 : output : 3.3-V LVTTL : : 2 : N nRES : 73 : input : 3.3-V LVTTL : : 2 : N
SA[4] : 74 : output : 3.3-V LVTTL : : 2 : N nWE : 74 : input : 3.3-V LVTTL : : 2 : N
DQMH : 75 : output : 3.3-V LVTTL : : 2 : N RDdir : 75 : output : 3.3-V LVTTL : : 2 : N
DQML : 76 : output : 3.3-V LVTTL : : 2 : N GND* : 76 : : : : 2 :
nDEVSEL : 77 : input : 3.3-V LVTTL : : 2 : N SA[5] : 77 : output : 3.3-V LVTTL : : 2 : N
RAdir : 78 : output : 3.3-V LVTTL : : 2 : N GND* : 78 : : : : 2 :
GNDIO : 79 : gnd : : : : GNDIO : 79 : gnd : : : :
VCCIO2 : 80 : power : : 3.3V : 2 : VCCIO2 : 80 : power : : 3.3V : 2 :
RA[5] : 81 : input : 3.3-V LVTTL : : 2 : N SA[7] : 81 : output : 3.3-V LVTTL : : 2 : N
RA[6] : 82 : input : 3.3-V LVTTL : : 2 : N nSWE : 82 : output : 3.3-V LVTTL : : 2 : N
SA[6] : 83 : output : 3.3-V LVTTL : : 2 : N nCAS : 83 : output : 3.3-V LVTTL : : 2 : N
RA[4] : 84 : input : 3.3-V LVTTL : : 2 : N nRCS : 84 : output : 3.3-V LVTTL : : 2 : N
SA[5] : 85 : output : 3.3-V LVTTL : : 2 : N RD[2] : 85 : bidir : 3.3-V LVTTL : : 2 : N
SBA[1] : 86 : output : 3.3-V LVTTL : : 2 : N SBA[0] : 86 : output : 3.3-V LVTTL : : 2 : N
GND* : 87 : : : : 2 : RD[7] : 87 : bidir : 3.3-V LVTTL : : 2 : N
SA[11] : 88 : output : 3.3-V LVTTL : : 2 : N SA[3] : 88 : output : 3.3-V LVTTL : : 2 : N
GND* : 89 : : : : 2 : RD[6] : 89 : bidir : 3.3-V LVTTL : : 2 : N
GND* : 90 : : : : 2 : RD[1] : 90 : bidir : 3.3-V LVTTL : : 2 : N
GND* : 91 : : : : 2 : RA[6] : 91 : input : 3.3-V LVTTL : : 2 : N
RA[1] : 92 : input : 3.3-V LVTTL : : 2 : N RD[0] : 92 : bidir : 3.3-V LVTTL : : 2 : N
GNDIO : 93 : gnd : : : : GNDIO : 93 : gnd : : : :
VCCIO2 : 94 : power : : 3.3V : 2 : VCCIO2 : 94 : power : : 3.3V : 2 :
RA[15] : 95 : input : 3.3-V LVTTL : : 2 : N RD[4] : 95 : bidir : 3.3-V LVTTL : : 2 : N
RA[3] : 96 : input : 3.3-V LVTTL : : 2 : N RD[3] : 96 : bidir : 3.3-V LVTTL : : 2 : N
RA[13] : 97 : input : 3.3-V LVTTL : : 2 : N RD[5] : 97 : bidir : 3.3-V LVTTL : : 2 : N
RD[2] : 98 : bidir : 3.3-V LVTTL : : 2 : N SA[6] : 98 : output : 3.3-V LVTTL : : 2 : N
RD[5] : 99 : bidir : 3.3-V LVTTL : : 2 : N GND* : 99 : : : : 2 :
RDdir : 100 : output : 3.3-V LVTTL : : 2 : N SA[1] : 100 : output : 3.3-V LVTTL : : 2 : N

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cpld/output_files/GR8RAM.pof
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cpld/output_files/GR8RAM.sta.rpt
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cpld/output_files/GR8RAM.sta.summary
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TimeQuest Timing Analyzer Summary TimeQuest Timing Analyzer Summary
------------------------------------------------------------ ------------------------------------------------------------
Type : Setup 'ARCLK'
Slack : -99.000
TNS : -99.000
Type : Setup 'DRCLK'
Slack : -99.000
TNS : -99.000
Type : Setup 'C25M' Type : Setup 'C25M'
Slack : -9.506 Slack : -9.555
TNS : -540.769 TNS : -547.115
Type : Hold 'ARCLK'
Slack : -16.276
TNS : -16.276
Type : Hold 'DRCLK'
Slack : -16.256
TNS : -16.256
Type : Hold 'C25M' Type : Hold 'C25M'
Slack : 1.639 Slack : 1.377
TNS : 0.000 TNS : 0.000
Type : Minimum Pulse Width 'ARCLK'
Slack : -29.500
TNS : -59.000
Type : Minimum Pulse Width 'DRCLK'
Slack : -29.500
TNS : -59.000
Type : Minimum Pulse Width 'C25M' Type : Minimum Pulse Width 'C25M'
Slack : -2.289 Slack : -2.289
TNS : -2.289 TNS : -2.289