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GR8RAM
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Comments, no actual changes to CPLD verilog

This commit is contained in:
Zane Kaminski 2020-02-16 22:03:57 -05:00
parent 88a4169ab6
commit 764b09ba6a
1 changed files with 2 additions and 1 deletions
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cpld/GR8RAM.v
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@ -140,13 +140,14 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
end
end
/* DEVSEL register and IOSTRB ROM enable */
always @(posedge C7M, negedge nRES) begin
if (~nRES) begin
REGEN <= 0;
IOROMEN <= 0;
end else begin
// Enable registers at end of S4 when IOSEL accessed (Cn00-CnFF).
if (S==4 & ~nIOSEL) REGEN <= 1;
if (S==4 & ~nIOSEL) REGEN <= 1'b1;
// Enable IOSTRB ROM when accessing CnXX in IOSEL ROM.
if (S==4 & ~nIOSEL) IOROMEN <= 1'b1;