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Comments, no actual changes to CPLD verilog
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@ -140,13 +140,14 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
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end
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end
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/* DEVSEL register and IOSTRB ROM enable */
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always @(posedge C7M, negedge nRES) begin
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if (~nRES) begin
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REGEN <= 0;
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IOROMEN <= 0;
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end else begin
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// Enable registers at end of S4 when IOSEL accessed (Cn00-CnFF).
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if (S==4 & ~nIOSEL) REGEN <= 1;
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if (S==4 & ~nIOSEL) REGEN <= 1'b1;
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// Enable IOSTRB ROM when accessing CnXX in IOSEL ROM.
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if (S==4 & ~nIOSEL) IOROMEN <= 1'b1;
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