Apple-2-HW/GR8RAM
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This commit is contained in:
Zane Kaminski 2023-06-07 18:52:59 -04:00
parent 9a1aa44d03
commit cdabd90e3a
40 changed files with 737 additions and 709 deletions
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102
cpld/GR8RAM.v
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@ -19,7 +19,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
/* Firmware select */ /* Firmware select */
input [1:0] SetFW; input [1:0] SetFW;
wire [1:0] SetROM = ~SetFW[1:0]; wire [1:0] SetROM = ~SetFW[1:0];
wire SetEN16MB = 0;//SetROM[1:0]==2'b11; wire SetENRestore = SetROM[1:0]==1'b11;
wire SetEN24bit = SetROM[1]; wire SetEN24bit = SetROM[1];
/* State counter from PHI0 rising edge */ /* State counter from PHI0 rising edge */
@ -58,12 +58,14 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC; always @(posedge PHI0) CXXXr <= RA[15:12]==4'hC;
/* Apple select signals */ /* Apple select signals */
wire RAMExists = (~SetEN24bit || SetEN16MB || ~Addr[23]); wire RAMExists = (!SetEN24bit || !Addr[23] || Addr[22] || Addr[21]);
wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF; wire BankSEL = REGEN && !nDEVSEL && RA[3:0]==4'hF;
wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3; wire SPITX1SEL = REGEN && !nDEVSEL && RA[3:0]==4'hD;
wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2; wire SPITX0SEL = REGEN && !nDEVSEL && RA[3:0]==4'hC;
wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1; wire RAMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h3;
wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0; wire AddrHSEL = REGEN && !nDEVSEL && RA[3:0]==4'h2;
wire AddrMSEL = REGEN && !nDEVSEL && RA[3:0]==4'h1;
wire AddrLSEL = REGEN && !nDEVSEL && RA[3:0]==4'h0;
/* IOROMEN control */ /* IOROMEN control */
reg IOROMEN = 0; reg IOROMEN = 0;
@ -78,7 +80,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
reg REGEN = 0; reg REGEN = 0;
always @(posedge C25M, negedge nRESr) begin always @(posedge C25M, negedge nRESr) begin
if (!nRESr) REGEN <= 0; if (!nRESr) REGEN <= 0;
else if (!nIOSEL) REGEN <= 1; else if (PS==8 && !nIOSEL) REGEN <= 1;
end end
/* Apple data bus */ /* Apple data bus */
@ -104,7 +106,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
if (PS==8 && AddrLSEL && !nWE) begin if (PS==8 && AddrLSEL && !nWE) begin
Addr[7:0] <= RD[7:0]; Addr[7:0] <= RD[7:0];
AddrIncM <= Addr[7] && ~RD[7]; AddrIncM <= Addr[7] && !RD[7];
end else if (AddrIncL) begin end else if (AddrIncL) begin
Addr[7:0] <= Addr[7:0]+1; Addr[7:0] <= Addr[7:0]+1;
AddrIncM <= Addr[7:0]==8'hFF; AddrIncM <= Addr[7:0]==8'hFF;
@ -112,7 +114,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
if (PS==8 && AddrMSEL && !nWE) begin if (PS==8 && AddrMSEL && !nWE) begin
Addr[15:8] <= RD[7:0]; Addr[15:8] <= RD[7:0];
AddrIncH <= Addr[15] && ~RD[7]; AddrIncH <= Addr[15] && !RD[7];
end else if (AddrIncM) begin end else if (AddrIncM) begin
Addr[15:8] <= Addr[15:8]+1; Addr[15:8] <= Addr[15:8]+1;
AddrIncH <= Addr[15:8]==8'hFF; AddrIncH <= Addr[15:8]==8'hFF;
@ -127,19 +129,26 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
end end
/* ROM bank register */ /* ROM bank register */
reg Bank = 0; reg Bank;
always @(posedge C25M, negedge nRESr) begin always @(posedge C25M, negedge nRESr) begin
if (~nRESr) Bank <= 0; if (!nRESr) Bank <= 0;
else if (PS==8 && BankSEL && !nWE) begin else if (PS==8 && BankSEL && !nWE) begin
Bank <= RD[0]; Bank <= RD[0];
end end
end end
/* Restore state */
reg RestoreDone = 0;
always @(posedge C25M) begin
if (!SetENRestore) RestoreDone <= 1;
else if (PS==8 && BankSEL && !nWE) begin
if (RD[1:0]==2'b11) RestoreDone <= 1;
end
end
/* SPI flash control signals */ /* SPI flash control signals */
output nFCS = FCKOE ? ~FCS : 1'bZ; output reg nFCS = 1;
reg FCS = 0; output FCK = FCKout;
output FCK = FCKOE ? FCKout : 1'bZ;
reg FCKOE = 0;
reg FCKout = 0; reg FCKout = 0;
inout MOSI = MOSIOE ? MOSIout : 1'bZ; inout MOSI = MOSIOE ? MOSIout : 1'bZ;
reg MOSIOE = 0; reg MOSIOE = 0;
@ -149,40 +158,39 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
0: begin // NOP CKE 0: begin // NOP CKE
FCKout <= 1'b1; FCKout <= 1'b1;
end 1: begin // ACT end 1: begin // ACT
FCKout <= ~(IS==5 || IS==6); FCKout <= !(IS==5 || IS==6);
end 2: begin // RD end 2: begin // RD
FCKout <= 1'b1; FCKout <= 1'b1;
end 3: begin // NOP CKE end 3: begin // NOP CKE
FCKout <= ~(IS==5 || IS==6); FCKout <= !(IS==5 || IS==6);
end 4: begin // NOP CKE end 4: begin // NOP CKE
FCKout <= 1'b1; FCKout <= 1'b1;
end 5: begin // NOP CKE end 5: begin // NOP CKE
FCKout <= ~(IS==5 || IS==6); FCKout <= !(IS==5 || IS==6);
end 6: begin // NOP CKE end 6: begin // NOP CKE
FCKout <= 1'b1; FCKout <= 1'b1;
end 7: begin // NOP CKE end 7: begin // NOP CKE
FCKout <= ~(IS==5 || IS==6); FCKout <= !(IS==5 || IS==6 || (!RestoreDone && SetENRestore && (SPITX0SEL || SPITX1SEL)));
end 8: begin // WR AP end 8: begin // WR AP
FCKout <= 1'b1; FCKout <= 1'b1;
end 9: begin // NOP CKE end 9: begin // NOP CKE
FCKout <= ~(IS==5); FCKout <= !(IS==5);
end 10: begin // PC all end 10: begin // PC all
FCKout <= 1'b1; FCKout <= 1'b1;
end 11: begin // AREF end 11: begin // AREF
FCKout <= ~(IS==5); FCKout <= !(IS==5);
end 12: begin // NOP CKE end 12: begin // NOP CKE
FCKout <= 1'b1; FCKout <= 1'b1;
end 13: begin // NOP CKE end 13: begin // NOP CKE
FCKout <= ~(IS==5); FCKout <= !(IS==5);
end 14: begin // NOP CKE end 14: begin // NOP CKE
FCKout <= 1'b1; FCKout <= 1'b1;
end 15: begin // NOP CKE end 15: begin // NOP CKE
FCKout <= ~(IS==5); FCKout <= !(IS==5);
end end
endcase endcase
FCS <= IS==4 || IS==5 || IS==6; nFCS <= !(IS==4 || IS==5 || IS==6);
MOSIOE <= IS==5; MOSIOE <= IS==5;
FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
end end
/* SPI flash MOSI control */ /* SPI flash MOSI control */
@ -214,13 +222,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
default MOSIout <= 1'b0; default MOSIout <= 1'b0;
endcase endcase
end 7: begin end 7: begin
case (LS[2:0]) if (nRESout) case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 4 3'h3: MOSIout <= 1'b1; // Command bit 4
3'h4: MOSIout <= 1'b0; // Address bit 20 3'h4: MOSIout <= 1'b0; // Address bit 20
3'h5: MOSIout <= 1'b0; // Address bit 12 3'h5: MOSIout <= 1'b0; // Address bit 12
3'h6: MOSIout <= 1'b0; // Address bit 4 3'h6: MOSIout <= 1'b0; // Address bit 4
default MOSIout <= 1'b0; default MOSIout <= 1'b0;
endcase endcase else MOSIout <= RA[0];
end 9: begin end 9: begin
case (LS[2:0]) case (LS[2:0])
3'h3: MOSIout <= 1'b1; // Command bit 3 3'h3: MOSIout <= 1'b1; // Command bit 3
@ -307,6 +315,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
4'h1: RDD[7:0] <= Addr[15:8]; 4'h1: RDD[7:0] <= Addr[15:8];
4'h2: RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] }; 4'h2: RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
4'h3: RDD[7:0] <= SD[7:0]; 4'h3: RDD[7:0] <= SD[7:0];
4'hF: RDD[7:0] <= { MISO, SD[6:0] };
default: RDD[7:0] <= SD[7:0]; default: RDD[7:0] <= SD[7:0];
endcase else RDD[7:0] <= SD[7:0]; endcase else RDD[7:0] <= SD[7:0];
end end
@ -403,7 +412,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
nRCS <= !RCKE; nRCS <= !RCKE;
nRAS <= 0; nRAS <= 0;
nCAS <= 0; nCAS <= 0;
nSWE <= ~(IS==1); nSWE <= !(IS==1);
SDOE <= 0; SDOE <= 0;
end default: begin // NOP CKD end default: begin // NOP CKD
RCKE <= 0; RCKE <= 0;
@ -432,27 +441,30 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
DQML <= 1'b1; DQML <= 1'b1;
DQMH <= 1'b1; DQMH <= 1'b1;
if (IS==6) begin if (IS==6) begin
SBA[1:0] <= { 2'b10 }; SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, LS[12:10] }; SA[12:0] <= { 10'b0011000100, LS[12:10] };
end else if (nIOSEL && nIOSTRB) begin end else if (nIOSEL && nIOSTRB) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000; SA[12:10] <= SetEN24bit ? { Addr[23], Addr[21:20] } : 3'b000;
SA[9:0] <= Addr[19:10]; SA[9:0] <= Addr[19:10];
end else begin end else if (!nIOSTRB) begin
SBA[1:0] <= 2'b10; SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] }; SA[12:0] <= { 10'b0011000100, Bank, 1'b1, RA[10] };
end else begin // IOSEL
SBA[1:0] <= 2'b10;
SA[12:0] <= { 10'b0011000100, !RestoreDone, 1'b0, RA[10] };
end end
end 2: begin // RD end 2: begin // RD
if (nIOSEL && nIOSTRB) begin if (nIOSEL && nIOSTRB) begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] }; SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0]; DQML <= Addr[0];
DQMH <= ~Addr[0]; DQMH <= !Addr[0];
end else begin end else begin
SBA[1:0] <= 2'b10; SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, RA[9:1]}; SA[12:0] <= { 4'b0011, RA[9:1]};
DQML <= RA[0]; DQML <= RA[0];
DQMH <= ~RA[0]; DQMH <= !RA[0];
end end
end 3: begin // NOP CKE end 3: begin // NOP CKE
DQML <= 1'b1; DQML <= 1'b1;
@ -484,12 +496,12 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
SBA[1:0] <= 2'b10; SBA[1:0] <= 2'b10;
SA[12:0] <= { 4'b0011, LS[9:1] }; SA[12:0] <= { 4'b0011, LS[9:1] };
DQML <= LS[0]; DQML <= LS[0];
DQMH <= ~LS[0]; DQMH <= !LS[0];
end else begin end else begin
SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 }; SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[22] : 1'b0 };
SA[12:0] <= { 4'b0011, Addr[9:1] }; SA[12:0] <= { 4'b0011, Addr[9:1] };
DQML <= Addr[0]; DQML <= Addr[0];
DQMH <= ~Addr[0]; DQMH <= !Addr[0];
end end
end 9: begin // NOP CKE end 9: begin // NOP CKE
DQML <= 1'b1; DQML <= 1'b1;

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@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681444899848 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681451537114 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444899862 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:01:39 2023 " "Processing started: Fri Apr 14 00:01:39 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444899862 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1681444899862 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681451537114 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 01:52:16 2023 " "Processing started: Fri Apr 14 01:52:16 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681451537114 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1681451537114 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1681444899862 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1681451537114 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1681444900157 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1681451537364 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1681444900188 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1681451537395 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1681444900188 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1681451537411 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13056 " "Peak virtual memory: 13056 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444900423 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:01:40 2023 " "Processing ended: Fri Apr 14 00:01:40 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444900423 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444900423 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444900423 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1681444900423 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13056 " "Peak virtual memory: 13056 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681451537634 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 01:52:17 2023 " "Processing ended: Fri Apr 14 01:52:17 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681451537634 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681451537634 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681451537634 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1681451537634 ""}

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cpld/db/GR8RAM.fit.qmsg
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@ -1,38 +1,38 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1681444896092 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1681451533260 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1681444896092 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1681451533260 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1681444896092 ""} { "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1681451533276 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681444896139 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681451533323 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681444896139 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681451533323 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1681444896232 ""} { "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1681451533416 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1681444896248 ""} { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1681451533432 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444896498 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1681444896498 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451533666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451533666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451533666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451533666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451533666 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1681451533666 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1681444896624 ""} { "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1681451533776 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1681444896639 ""} { "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1681451533791 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444896639 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444896639 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444896639 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444896639 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1681444896639 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681451533791 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681451533791 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681451533791 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681451533791 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1681451533791 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681444896639 ""} { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681451533808 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681444896639 ""} { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681451533808 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681444896654 ""} { "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681451533808 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681444896670 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681451533823 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 69 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681444896670 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681444896670 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 71 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681451533823 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681451533823 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681444896670 ""} { "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681451533823 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1681444896670 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1681451533838 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1681444896702 ""} { "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1681451533870 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1681444896748 ""} { "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1681451533917 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1681444896763 ""} { "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1681451533917 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1681444896763 ""} { "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1681451533917 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1681444896763 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1681451533917 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444896810 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451533964 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1681444896810 ""} { "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1681451533979 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1681444896965 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1681451534104 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444897139 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451534324 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1681444897139 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1681451534324 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1681444897811 ""} { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1681451535057 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444897811 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451535057 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1681444897857 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1681451535088 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "30 " "Router estimated average interconnect usage is 30% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "30 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1681444898076 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1681444898076 ""} { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1681451535324 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1681451535324 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444898310 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451535588 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1681444898325 ""} { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.29 " "Total time spent on timing analysis during the Fitter is 0.29 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1681451535605 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444898340 ""} { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451535605 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1681444898387 ""} { "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1681451535651 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1681444898434 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1681451535698 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13732 " "Peak virtual memory: 13732 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444898489 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:01:38 2023 " "Processing ended: Fri Apr 14 00:01:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444898489 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444898489 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444898489 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1681444898489 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13732 " "Peak virtual memory: 13732 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681451535760 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 01:52:15 2023 " "Processing ended: Fri Apr 14 01:52:15 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681451535760 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681451535760 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681451535760 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1681451535760 ""}

96
cpld/db/GR8RAM.hier_info
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@ -31,10 +31,10 @@ C25M => WRD[5].CLK
C25M => WRD[6].CLK C25M => WRD[6].CLK
C25M => WRD[7].CLK C25M => WRD[7].CLK
C25M => MOSIout.CLK C25M => MOSIout.CLK
C25M => FCKOE.CLK
C25M => MOSIOE.CLK C25M => MOSIOE.CLK
C25M => FCS.CLK C25M => nFCS~reg0.CLK
C25M => FCKout.CLK C25M => FCKout.CLK
C25M => RestoreDone.CLK
C25M => Bank.CLK C25M => Bank.CLK
C25M => AddrIncH.CLK C25M => AddrIncH.CLK
C25M => AddrIncM.CLK C25M => AddrIncM.CLK
@ -102,7 +102,8 @@ PHI0 => PHI0r1.DATAIN
nRES => nRESr.DATAIN nRES => nRESr.DATAIN
nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE nRESout <= nRESout~reg0.DB_MAX_OUTPUT_PORT_TYPE
SetFW[0] => Mux1.IN7 SetFW[0] => Mux1.IN7
SetFW[1] => RAMExists.IN1 SetFW[0] => Equal1.IN1
SetFW[1] => comb.IN1
SetFW[1] => RDD.OUTPUTSELECT SetFW[1] => RDD.OUTPUTSELECT
SetFW[1] => RDD.OUTPUTSELECT SetFW[1] => RDD.OUTPUTSELECT
SetFW[1] => RDD.OUTPUTSELECT SetFW[1] => RDD.OUTPUTSELECT
@ -112,6 +113,7 @@ SetFW[1] => SA.OUTPUTSELECT
SetFW[1] => SA.OUTPUTSELECT SetFW[1] => SA.OUTPUTSELECT
SetFW[1] => SBA.OUTPUTSELECT SetFW[1] => SBA.OUTPUTSELECT
SetFW[1] => MOSIout.DATAB SetFW[1] => MOSIout.DATAB
SetFW[1] => Equal1.IN0
INTin => INTout.DATAIN INTin => INTout.DATAIN
INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE INTout <= INTin.DB_MAX_OUTPUT_PORT_TYPE
DMAin => DMAout.DATAIN DMAin => DMAout.DATAIN
@ -122,7 +124,8 @@ nRDYout <= <VCC>
nINHout <= <VCC> nINHout <= <VCC>
RWout <= <VCC> RWout <= <VCC>
nDMAout <= <VCC> nDMAout <= <VCC>
RA[0] => Mux11.IN17 RA[0] => MOSIout.DATAA
RA[0] => Mux11.IN16
RA[0] => Mux12.IN17 RA[0] => Mux12.IN17
RA[0] => Mux13.IN17 RA[0] => Mux13.IN17
RA[0] => Mux14.IN17 RA[0] => Mux14.IN17
@ -131,14 +134,16 @@ RA[0] => Mux16.IN16
RA[0] => Mux17.IN16 RA[0] => Mux17.IN16
RA[0] => Mux18.IN16 RA[0] => Mux18.IN16
RA[0] => DQML.DATAA RA[0] => DQML.DATAA
RA[0] => Equal8.IN3
RA[0] => Equal9.IN3 RA[0] => Equal9.IN3
RA[0] => Equal10.IN2 RA[0] => Equal10.IN3
RA[0] => Equal11.IN3 RA[0] => Equal11.IN1
RA[0] => Equal12.IN3 RA[0] => Equal12.IN3
RA[0] => Equal13.IN10 RA[0] => Equal13.IN2
RA[0] => Equal14.IN3
RA[0] => Equal15.IN3
RA[0] => Equal16.IN10
RA[0] => DQMH.DATAA RA[0] => DQMH.DATAA
RA[1] => Mux11.IN16 RA[1] => Mux11.IN15
RA[1] => Mux12.IN16 RA[1] => Mux12.IN16
RA[1] => Mux13.IN16 RA[1] => Mux13.IN16
RA[1] => Mux14.IN16 RA[1] => Mux14.IN16
@ -147,13 +152,15 @@ RA[1] => Mux16.IN15
RA[1] => Mux17.IN15 RA[1] => Mux17.IN15
RA[1] => Mux18.IN15 RA[1] => Mux18.IN15
RA[1] => SA.DATAA RA[1] => SA.DATAA
RA[1] => Equal8.IN2
RA[1] => Equal9.IN2 RA[1] => Equal9.IN2
RA[1] => Equal10.IN3 RA[1] => Equal10.IN0
RA[1] => Equal11.IN2 RA[1] => Equal11.IN0
RA[1] => Equal12.IN2 RA[1] => Equal12.IN2
RA[1] => Equal13.IN9 RA[1] => Equal13.IN3
RA[2] => Mux11.IN15 RA[1] => Equal14.IN2
RA[1] => Equal15.IN2
RA[1] => Equal16.IN9
RA[2] => Mux11.IN14
RA[2] => Mux12.IN15 RA[2] => Mux12.IN15
RA[2] => Mux13.IN15 RA[2] => Mux13.IN15
RA[2] => Mux14.IN15 RA[2] => Mux14.IN15
@ -162,13 +169,15 @@ RA[2] => Mux16.IN14
RA[2] => Mux17.IN14 RA[2] => Mux17.IN14
RA[2] => Mux18.IN14 RA[2] => Mux18.IN14
RA[2] => SA.DATAA RA[2] => SA.DATAA
RA[2] => Equal8.IN1
RA[2] => Equal9.IN1 RA[2] => Equal9.IN1
RA[2] => Equal10.IN1 RA[2] => Equal10.IN2
RA[2] => Equal11.IN1 RA[2] => Equal11.IN3
RA[2] => Equal12.IN1 RA[2] => Equal12.IN1
RA[2] => Equal13.IN8 RA[2] => Equal13.IN1
RA[3] => Mux11.IN14 RA[2] => Equal14.IN1
RA[2] => Equal15.IN1
RA[2] => Equal16.IN8
RA[3] => Mux11.IN13
RA[3] => Mux12.IN14 RA[3] => Mux12.IN14
RA[3] => Mux13.IN14 RA[3] => Mux13.IN14
RA[3] => Mux14.IN14 RA[3] => Mux14.IN14
@ -177,34 +186,36 @@ RA[3] => Mux16.IN13
RA[3] => Mux17.IN13 RA[3] => Mux17.IN13
RA[3] => Mux18.IN13 RA[3] => Mux18.IN13
RA[3] => SA.DATAA RA[3] => SA.DATAA
RA[3] => Equal8.IN0
RA[3] => Equal9.IN0 RA[3] => Equal9.IN0
RA[3] => Equal10.IN0 RA[3] => Equal10.IN1
RA[3] => Equal11.IN0 RA[3] => Equal11.IN2
RA[3] => Equal12.IN0 RA[3] => Equal12.IN0
RA[3] => Equal13.IN7 RA[3] => Equal13.IN0
RA[3] => Equal14.IN0
RA[3] => Equal15.IN0
RA[3] => Equal16.IN7
RA[4] => SA.DATAA RA[4] => SA.DATAA
RA[4] => Equal13.IN6 RA[4] => Equal16.IN6
RA[5] => SA.DATAA RA[5] => SA.DATAA
RA[5] => Equal13.IN5 RA[5] => Equal16.IN5
RA[6] => SA.DATAA RA[6] => SA.DATAA
RA[6] => Equal13.IN4 RA[6] => Equal16.IN4
RA[7] => SA.DATAA RA[7] => SA.DATAA
RA[7] => Equal13.IN3 RA[7] => Equal16.IN3
RA[8] => SA.DATAA RA[8] => SA.DATAA
RA[8] => Equal13.IN2 RA[8] => Equal16.IN2
RA[9] => SA.DATAA RA[9] => SA.DATAA
RA[9] => Equal13.IN1 RA[9] => Equal16.IN1
RA[10] => SA.DATAA RA[10] => SA.DATAA
RA[10] => Equal13.IN0 RA[10] => Equal16.IN0
RA[11] => SA.DATAA RA[11] => ~NO_FANOUT~
RA[12] => Equal7.IN1 RA[12] => Equal8.IN1
RA[13] => Equal7.IN0 RA[13] => Equal8.IN0
RA[14] => Equal7.IN3 RA[14] => Equal8.IN3
RA[15] => Equal7.IN2 RA[15] => Equal8.IN2
nWE => comb.IN1 nWE => comb.IN1
nWE => RCKE.IN1 nWE => RCKE.IN1
nWE => always9.IN1 nWE => always10.IN1
nWE => always8.IN1 nWE => always8.IN1
nWE => always8.IN1 nWE => always8.IN1
nWE => always8.IN1 nWE => always8.IN1
@ -218,10 +229,10 @@ RD[6] <> RD[6]
RD[7] <> RD[7] RD[7] <> RD[7]
RAdir <= <VCC> RAdir <= <VCC>
RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE RDdir <= comb.DB_MAX_OUTPUT_PORT_TYPE
nIOSEL => always15.IN0 nIOSEL => always16.IN0
nIOSEL => IOROMEN.OUTPUTSELECT nIOSEL => IOROMEN.OUTPUTSELECT
nIOSEL => comb.IN1 nIOSEL => comb.IN1
nIOSEL => REGEN.ENA nIOSEL => always7.IN1
nDEVSEL => RDD.OUTPUTSELECT nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => RDD.OUTPUTSELECT nDEVSEL => RDD.OUTPUTSELECT
@ -233,8 +244,10 @@ nDEVSEL => RDD.OUTPUTSELECT
nDEVSEL => comb.IN1 nDEVSEL => comb.IN1
nDEVSEL => comb.IN1 nDEVSEL => comb.IN1
nDEVSEL => comb.IN1 nDEVSEL => comb.IN1
nIOSTRB => always15.IN1 nIOSTRB => always16.IN1
nIOSTRB => comb.IN1 nIOSTRB => comb.IN1
nIOSTRB => SA.OUTPUTSELECT
nIOSTRB => SA.DATAA
nIOSTRB => IOROMRES.IN1 nIOSTRB => IOROMRES.IN1
SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE SBA[0] <= SBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE SBA[1] <= SBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
@ -266,9 +279,10 @@ SD[4] <> SD[4]
SD[5] <> SD[5] SD[5] <> SD[5]
SD[6] <> SD[6] SD[6] <> SD[6]
SD[7] <> SD[7] SD[7] <> SD[7]
nFCS <= nFCS.DB_MAX_OUTPUT_PORT_TYPE nFCS <= nFCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
FCK <= FCK.DB_MAX_OUTPUT_PORT_TYPE FCK <= FCKout.DB_MAX_OUTPUT_PORT_TYPE
MISO => WRD.DATAB MISO => WRD.DATAB
MISO => Mux11.IN19
MOSI <> MOSI MOSI <> MOSI

BIN
cpld/db/GR8RAM.hif
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cpld/db/GR8RAM.map.cdb
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cpld/db/GR8RAM.map.hdb
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42
cpld/db/GR8RAM.map.qmsg
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@ -1,20 +1,22 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681444876827 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681451514506 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444876827 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:01:16 2023 " "Processing started: Fri Apr 14 00:01:16 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444876827 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444876827 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681451514506 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 01:51:54 2023 " "Processing started: Fri Apr 14 01:51:54 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681451514506 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451514506 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444876827 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451514506 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1681444877218 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1681451514850 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1681444877218 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1681451514850 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(85) " "Verilog HDL warning at GR8RAM.v(85): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681444893408 ""} { "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 GR8RAM.v(22) " "Verilog HDL Expression warning at GR8RAM.v(22): truncated literal to match 1 bits" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 22 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1681451530317 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(261) " "Verilog HDL warning at GR8RAM.v(261): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 261 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681444893408 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(87) " "Verilog HDL warning at GR8RAM.v(87): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 87 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681451530317 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1681444893408 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444893408 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(269) " "Verilog HDL warning at GR8RAM.v(269): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 269 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681451530317 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1681444893440 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1681451530317 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451530317 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(31) " "Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1681451530364 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(36) " "Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 36 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(31) " "Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451530364 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(109) " "Verilog HDL assignment warning at GR8RAM.v(109): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(36) " "Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 36 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451530364 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451530364 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(124) " "Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444893455 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(119) " "Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 119 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451530364 "|GR8RAM"}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1681444893877 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451530364 "|GR8RAM"}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 541 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 544 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 543 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 542 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 545 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444894049 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1681444894049 ""} { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1681451530786 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1681444894252 ""} { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451530973 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451530973 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451530973 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451530973 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451530973 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451530973 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451530973 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1681451530973 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "305 " "Implemented 305 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1681444894268 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1681444894268 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1681444894268 ""} { "Info" "ICUT_CUT_TM_LCELLS" "225 " "Implemented 225 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1681444894268 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1681444894268 ""} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1681451531459 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444894331 ""} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "RA\[11\] " "No output dependent on input pin \"RA\[11\]\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 56 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1681451531473 "|GR8RAM|RA[11]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1681451531473 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13092 " "Peak virtual memory: 13092 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444894347 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:01:34 2023 " "Processing ended: Fri Apr 14 00:01:34 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444894347 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444894347 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444894347 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444894347 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "316 " "Implemented 316 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1681451531473 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1681451531473 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1681451531473 ""} { "Info" "ICUT_CUT_TM_LCELLS" "236 " "Implemented 236 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1681451531473 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1681451531473 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451531520 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13092 " "Peak virtual memory: 13092 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681451531551 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 01:52:11 2023 " "Processing ended: Fri Apr 14 01:52:11 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681451531551 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681451531551 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:39 " "Total CPU time (on all processors): 00:00:39" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681451531551 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451531551 ""}

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cpld/db/GR8RAM.pre_map.hdb
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cpld/db/GR8RAM.root_partition.map.reg_db.cdb
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cpld/db/GR8RAM.routing.rdb
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cpld/db/GR8RAM.rtlv.hdb
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cpld/db/GR8RAM.sta.qmsg
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@ -1,22 +1,22 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681444902112 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681451539137 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444902128 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:01:41 2023 " "Processing started: Fri Apr 14 00:01:41 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444902128 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1681444902128 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681451539137 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 01:52:18 2023 " "Processing started: Fri Apr 14 01:52:18 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681451539137 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1681451539137 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1681444902128 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1681451539137 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1681444902237 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1681451539246 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1681444902472 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1681451539387 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1681444902472 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1681451539387 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444902534 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451539434 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444902534 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451539434 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1681444902597 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1681451539497 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1681444903003 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1681451539904 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1681444903068 ""} { "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1681451539965 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1681444903083 ""} { "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1681451539981 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1681444903115 ""} { "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1681451539996 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.252 " "Worst-case setup slack is 14.252" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.252 0.000 C25M " " 14.252 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903130 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup 13.632 " "Worst-case setup slack is 13.632" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540012 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540012 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 13.632 0.000 C25M " " 13.632 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540012 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451540012 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.394 " "Worst-case hold slack is 1.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.394 0.000 C25M " " 1.394 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903130 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 1.404 " "Worst-case hold slack is 1.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540012 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540012 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.404 0.000 C25M " " 1.404 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540012 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451540012 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.179 " "Worst-case recovery slack is 33.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.179 0.000 C25M " " 33.179 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903130 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903130 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.394 " "Worst-case recovery slack is 33.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.394 0.000 C25M " " 33.394 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451540027 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.267 " "Worst-case removal slack is 6.267" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.267 0.000 C25M " " 6.267 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903146 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 6.052 " "Worst-case removal slack is 6.052" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.052 0.000 C25M " " 6.052 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451540027 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444903146 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444903146 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451540043 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451540043 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1681444903193 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1681451540111 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681444903208 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681451540142 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681444903224 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681451540142 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13051 " "Peak virtual memory: 13051 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444903292 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:01:43 2023 " "Processing ended: Fri Apr 14 00:01:43 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444903292 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444903292 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444903292 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681444903292 ""} { "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13053 " "Peak virtual memory: 13053 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681451540209 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 01:52:20 2023 " "Processing ended: Fri Apr 14 01:52:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681451540209 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681451540209 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681451540209 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681451540209 ""}

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cpld/db/GR8RAM.sta_cmp.5_slow.tdb
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681444781029 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1681451453154 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444781029 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 13 23:59:40 2023 " "Processing started: Thu Apr 13 23:59:40 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444781029 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444781029 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681451453170 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 01:50:52 2023 " "Processing started: Fri Apr 14 01:50:52 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681451453170 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451453170 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444781029 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451453170 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1681444781402 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1681451453502 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1681444781402 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1681451453502 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(85) " "Verilog HDL warning at GR8RAM.v(85): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 85 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681444798192 ""} { "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "1 GR8RAM.v(22) " "Verilog HDL Expression warning at GR8RAM.v(22): truncated literal to match 1 bits" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 22 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1681451469792 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(261) " "Verilog HDL warning at GR8RAM.v(261): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 261 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681444798192 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(87) " "Verilog HDL warning at GR8RAM.v(87): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 87 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681451469792 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1681444798192 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444798192 ""} { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(269) " "Verilog HDL warning at GR8RAM.v(269): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 269 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1681451469792 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1681444798239 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1681451469792 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451469792 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(31) " "Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798254 "|GR8RAM"} { "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1681451469839 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(36) " "Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 36 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798254 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(31) " "Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 31 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451469839 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(109) " "Verilog HDL assignment warning at GR8RAM.v(109): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 109 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798254 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(36) " "Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 36 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451469839 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(117) " "Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798270 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(111) " "Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 111 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451469839 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(124) " "Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681444798270 "|GR8RAM"} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(119) " "Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 119 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451469839 "|GR8RAM"}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1681444798739 ""} { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1681451469839 "|GR8RAM"}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 541 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 544 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 543 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 542 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 545 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 540 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 539 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681444798911 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1681444798911 ""} { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Analysis & Synthesis" 0 -1 1681451470277 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1681444799194 ""} { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451470449 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451470449 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451470449 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451470449 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451470449 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451470449 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451470449 "|GR8RAM|RAdir"} { "Warning" "WMLS_MLS_STUCK_PIN" "SA\[12\] GND " "Pin \"SA\[12\]\" is stuck at GND" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 433 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1681451470449 "|GR8RAM|SA[12]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1681451470449 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "305 " "Implemented 305 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1681444799208 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1681444799208 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1681444799208 ""} { "Info" "ICUT_CUT_TM_LCELLS" "225 " "Implemented 225 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1681444799208 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1681444799208 ""} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1681451470954 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444799270 ""} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "RA\[11\] " "No output dependent on input pin \"RA\[11\]\"" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 56 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1681451470954 "|GR8RAM|RA[11]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1681451470954 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13091 " "Peak virtual memory: 13091 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444799301 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 13 23:59:59 2023 " "Processing ended: Thu Apr 13 23:59:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444799301 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444799301 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444799301 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1681444799301 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "314 " "Implemented 314 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1681451470970 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1681451470970 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1681451470970 ""} { "Info" "ICUT_CUT_TM_LCELLS" "234 " "Implemented 234 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1681451470970 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1681451470970 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1681444800872 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451471017 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444800888 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:00:00 2023 " "Processing started: Fri Apr 14 00:00:00 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444800888 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1681444800888 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13092 " "Peak virtual memory: 13092 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681451471048 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 01:51:11 2023 " "Processing ended: Fri Apr 14 01:51:11 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681451471048 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681451471048 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:40 " "Total CPU time (on all processors): 00:00:40" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681451471048 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1681451471048 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1681444800888 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1681451472626 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1681444800982 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681451472634 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 01:51:12 2023 " "Processing started: Fri Apr 14 01:51:12 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681451472634 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1681451472634 ""}
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1681444800982 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1681451472634 ""}
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1681444800982 ""} { "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1681451472738 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1681444801107 ""} { "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1681451472738 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1681444801107 ""} { "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1681451472738 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1681444801107 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1681451472817 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681444801153 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1681451472817 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681444801169 ""} { "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1681451472817 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1681444801263 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681451472864 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1681444801278 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1681451472864 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681444801528 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1681444801528 ""} { "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1681451472957 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1681444801716 ""} { "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1681451472973 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1681444801747 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451473207 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451473207 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451473207 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451473207 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1681451473207 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1681451473207 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444801747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444801747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444801747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681444801747 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1681444801747 ""} { "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1681451473318 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681444801747 ""} { "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1681451473332 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681444801747 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681451473332 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681451473332 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 40.000 C25M " " 40.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681451473332 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 978.000 PHI0 " " 978.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1681451473332 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1681451473332 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681444801747 ""} { "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681451473348 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681444801779 ""} { "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1681451473348 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 69 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681444801779 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681444801779 ""} { "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681451473348 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681444801779 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681451473363 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1681444801779 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nRESr Global clock " "Automatically promoted some destinations of signal \"nRESr\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "IOROMEN " "Destination \"IOROMEN\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 71 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1681451473363 ""} } { { "GR8RAM.v" "" { Text "Y:/Repos/GR8RAM/cpld/GR8RAM.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1681451473363 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1681444801810 ""} { "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1681451473363 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1681444801857 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1681451473379 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1681444801857 ""} { "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1681451473410 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1681444801857 ""} { "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1681451473457 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1681444801857 ""} { "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1681451473457 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444801919 ""} { "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1681451473457 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1681444801919 ""} { "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1681451473457 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1681444802060 ""} { "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451473505 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444802294 ""} { "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1681451473520 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1681444802310 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1681451473657 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1681444803044 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451473845 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444803044 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1681451473845 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1681444803092 ""} { "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1681451474547 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "32 " "Router estimated average interconnect usage is 32% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "32 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1681444803327 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1681444803327 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451474547 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444803607 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1681451474601 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.32 " "Total time spent on timing analysis during the Fitter is 0.32 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1681444803622 ""} { "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "28 " "Router estimated average interconnect usage is 28% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "28 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 28% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Y:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 28% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1681451474820 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1681451474820 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681444803638 ""} { "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451475054 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1681444803685 ""} { "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.30 " "Total time spent on timing analysis during the Fitter is 0.30 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1681451475054 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1681444803732 ""} { "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1681451475070 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13735 " "Peak virtual memory: 13735 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444803779 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:00:03 2023 " "Processing ended: Fri Apr 14 00:00:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444803779 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444803779 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444803779 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1681444803779 ""} { "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1681451475117 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1681444805211 ""} { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1681451475180 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444805211 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:00:05 2023 " "Processing started: Fri Apr 14 00:00:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444805211 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1681444805211 ""} { "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13732 " "Peak virtual memory: 13732 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681451475226 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 01:51:15 2023 " "Processing ended: Fri Apr 14 01:51:15 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681451475226 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681451475226 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681451475226 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1681451475226 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1681444805211 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1681451476607 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1681444805477 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681451476621 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 01:51:16 2023 " "Processing started: Fri Apr 14 01:51:16 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681451476621 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1681451476621 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1681444805508 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1681451476621 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1681444805524 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1681451476903 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13055 " "Peak virtual memory: 13055 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444805748 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:00:05 2023 " "Processing ended: Fri Apr 14 00:00:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444805748 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444805748 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444805748 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1681444805748 ""} { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1681451476934 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1681444806469 ""} { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1681451476949 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1681444807407 ""} { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13056 " "Peak virtual memory: 13056 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681451477168 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 01:51:17 2023 " "Processing ended: Fri Apr 14 01:51:17 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681451477168 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681451477168 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681451477168 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1681451477168 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681444807407 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 00:00:07 2023 " "Processing started: Fri Apr 14 00:00:07 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681444807407 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1681444807407 ""} { "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1681451477955 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1681444807407 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1681451478695 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1681444807517 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1681451478695 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 14 01:51:18 2023 " "Processing started: Fri Apr 14 01:51:18 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1681451478695 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1681451478695 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1681444807689 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1681451478695 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1681444807689 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1681451478788 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444807735 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1681451478929 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444807735 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1681451478929 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1681444807802 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451478980 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1681444808204 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451478980 ""}
{ "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1681444808267 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1681451479038 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1681444808282 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1681451479430 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1681444808314 ""} { "Info" "ISTA_SDC_FOUND" "GR8RAM.sdc " "Reading SDC File: 'GR8RAM.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1681451479507 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 14.271 " "Worst-case setup slack is 14.271" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808314 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808314 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.271 0.000 C25M " " 14.271 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808314 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808314 ""} { "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1681451479523 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.385 " "Worst-case hold slack is 1.385" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 C25M " " 1.385 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808329 ""} { "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1681451479554 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 32.601 " "Worst-case recovery slack is 32.601" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 32.601 0.000 C25M " " 32.601 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808329 ""} { "Info" "ISTA_WORST_CASE_SLACK" "setup 13.711 " "Worst-case setup slack is 13.711" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 13.711 0.000 C25M " " 13.711 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479554 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451479554 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 6.845 " "Worst-case removal slack is 6.845" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.845 0.000 C25M " " 6.845 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808329 ""} { "Info" "ISTA_WORST_CASE_SLACK" "hold 1.401 " "Worst-case hold slack is 1.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.401 0.000 C25M " " 1.401 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479554 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451479554 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681444808329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681444808329 ""} { "Info" "ISTA_WORST_CASE_SLACK" "recovery 33.388 " "Worst-case recovery slack is 33.388" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 33.388 0.000 C25M " " 33.388 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451479570 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1681444808376 ""} { "Info" "ISTA_WORST_CASE_SLACK" "removal 6.058 " "Worst-case removal slack is 6.058" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.058 0.000 C25M " " 6.058 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451479570 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681444808407 ""} { "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 19.734 " "Worst-case minimum pulse width slack is 19.734" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 19.734 0.000 C25M " " 19.734 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 488.734 0.000 PHI0 " " 488.734 0.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1681451479570 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1681451479570 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681444808407 ""} { "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1681451479616 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13053 " "Peak virtual memory: 13053 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681444808471 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 00:00:08 2023 " "Processing ended: Fri Apr 14 00:00:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681444808471 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681444808471 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681444808471 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681444808471 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681451479632 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus Prime Full Compilation was successful. 0 errors, 19 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681444809260 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1681451479632 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "13053 " "Peak virtual memory: 13053 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1681451479695 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 14 01:51:19 2023 " "Processing ended: Fri Apr 14 01:51:19 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1681451479695 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1681451479695 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1681451479695 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681451479695 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 23 s " "Quartus Prime Full Compilation was successful. 0 errors, 23 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1681451480510 ""}

BIN
cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
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Binary file not shown.

12
cpld/output_files/GR8RAM.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for GR8RAM Assembler report for GR8RAM
Fri Apr 14 00:01:40 2023 Fri Apr 14 01:52:17 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Apr 14 00:01:40 2023 ; ; Assembler Status ; Successful - Fri Apr 14 01:52:17 2023 ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
; Option ; Setting ; ; Option ; Setting ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
; JTAG usercode ; 0x00166C15 ; ; JTAG usercode ; 0x00162AE9 ;
; Checksum ; 0x00167085 ; ; Checksum ; 0x00162DE9 ;
+----------------+-------------------------------------------------------+ +----------------+-------------------------------------------------------+
@ -78,14 +78,14 @@ https://fpgasoftware.intel.com/eula.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Assembler Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Fri Apr 14 00:01:39 2023 Info: Processing started: Fri Apr 14 01:52:16 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13056 megabytes Info: Peak virtual memory: 13056 megabytes
Info: Processing ended: Fri Apr 14 00:01:40 2023 Info: Processing ended: Fri Apr 14 01:52:17 2023
Info: Elapsed time: 00:00:01 Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:01

2
cpld/output_files/GR8RAM.done
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@ -1 +1 @@
Fri Apr 14 00:01:44 2023 Fri Apr 14 01:52:20 2023

228
cpld/output_files/GR8RAM.fit.rpt
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@ -1,5 +1,5 @@
Fitter report for GR8RAM Fitter report for GR8RAM
Fri Apr 14 00:01:38 2023 Fri Apr 14 01:52:15 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -57,14 +57,14 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+ +---------------------------------------------------------------------+
; Fitter Summary ; ; Fitter Summary ;
+-----------------------+---------------------------------------------+ +-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Fri Apr 14 00:01:38 2023 ; ; Fitter Status ; Successful - Fri Apr 14 01:52:15 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 220 / 240 ( 92 % ) ; ; Total logic elements ; 233 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ; ; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
@ -150,28 +150,28 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+---------------------------------------------+-----------------------+ +---------------------------------------------+-----------------------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+-----------------------+ +---------------------------------------------+-----------------------+
; Total logic elements ; 220 / 240 ( 92 % ) ; ; Total logic elements ; 233 / 240 ( 97 % ) ;
; -- Combinational with no register ; 120 ; ; -- Combinational with no register ; 133 ;
; -- Register only ; 1 ; ; -- Register only ; 1 ;
; -- Combinational with a register ; 99 ; ; -- Combinational with a register ; 99 ;
; ; ; ; ; ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 120 ; ; -- 4 input functions ; 128 ;
; -- 3 input functions ; 32 ; ; -- 3 input functions ; 37 ;
; -- 2 input functions ; 66 ; ; -- 2 input functions ; 66 ;
; -- 1 input functions ; 1 ; ; -- 1 input functions ; 1 ;
; -- 0 input functions ; 0 ; ; -- 0 input functions ; 0 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 187 ; ; -- normal mode ; 200 ;
; -- arithmetic mode ; 33 ; ; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 3 ; ; -- qfbk mode ; 2 ;
; -- register cascade mode ; 0 ; ; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 49 ; ; -- synchronous clear/load mode ; 48 ;
; -- asynchronous clear/load mode ; 30 ; ; -- asynchronous clear/load mode ; 30 ;
; ; ; ; ; ;
; Total registers ; 100 / 240 ( 42 % ) ; ; Total registers ; 100 / 240 ( 42 % ) ;
; Total LABs ; 23 / 24 ( 96 % ) ; ; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 37 ; ; Logic elements in carry chains ; 37 ;
; Virtual pins ; 0 ; ; Virtual pins ; 0 ;
; I/O pins ; 80 / 80 ( 100 % ) ; ; I/O pins ; 80 / 80 ( 100 % ) ;
@ -185,11 +185,11 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; Global signals ; 2 ; ; Global signals ; 2 ;
; -- Global clocks ; 2 / 4 ( 50 % ) ; ; -- Global clocks ; 2 / 4 ( 50 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 37.0% / 38.2% / 35.8% ; ; Average interconnect usage (total/H/V) ; 41.0% / 42.7% / 39.2% ;
; Peak interconnect usage (total/H/V) ; 37.0% / 38.2% / 35.8% ; ; Peak interconnect usage (total/H/V) ; 41.0% / 42.7% / 39.2% ;
; Maximum fan-out ; 99 ; ; Maximum fan-out ; 99 ;
; Highest non-global fan-out ; 43 ; ; Highest non-global fan-out ; 50 ;
; Total fan-out ; 1019 ; ; Total fan-out ; 1065 ;
; Average fan-out ; 3.40 ; ; Average fan-out ; 3.40 ;
+---------------------------------------------+-----------------------+ +---------------------------------------------+-----------------------+
@ -202,31 +202,31 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 99 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 99 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ; ; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 2 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ; no ;
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; ; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ; ; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ; no ;
; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ; ; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 8 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ; ; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 10 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ; no ;
; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; ; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; ; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; ; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; ; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ; ; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ; no ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+ +----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+----------------+
@ -238,7 +238,7 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; yes ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; yes ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
@ -251,9 +251,9 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; - ; - ;
; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
@ -261,7 +261,7 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
@ -279,22 +279,22 @@ The pin-out file can be found in Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ; ; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ;
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ;
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ;
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ;
; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ;
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ;
; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ;
; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~2 ; - ; ; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~3 ; - ;
; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; ; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; ; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ; ; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ; ; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -438,7 +438,7 @@ Note: User assignments will override these defaults. The user specified values a
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; |GR8RAM ; 220 (220) ; 100 ; 0 ; 80 ; 0 ; 120 (120) ; 1 (1) ; 99 (99) ; 37 (37) ; 4 (4) ; |GR8RAM ; GR8RAM ; work ; ; |GR8RAM ; 233 (233) ; 100 ; 0 ; 80 ; 0 ; 133 (133) ; 1 (1) ; 99 (99) ; 37 (37) ; 3 (3) ; |GR8RAM ; GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -457,6 +457,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; nINHout ; Output ; -- ; ; nINHout ; Output ; -- ;
; RWout ; Output ; -- ; ; RWout ; Output ; -- ;
; nDMAout ; Output ; -- ; ; nDMAout ; Output ; -- ;
; RA[11] ; Input ; (0) ;
; RAdir ; Output ; -- ; ; RAdir ; Output ; -- ;
; RDdir ; Output ; -- ; ; RDdir ; Output ; -- ;
; SBA[0] ; Output ; -- ; ; SBA[0] ; Output ; -- ;
@ -504,15 +505,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; DMAin ; Input ; (1) ; ; DMAin ; Input ; (1) ;
; PHI0 ; Input ; (0) ; ; PHI0 ; Input ; (0) ;
; nWE ; Input ; (1) ; ; nWE ; Input ; (1) ;
; nIOSTRB ; Input ; (1) ;
; nIOSEL ; Input ; (1) ;
; SetFW[1] ; Input ; (1) ; ; SetFW[1] ; Input ; (1) ;
; nDEVSEL ; Input ; (1) ; ; nDEVSEL ; Input ; (1) ;
; nIOSEL ; Input ; (1) ;
; nIOSTRB ; Input ; (1) ;
; C25M ; Input ; (0) ; ; C25M ; Input ; (0) ;
; RA[1] ; Input ; (1) ; ; RA[1] ; Input ; (1) ;
; RA[0] ; Input ; (1) ;
; RA[2] ; Input ; (1) ; ; RA[2] ; Input ; (1) ;
; RA[3] ; Input ; (1) ; ; RA[3] ; Input ; (1) ;
; RA[0] ; Input ; (1) ;
; RA[4] ; Input ; (1) ; ; RA[4] ; Input ; (1) ;
; RA[5] ; Input ; (1) ; ; RA[5] ; Input ; (1) ;
; RA[6] ; Input ; (1) ; ; RA[6] ; Input ; (1) ;
@ -520,14 +521,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RA[8] ; Input ; (1) ; ; RA[8] ; Input ; (1) ;
; RA[9] ; Input ; (1) ; ; RA[9] ; Input ; (1) ;
; RA[10] ; Input ; (1) ; ; RA[10] ; Input ; (1) ;
; RA[11] ; Input ; (1) ; ; SetFW[0] ; Input ; (1) ;
; nRES ; Input ; (1) ; ; nRES ; Input ; (1) ;
; RA[14] ; Input ; (1) ; ; RA[14] ; Input ; (1) ;
; RA[15] ; Input ; (1) ; ; RA[15] ; Input ; (1) ;
; RA[12] ; Input ; (1) ; ; RA[12] ; Input ; (1) ;
; RA[13] ; Input ; (1) ; ; RA[13] ; Input ; (1) ;
; MISO ; Input ; (1) ; ; MISO ; Input ; (1) ;
; SetFW[0] ; Input ; (1) ;
+----------+----------+---------------+ +----------+----------+---------------+
@ -537,20 +537,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
; C25M ; PIN_64 ; 99 ; Clock ; yes ; Global Clock ; GCLK3 ; ; C25M ; PIN_64 ; 99 ; Clock ; yes ; Global Clock ; GCLK3 ;
; Equal0~0 ; LC_X3_Y2_N7 ; 20 ; Clock enable ; no ; -- ; -- ; ; Equal0~0 ; LC_X3_Y2_N3 ; 20 ; Clock enable ; no ; -- ; -- ;
; Equal17~0 ; LC_X6_Y2_N9 ; 8 ; Clock enable ; no ; -- ; -- ; ; Equal21~0 ; LC_X5_Y2_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
; FCKOE ; LC_X2_Y2_N6 ; 2 ; Output enable ; no ; -- ; -- ; ; IOROMRES~4 ; LC_X3_Y3_N5 ; 1 ; Async. clear ; no ; -- ; -- ;
; IOROMRES~3 ; LC_X3_Y4_N5 ; 1 ; Async. clear ; no ; -- ; -- ; ; MOSIOE ; LC_X3_Y2_N9 ; 1 ; Output enable ; no ; -- ; -- ;
; MOSIOE ; LC_X2_Y2_N3 ; 1 ; Output enable ; no ; -- ; -- ;
; PHI0 ; PIN_41 ; 3 ; Clock ; no ; -- ; -- ; ; PHI0 ; PIN_41 ; 3 ; Clock ; no ; -- ; -- ;
; PS[0] ; LC_X5_Y2_N9 ; 42 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; ; PS[0] ; LC_X4_Y1_N5 ; 49 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ;
; PS[2] ; LC_X5_Y2_N7 ; 28 ; Sync. clear, Sync. load ; no ; -- ; -- ; ; PS[2] ; LC_X4_Y2_N7 ; 29 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; SDOE ; LC_X7_Y1_N5 ; 8 ; Output enable ; no ; -- ; -- ; ; SDOE ; LC_X5_Y2_N4 ; 8 ; Output enable ; no ; -- ; -- ;
; always8~1 ; LC_X6_Y4_N9 ; 8 ; Sync. load ; no ; -- ; -- ; ; always8~2 ; LC_X5_Y2_N6 ; 8 ; Sync. load ; no ; -- ; -- ;
; always8~2 ; LC_X6_Y4_N5 ; 9 ; Sync. load ; no ; -- ; -- ; ; always8~3 ; LC_X6_Y1_N5 ; 9 ; Sync. load ; no ; -- ; -- ;
; always8~3 ; LC_X6_Y3_N9 ; 9 ; Sync. load ; no ; -- ; -- ; ; always8~4 ; LC_X6_Y1_N7 ; 9 ; Sync. load ; no ; -- ; -- ;
; comb~2 ; LC_X5_Y3_N4 ; 9 ; Output enable ; no ; -- ; -- ; ; comb~3 ; LC_X4_Y1_N9 ; 9 ; Output enable ; no ; -- ; -- ;
; nRESr ; LC_X6_Y1_N3 ; 30 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK2 ; ; nRESr ; LC_X3_Y2_N8 ; 30 ; Async. clear, Sync. clear ; yes ; Global Clock ; GCLK2 ;
+------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+ +------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
@ -560,7 +559,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+-------------+---------+----------------------+------------------+ +-------+-------------+---------+----------------------+------------------+
; C25M ; PIN_64 ; 99 ; Global Clock ; GCLK3 ; ; C25M ; PIN_64 ; 99 ; Global Clock ; GCLK3 ;
; nRESr ; LC_X6_Y1_N3 ; 30 ; Global Clock ; GCLK2 ; ; nRESr ; LC_X3_Y2_N8 ; 30 ; Global Clock ; GCLK2 ;
+-------+-------------+---------+----------------------+------------------+ +-------+-------------+---------+----------------------+------------------+
@ -569,20 +568,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+ +-----------------------+--------------------+
; Routing Resource Type ; Usage ; ; Routing Resource Type ; Usage ;
+-----------------------+--------------------+ +-----------------------+--------------------+
; C4s ; 223 / 784 ( 28 % ) ; ; C4s ; 237 / 784 ( 30 % ) ;
; Direct links ; 51 / 888 ( 6 % ) ; ; Direct links ; 39 / 888 ( 4 % ) ;
; Global clocks ; 2 / 4 ( 50 % ) ; ; Global clocks ; 2 / 4 ( 50 % ) ;
; LAB clocks ; 8 / 32 ( 25 % ) ; ; LAB clocks ; 10 / 32 ( 31 % ) ;
; LUT chains ; 27 / 216 ( 13 % ) ; ; LUT chains ; 26 / 216 ( 12 % ) ;
; Local interconnects ; 392 / 888 ( 44 % ) ; ; Local interconnects ; 416 / 888 ( 47 % ) ;
; R4s ; 197 / 704 ( 28 % ) ; ; R4s ; 228 / 704 ( 32 % ) ;
+-----------------------+--------------------+ +-----------------------+--------------------+
+---------------------------------------------------------------------------+ +---------------------------------------------------------------------------+
; LAB Logic Elements ; ; LAB Logic Elements ;
+--------------------------------------------+------------------------------+ +--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 9.57) ; Number of LABs (Total = 23) ; ; Number of Logic Elements (Average = 9.71) ; Number of LABs (Total = 24) ;
+--------------------------------------------+------------------------------+ +--------------------------------------------+------------------------------+
; 1 ; 0 ; ; 1 ; 0 ;
; 2 ; 0 ; ; 2 ; 0 ;
@ -590,9 +589,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 4 ; 0 ; ; 4 ; 0 ;
; 5 ; 0 ; ; 5 ; 0 ;
; 6 ; 0 ; ; 6 ; 0 ;
; 7 ; 1 ; ; 7 ; 0 ;
; 8 ; 3 ; ; 8 ; 1 ;
; 9 ; 1 ; ; 9 ; 5 ;
; 10 ; 18 ; ; 10 ; 18 ;
+--------------------------------------------+------------------------------+ +--------------------------------------------+------------------------------+
@ -600,21 +599,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------------------------------------------+ +-------------------------------------------------------------------+
; LAB-wide Signals ; ; LAB-wide Signals ;
+------------------------------------+------------------------------+ +------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.74) ; Number of LABs (Total = 23) ; ; LAB-wide Signals (Average = 1.96) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+ +------------------------------------+------------------------------+
; 1 Async. clear ; 5 ; ; 1 Async. clear ; 7 ;
; 1 Clock ; 21 ; ; 1 Clock ; 22 ;
; 1 Clock enable ; 4 ; ; 1 Clock enable ; 6 ;
; 1 Sync. clear ; 5 ; ; 1 Sync. clear ; 7 ;
; 1 Sync. load ; 4 ; ; 1 Sync. load ; 5 ;
; 2 Clocks ; 1 ;
+------------------------------------+------------------------------+ +------------------------------------+------------------------------+
+----------------------------------------------------------------------------+ +----------------------------------------------------------------------------+
; LAB Signals Sourced ; ; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+ +---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 9.78) ; Number of LABs (Total = 23) ; ; Number of Signals Sourced (Average = 9.83) ; Number of LABs (Total = 24) ;
+---------------------------------------------+------------------------------+ +---------------------------------------------+------------------------------+
; 0 ; 0 ; ; 0 ; 0 ;
; 1 ; 0 ; ; 1 ; 0 ;
@ -623,11 +621,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 4 ; 0 ; ; 4 ; 0 ;
; 5 ; 0 ; ; 5 ; 0 ;
; 6 ; 0 ; ; 6 ; 0 ;
; 7 ; 1 ; ; 7 ; 0 ;
; 8 ; 2 ; ; 8 ; 1 ;
; 9 ; 2 ; ; 9 ; 5 ;
; 10 ; 15 ; ; 10 ; 16 ;
; 11 ; 2 ; ; 11 ; 1 ;
; 12 ; 1 ; ; 12 ; 1 ;
+---------------------------------------------+------------------------------+ +---------------------------------------------+------------------------------+
@ -635,18 +633,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ; ; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+ +-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 23) ; ; Number of Signals Sourced Out (Average = 6.67) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+ +-------------------------------------------------+------------------------------+
; 0 ; 0 ; ; 0 ; 0 ;
; 1 ; 0 ; ; 1 ; 0 ;
; 2 ; 1 ; ; 2 ; 0 ;
; 3 ; 2 ; ; 3 ; 3 ;
; 4 ; 2 ; ; 4 ; 0 ;
; 5 ; 2 ; ; 5 ; 5 ;
; 6 ; 1 ; ; 6 ; 4 ;
; 7 ; 3 ; ; 7 ; 3 ;
; 8 ; 3 ; ; 8 ; 3 ;
; 9 ; 6 ; ; 9 ; 3 ;
; 10 ; 3 ; ; 10 ; 3 ;
+-------------------------------------------------+------------------------------+ +-------------------------------------------------+------------------------------+
@ -654,35 +652,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------------------------------------------------------+ +-----------------------------------------------------------------------------+
; LAB Distinct Inputs ; ; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+ +----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 14.87) ; Number of LABs (Total = 23) ; ; Number of Distinct Inputs (Average = 15.46) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+ +----------------------------------------------+------------------------------+
; 0 ; 0 ; ; 0 ; 0 ;
; 1 ; 0 ; ; 1 ; 0 ;
; 2 ; 0 ; ; 2 ; 0 ;
; 3 ; 0 ; ; 3 ; 0 ;
; 4 ; 1 ; ; 4 ; 0 ;
; 5 ; 0 ; ; 5 ; 1 ;
; 6 ; 1 ; ; 6 ; 1 ;
; 7 ; 1 ; ; 7 ; 0 ;
; 8 ; 0 ; ; 8 ; 0 ;
; 9 ; 0 ; ; 9 ; 0 ;
; 10 ; 2 ; ; 10 ; 0 ;
; 11 ; 0 ; ; 11 ; 0 ;
; 12 ; 2 ; ; 12 ; 1 ;
; 13 ; 3 ; ; 13 ; 4 ;
; 14 ; 1 ; ; 14 ; 2 ;
; 15 ; 2 ; ; 15 ; 3 ;
; 16 ; 1 ; ; 16 ; 6 ;
; 17 ; 2 ; ; 17 ; 0 ;
; 18 ; 1 ; ; 18 ; 1 ;
; 19 ; 1 ; ; 19 ; 0 ;
; 20 ; 2 ; ; 20 ; 1 ;
; 21 ; 0 ; ; 21 ; 2 ;
; 22 ; 1 ; ; 22 ; 0 ;
; 23 ; 1 ; ; 23 ; 1 ;
; 24 ; 0 ; ; 24 ; 1 ;
; 25 ; 0 ;
; 26 ; 1 ;
+----------------------------------------------+------------------------------+ +----------------------------------------------+------------------------------+
@ -726,7 +722,7 @@ Info (332111): Found 2 clocks
Info (186079): Completed User Assigned Global Signals Promotion Operation Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9 Info (186215): Automatically promoted signal "C25M" to use Global clock in PIN 64 File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 9
Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 14 Info (186216): Automatically promoted some destinations of signal "nRESr" to use Global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 14
Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 69 Info (186217): Destination "IOROMEN" may be non-global or may not use global clock File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 71
Info (186079): Completed Auto Global Promotion Operation Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing Info (176234): Starting register packing
Info (186468): Started processing fast register assignments Info (186468): Started processing fast register assignments
@ -740,16 +736,16 @@ Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 30% of the available device resources Info (170195): Router estimated average interconnect usage is 32% of the available device resources
Info (170196): Router estimated peak interconnect usage is 30% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170196): Router estimated peak interconnect usage is 32% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.27 seconds. Info (11888): Total time spent on timing analysis during the Fitter is 0.29 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 13732 megabytes Info: Peak virtual memory: 13732 megabytes
Info: Processing ended: Fri Apr 14 00:01:38 2023 Info: Processing ended: Fri Apr 14 01:52:15 2023
Info: Elapsed time: 00:00:03 Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:04 Info: Total CPU time (on all processors): 00:00:04

4
cpld/output_files/GR8RAM.fit.summary
View File

@ -1,11 +1,11 @@
Fitter Status : Successful - Fri Apr 14 00:01:38 2023 Fitter Status : Successful - Fri Apr 14 01:52:15 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Device : EPM240T100C5 Device : EPM240T100C5
Timing Models : Final Timing Models : Final
Total logic elements : 220 / 240 ( 92 % ) Total logic elements : 233 / 240 ( 97 % )
Total pins : 80 / 80 ( 100 % ) Total pins : 80 / 80 ( 100 % )
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % ) UFM blocks : 0 / 1 ( 0 % )

16
cpld/output_files/GR8RAM.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for GR8RAM Flow report for GR8RAM
Fri Apr 14 00:01:43 2023 Fri Apr 14 01:52:20 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -41,14 +41,14 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+ +---------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+-----------------------+---------------------------------------------+ +-----------------------+---------------------------------------------+
; Flow Status ; Successful - Fri Apr 14 00:01:40 2023 ; ; Flow Status ; Successful - Fri Apr 14 01:52:17 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Device ; EPM240T100C5 ; ; Device ; EPM240T100C5 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 220 / 240 ( 92 % ) ; ; Total logic elements ; 233 / 240 ( 97 % ) ;
; Total pins ; 80 / 80 ( 100 % ) ; ; Total pins ; 80 / 80 ( 100 % ) ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 04/14/2023 00:01:17 ; ; Start date & time ; 04/14/2023 01:51:54 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
+-------------------+---------------------+ +-------------------+---------------------+
@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; ; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; AUTO_PACKED_REGISTERS_MAX ; Minimize Area ; Auto ; -- ; -- ; ; AUTO_PACKED_REGISTERS_MAX ; Minimize Area ; Auto ; -- ; -- ;
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ; ; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 121381084694.168144487708968 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 121381084694.168145151401644 ; -- ; -- ; -- ;
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ; ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ; ; IOBANK_VCCIO ; -- (Not supported for targeted family) ; -- ; -- ; 1 ;
@ -103,11 +103,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:18 ; 1.0 ; 13092 MB ; 00:00:39 ; ; Analysis & Synthesis ; 00:00:17 ; 1.0 ; 13092 MB ; 00:00:39 ;
; Fitter ; 00:00:03 ; 1.0 ; 13732 MB ; 00:00:04 ; ; Fitter ; 00:00:03 ; 1.0 ; 13732 MB ; 00:00:04 ;
; Assembler ; 00:00:01 ; 1.0 ; 13052 MB ; 00:00:01 ; ; Assembler ; 00:00:01 ; 1.0 ; 13052 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13051 MB ; 00:00:01 ; ; Timing Analyzer ; 00:00:02 ; 1.0 ; 13053 MB ; 00:00:01 ;
; Total ; 00:00:24 ; -- ; -- ; 00:00:45 ; ; Total ; 00:00:23 ; -- ; -- ; 00:00:45 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+

74
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM Analysis & Synthesis report for GR8RAM
Fri Apr 14 00:01:34 2023 Fri Apr 14 01:52:11 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+ +---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+ +-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Apr 14 00:01:34 2023 ; ; Analysis & Synthesis Status ; Successful - Fri Apr 14 01:52:11 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; GR8RAM ; ; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ; ; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ; ; Family ; MAX II ;
; Total logic elements ; 225 ; ; Total logic elements ; 236 ;
; Total pins ; 80 ; ; Total pins ; 80 ;
; Total virtual pins ; 0 ; ; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ; ; UFM blocks ; 0 / 1 ( 0 % ) ;
@ -159,20 +159,20 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Resource ; Usage ; ; Resource ; Usage ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
; Total logic elements ; 225 ; ; Total logic elements ; 236 ;
; -- Combinational with no register ; 125 ; ; -- Combinational with no register ; 136 ;
; -- Register only ; 6 ; ; -- Register only ; 4 ;
; -- Combinational with a register ; 94 ; ; -- Combinational with a register ; 96 ;
; ; ; ; ; ;
; Logic element usage by number of LUT inputs ; ; ; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 120 ; ; -- 4 input functions ; 128 ;
; -- 3 input functions ; 32 ; ; -- 3 input functions ; 37 ;
; -- 2 input functions ; 66 ; ; -- 2 input functions ; 66 ;
; -- 1 input functions ; 1 ; ; -- 1 input functions ; 1 ;
; -- 0 input functions ; 0 ; ; -- 0 input functions ; 0 ;
; ; ; ; ; ;
; Logic elements by mode ; ; ; Logic elements by mode ; ;
; -- normal mode ; 192 ; ; -- normal mode ; 203 ;
; -- arithmetic mode ; 33 ; ; -- arithmetic mode ; 33 ;
; -- qfbk mode ; 0 ; ; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ; ; -- register cascade mode ; 0 ;
@ -184,8 +184,8 @@ https://fpgasoftware.intel.com/eula.
; I/O pins ; 80 ; ; I/O pins ; 80 ;
; Maximum fan-out node ; C25M ; ; Maximum fan-out node ; C25M ;
; Maximum fan-out ; 99 ; ; Maximum fan-out ; 99 ;
; Total fan-out ; 1009 ; ; Total fan-out ; 1052 ;
; Average fan-out ; 3.31 ; ; Average fan-out ; 3.33 ;
+---------------------------------------------+-------+ +---------------------------------------------+-------+
@ -194,7 +194,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
; |GR8RAM ; 225 (225) ; 100 ; 0 ; 80 ; 0 ; 125 (125) ; 6 (6) ; 94 (94) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ; ; |GR8RAM ; 236 (236) ; 100 ; 0 ; 80 ; 0 ; 136 (136) ; 4 (4) ; 96 (96) ; 37 (37) ; 0 (0) ; |GR8RAM ; GR8RAM ; work ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+ +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -251,7 +251,8 @@ Encoding Type: Minimal Bits
; DQML~reg0 ; 1 ; ; DQML~reg0 ; 1 ;
; DQMH~reg0 ; 1 ; ; DQMH~reg0 ; 1 ;
; RCKE~reg0 ; 4 ; ; RCKE~reg0 ; 4 ;
; Total number of inverted registers = 7 ; ; ; nFCS~reg0 ; 1 ;
; Total number of inverted registers = 8 ; ;
+----------------------------------------+---------+ +----------------------------------------+---------+
@ -260,14 +261,14 @@ Encoding Type: Minimal Bits
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[1] ; ; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |GR8RAM|PS[2] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ; ; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; Yes ; |GR8RAM|SA[11]~reg0 ;
; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[6]~reg0 ; ; 20:1 ; 6 bits ; 78 LEs ; 24 LEs ; 54 LEs ; Yes ; |GR8RAM|SA[6]~reg0 ;
; 20:1 ; 3 bits ; 39 LEs ; 18 LEs ; 21 LEs ; Yes ; |GR8RAM|SA[2]~reg0 ; ; 20:1 ; 2 bits ; 26 LEs ; 12 LEs ; 14 LEs ; Yes ; |GR8RAM|SA[1]~reg0 ;
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[5] ; ; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |GR8RAM|WRD[4] ;
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |GR8RAM|RDD[2] ; ; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |GR8RAM|RDD[2] ;
; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQML~reg0 ; ; 18:1 ; 2 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |GR8RAM|DQMH~reg0 ;
; 18:1 ; 4 bits ; 48 LEs ; 8 LEs ; 40 LEs ; Yes ; |GR8RAM|RDD[6] ; ; 18:1 ; 3 bits ; 36 LEs ; 6 LEs ; 30 LEs ; Yes ; |GR8RAM|RDD[4] ;
; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ; ; 7:1 ; 5 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |GR8RAM|IS ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
@ -278,38 +279,41 @@ Encoding Type: Minimal Bits
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Fri Apr 14 00:01:16 2023 Info: Processing started: Fri Apr 14 01:51:54 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Warning (10229): Verilog HDL Expression warning at GR8RAM.v(22): truncated literal to match 1 bits File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 22
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 1 Info (12023): Found entity 1: GR8RAM File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 1
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 31 Warning (10230): Verilog HDL assignment warning at GR8RAM.v(31): truncated value with size 32 to match size of target (4) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 31
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 36 Warning (10230): Verilog HDL assignment warning at GR8RAM.v(36): truncated value with size 32 to match size of target (14) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 36
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(109): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 109 Warning (10230): Verilog HDL assignment warning at GR8RAM.v(111): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 111
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(117): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 117 Warning (10230): Verilog HDL assignment warning at GR8RAM.v(119): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 119
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(124): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 124 Warning (10230): Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (8) File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 126
Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "area" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
Warning (13024): Output pins are stuck at VCC or GND Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "nNMIout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 541 Warning (13410): Pin "nNMIout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 553
Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 544 Warning (13410): Pin "nIRQout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 556
Warning (13410): Pin "nRDYout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 543 Warning (13410): Pin "nRDYout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 555
Warning (13410): Pin "nINHout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 542 Warning (13410): Pin "nINHout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 554
Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 545 Warning (13410): Pin "RWout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 557
Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 540 Warning (13410): Pin "nDMAout" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 552
Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 539 Warning (13410): Pin "RAdir" is stuck at VCC File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 551
Info (17049): 1 registers lost all their fanouts during netlist optimizations. Info (17049): 1 registers lost all their fanouts during netlist optimizations.
Info (21057): Implemented 305 device resources after synthesis - the final resource count might be different Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "RA[11]" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 56
Info (21057): Implemented 316 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 28 input pins Info (21058): Implemented 28 input pins
Info (21059): Implemented 35 output pins Info (21059): Implemented 35 output pins
Info (21060): Implemented 17 bidirectional pins Info (21060): Implemented 17 bidirectional pins
Info (21061): Implemented 225 logic cells Info (21061): Implemented 236 logic cells
Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg Info (144001): Generated suppressed messages file Y:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 14 warnings Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 17 warnings
Info: Peak virtual memory: 13092 megabytes Info: Peak virtual memory: 13092 megabytes
Info: Processing ended: Fri Apr 14 00:01:34 2023 Info: Processing ended: Fri Apr 14 01:52:11 2023
Info: Elapsed time: 00:00:18 Info: Elapsed time: 00:00:17
Info: Total CPU time (on all processors): 00:00:39 Info: Total CPU time (on all processors): 00:00:39

4
cpld/output_files/GR8RAM.map.smsg
View File

@ -1,2 +1,2 @@
Warning (10273): Verilog HDL warning at GR8RAM.v(85): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 85 Warning (10273): Verilog HDL warning at GR8RAM.v(87): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 87
Warning (10273): Verilog HDL warning at GR8RAM.v(261): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 261 Warning (10273): Verilog HDL warning at GR8RAM.v(269): extended using "x" or "z" File: Y:/Repos/GR8RAM/cpld/GR8RAM.v Line: 269

4
cpld/output_files/GR8RAM.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Fri Apr 14 00:01:34 2023 Analysis & Synthesis Status : Successful - Fri Apr 14 01:52:11 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : GR8RAM Revision Name : GR8RAM
Top-level Entity Name : GR8RAM Top-level Entity Name : GR8RAM
Family : MAX II Family : MAX II
Total logic elements : 225 Total logic elements : 236
Total pins : 80 Total pins : 80
Total virtual pins : 0 Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % ) UFM blocks : 0 / 1 ( 0 % )

BIN
cpld/output_files/GR8RAM.pof
View File

Binary file not shown.

528
cpld/output_files/GR8RAM.sta.rpt
View File

@ -1,5 +1,5 @@
Timing Analyzer report for GR8RAM Timing Analyzer report for GR8RAM
Fri Apr 14 00:01:43 2023 Fri Apr 14 01:52:20 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -93,7 +93,7 @@ https://fpgasoftware.intel.com/eula.
+---------------+--------+--------------------------+ +---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ; ; SDC File Path ; Status ; Read at ;
+---------------+--------+--------------------------+ +---------------+--------+--------------------------+
; GR8RAM.sdc ; OK ; Fri Apr 14 00:01:43 2023 ; ; GR8RAM.sdc ; OK ; Fri Apr 14 01:52:19 2023 ;
+---------------+--------+--------------------------+ +---------------+--------+--------------------------+
@ -112,7 +112,7 @@ https://fpgasoftware.intel.com/eula.
+-----------+-----------------+------------+------+ +-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ; ; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+ +-----------+-----------------+------------+------+
; 86.99 MHz ; 86.99 MHz ; C25M ; ; ; 73.38 MHz ; 73.38 MHz ; C25M ; ;
+-----------+-----------------+------------+------+ +-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -122,7 +122,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+--------+---------------+ +-------+--------+---------------+
; Clock ; Slack ; End Point TNS ; ; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+ +-------+--------+---------------+
; C25M ; 14.252 ; 0.000 ; ; C25M ; 13.632 ; 0.000 ;
+-------+--------+---------------+ +-------+--------+---------------+
@ -131,7 +131,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-------+---------------+ +-------+-------+---------------+
; Clock ; Slack ; End Point TNS ; ; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+ +-------+-------+---------------+
; C25M ; 1.394 ; 0.000 ; ; C25M ; 1.404 ; 0.000 ;
+-------+-------+---------------+ +-------+-------+---------------+
@ -140,7 +140,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+--------+---------------+ +-------+--------+---------------+
; Clock ; Slack ; End Point TNS ; ; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+ +-------+--------+---------------+
; C25M ; 33.179 ; 0.000 ; ; C25M ; 33.394 ; 0.000 ;
+-------+--------+---------------+ +-------+--------+---------------+
@ -149,7 +149,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-------+---------------+ +-------+-------+---------------+
; Clock ; Slack ; End Point TNS ; ; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+ +-------+-------+---------------+
; C25M ; 6.267 ; 0.000 ; ; C25M ; 6.052 ; 0.000 ;
+-------+-------+---------------+ +-------+-------+---------------+
@ -168,106 +168,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
; 14.252 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.415 ; ; 13.632 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.035 ;
; 14.252 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.415 ; ; 13.741 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.926 ;
; 14.252 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.415 ; ; 13.741 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.926 ;
; 14.272 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.395 ; ; 13.741 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.926 ;
; 14.272 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.395 ; ; 13.857 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.810 ;
; 14.272 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.395 ; ; 13.907 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.760 ;
; 14.313 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.354 ; ; 13.966 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.701 ;
; 14.640 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.027 ; ; 13.966 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.701 ;
; 14.640 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.027 ; ; 13.966 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.701 ;
; 14.640 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.027 ; ; 14.016 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.651 ;
; 14.716 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ; ; 14.016 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.651 ;
; 14.716 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ; ; 14.016 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.651 ;
; 14.716 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ; ; 14.028 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.639 ;
; 14.716 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ; ; 14.032 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.635 ;
; 14.716 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.951 ; ; 14.137 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.530 ;
; 14.718 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.949 ; ; 14.137 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.530 ;
; 14.736 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ; ; 14.137 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.530 ;
; 14.736 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ; ; 14.234 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.433 ;
; 14.736 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ; ; 14.241 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.426 ;
; 14.736 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ; ; 14.265 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.402 ;
; 14.736 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.931 ; ; 14.388 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.279 ;
; 14.746 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.921 ; ; 14.388 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.279 ;
; 14.746 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.921 ; ; 14.388 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.279 ;
; 14.746 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.921 ; ; 14.388 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.279 ;
; 14.758 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.909 ; ; 14.430 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.237 ;
; 14.841 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.826 ; ; 14.497 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.170 ;
; 14.881 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.786 ; ; 14.594 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.073 ;
; 14.993 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.674 ; ; 14.613 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.054 ;
; 15.104 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ; ; 14.613 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.054 ;
; 15.104 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ; ; 14.613 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.054 ;
; 15.104 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ; ; 14.613 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.054 ;
; 15.104 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ; ; 14.663 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.004 ;
; 15.104 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.563 ; ; 14.663 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.004 ;
; 15.210 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ; ; 14.663 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.004 ;
; 15.210 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ; ; 14.663 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.004 ;
; 15.210 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ; ; 14.784 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.883 ;
; 15.210 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ; ; 14.784 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.883 ;
; 15.210 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.457 ; ; 14.784 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.883 ;
; 15.303 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.364 ; ; 14.784 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.883 ;
; 15.404 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.263 ; ; 15.031 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.636 ;
; 15.629 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.038 ; ; 15.061 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.606 ;
; 15.669 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.998 ; ; 15.151 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.516 ;
; 15.686 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.981 ; ; 15.285 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.382 ;
; 15.695 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.972 ; ; 15.309 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.358 ;
; 15.762 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.905 ; ; 15.415 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.252 ;
; 15.840 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.827 ; ; 15.445 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.222 ;
; 15.967 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.700 ; ; 15.454 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.213 ;
; 16.041 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.626 ; ; 15.533 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.134 ;
; 16.139 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.528 ; ; 15.625 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.042 ;
; 16.203 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.464 ; ; 15.761 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.906 ;
; 16.253 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.414 ; ; 15.775 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.892 ;
; 16.354 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.313 ; ; 15.779 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.888 ;
; 16.389 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.278 ; ; 15.879 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.788 ;
; 16.467 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.200 ; ; 15.981 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.686 ;
; 16.527 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.140 ; ; 16.027 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.640 ;
; 16.563 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.104 ; ; 16.325 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.342 ;
; 28.556 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.111 ; ; 26.372 ; PS[3] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.295 ;
; 28.715 ; LS[9] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.952 ; ; 26.645 ; PS[3] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.022 ;
; 28.895 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.772 ; ; 26.748 ; PS[3] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.919 ;
; 28.900 ; LS[10] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.767 ; ; 27.318 ; PS[3] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.349 ;
; 29.059 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.608 ; ; 27.398 ; PS[3] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.269 ;
; 29.239 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.428 ; ; 27.575 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 12.092 ;
; 29.252 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.415 ; ; 27.762 ; PS[3] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.905 ;
; 29.535 ; PS[3] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.132 ; ; 27.848 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.819 ;
; 29.596 ; LS[8] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.071 ; ; 27.951 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.716 ;
; 29.602 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.065 ; ; 27.965 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.702 ;
; 29.687 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.980 ; ; 28.136 ; PS[0] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.531 ;
; 29.698 ; IS.state_bit_1 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.969 ; ; 28.136 ; PS[0] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.531 ;
; 29.729 ; LS[7] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.938 ; ; 28.136 ; PS[0] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.531 ;
; 29.734 ; LS[3] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.933 ; ; 28.136 ; PS[0] ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.531 ;
; 29.770 ; PS[1] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.897 ; ; 28.136 ; PS[0] ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.531 ;
; 29.811 ; PS[3] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.856 ; ; 28.136 ; PS[0] ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.531 ;
; 29.837 ; PS[1] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ; ; 28.136 ; PS[0] ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.531 ;
; 29.837 ; PS[1] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ; ; 28.136 ; PS[0] ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.531 ;
; 29.837 ; PS[1] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ; ; 28.177 ; PS[0] ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.490 ;
; 29.837 ; PS[1] ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ; ; 28.177 ; PS[0] ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.490 ;
; 29.837 ; PS[1] ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ; ; 28.177 ; PS[0] ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.490 ;
; 29.837 ; PS[1] ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ; ; 28.177 ; PS[0] ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.490 ;
; 29.837 ; PS[1] ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ; ; 28.177 ; PS[0] ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.490 ;
; 29.837 ; PS[1] ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.830 ; ; 28.177 ; PS[0] ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.490 ;
; 29.841 ; PS[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.826 ; ; 28.177 ; PS[0] ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.490 ;
; 29.878 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.789 ; ; 28.177 ; PS[0] ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 11.490 ;
; 29.892 ; PS[0] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.775 ; ; 28.238 ; IS.state_bit_0 ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.429 ;
; 29.926 ; LS[6] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.741 ; ; 28.341 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.326 ;
; 29.942 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.725 ; ; 28.521 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.146 ;
; 30.003 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.664 ; ; 28.553 ; LS[6] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.114 ;
; 30.027 ; PS[3] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.640 ; ; 28.601 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.066 ;
; 30.030 ; PS[3] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.637 ; ; 28.633 ; LS[3] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.034 ;
; 30.058 ; LS[12] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.609 ; ; 28.770 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.897 ;
; 30.073 ; LS[7] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.594 ; ; 28.895 ; LS[6] ; IS.state_bit_2 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.772 ;
; 30.078 ; LS[3] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.589 ; ; 28.911 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.756 ;
; 30.094 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.573 ; ; 28.975 ; LS[3] ; IS.state_bit_2 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.692 ;
; 30.097 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.570 ; ; 28.991 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.676 ;
; 30.099 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.568 ; ; 29.031 ; IS.state_bit_1 ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.636 ;
; 30.100 ; LS[1] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.567 ; ; 29.044 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.623 ;
; 30.101 ; LS[9] ; IS.state_bit_2 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.566 ; ; 29.102 ; PS[1] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.565 ;
; 30.102 ; PS[0] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.565 ; ; 29.114 ; PS[3] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.553 ;
; 30.168 ; PS[0] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.499 ; ; 29.152 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.515 ;
; 30.226 ; PS[3] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.441 ; ; 29.158 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.509 ;
; 30.249 ; PS[1] ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.418 ; ; 29.160 ; IS.state_bit_0 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.507 ;
+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+ +--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
@ -276,106 +276,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
; 1.394 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.615 ; ; 1.404 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.625 ;
; 1.403 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.624 ; ; 1.412 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ;
; 1.410 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.631 ; ; 1.419 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.640 ;
; 1.411 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.632 ; ; 1.420 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ;
; 1.420 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ; ; 1.646 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.867 ;
; 1.640 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.861 ; ; 1.650 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.871 ;
; 1.695 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 1.916 ; ; 1.674 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.895 ;
; 1.815 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.036 ; ; 1.678 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.899 ;
; 1.835 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.056 ; ; 1.698 ; RCKE~reg0 ; SDOE ; C25M ; C25M ; 0.000 ; 0.000 ; 1.919 ;
; 1.927 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.148 ; ; 1.799 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.020 ;
; 1.937 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.158 ; ; 1.806 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.027 ;
; 1.941 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.162 ; ; 1.831 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.052 ;
; 1.972 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.193 ; ; 1.836 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.057 ;
; 2.076 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.297 ; ; 1.916 ; IS.state_bit_1 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.137 ;
; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ; ; 1.929 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.150 ;
; 1.951 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.172 ;
; 1.967 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.188 ;
; 1.968 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.189 ;
; 1.972 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.193 ;
; 1.986 ; PS[0] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.207 ;
; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ;
; 2.107 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ;
; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.120 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.341 ; ; 2.118 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.339 ;
; 2.122 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.343 ; ; 2.124 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.345 ;
; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; ; 2.125 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ; ; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; ; 2.126 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; ; 2.127 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; ; 2.134 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.355 ;
; 2.126 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ; ; 2.137 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ;
; 2.127 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ; ; 2.137 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ;
; 2.136 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.357 ; ; 2.139 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.360 ;
; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; ; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
; 2.144 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; ; 2.150 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.371 ;
; 2.144 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ; ; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ;
; 2.147 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.368 ; ; 2.212 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.433 ;
; 2.153 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ; ; 2.225 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.446 ;
; 2.170 ; REGEN ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 2.391 ;
; 2.222 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.443 ;
; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ; ; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
; 2.231 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.230 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.234 ; RCKE~reg0 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.455 ; ; 2.231 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.241 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; ; 2.231 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.231 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.231 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
; 2.232 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.241 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ; ; 2.241 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
; 2.246 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.467 ;
; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ; ; 2.248 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ;
; 2.249 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.249 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; ; 2.249 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.249 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ; ; 2.252 ; PHI0r2 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ;
; 2.250 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; ; 2.252 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ;
; 2.250 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; ; 2.255 ; IS.state_bit_2 ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 2.476 ;
; 2.250 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; ; 2.255 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.476 ;
; 2.250 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ; ; 2.259 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ;
; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ; ; 2.260 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
; 2.251 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
; 2.253 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.474 ;
; 2.254 ; PHI0r2 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.475 ;
; 2.254 ; Addr[19] ; SA[9]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.475 ;
; 2.261 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.261 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; ; 2.261 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.261 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ; ; 2.261 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.262 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ; ; 2.264 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ;
; 2.428 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.649 ; ; 2.267 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.488 ;
; 2.500 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 2.721 ; ; 2.273 ; RCKE~reg0 ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.494 ;
; 2.548 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.769 ; ; 2.273 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.494 ;
; 2.558 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.779 ; ; 2.293 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.514 ;
; 2.569 ; IS.state_bit_0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.790 ; ; 2.425 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.646 ;
; 2.574 ; IS.state_bit_0 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 2.795 ; ; 2.495 ; IS.state_bit_1 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.716 ;
; 2.584 ; IS.state_bit_0 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.805 ; ; 2.559 ; PS[3] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.780 ;
; 2.622 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.843 ; ; 2.627 ; PS[2] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.848 ;
; 2.702 ; IS.state_bit_1 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.923 ; ; 2.636 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.857 ;
; 2.717 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.938 ; ; 2.676 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.897 ;
; 2.718 ; IS.state_bit_1 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 2.939 ; ; 2.838 ; PS[2] ; nSWE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.059 ;
; 2.719 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.940 ; ; 2.842 ; PS[2] ; SA[0]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.063 ;
; 2.721 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.942 ; ; 2.842 ; PS[2] ; SA[1]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.063 ;
; 2.782 ; IS.state_bit_0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.003 ; ; 2.847 ; IS.state_bit_0 ; FCKout ; C25M ; C25M ; 0.000 ; 0.000 ; 3.068 ;
; 2.849 ; IS.state_bit_2 ; IS.state_bit_2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.070 ; ; 2.886 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.107 ;
; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ; ; 2.933 ; IS.state_bit_2 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.154 ;
; 2.937 ; IS.state_bit_2 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.158 ;
; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ; ; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.954 ; PS[2] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.175 ; ; 2.955 ; IS.state_bit_0 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.176 ;
; 2.955 ; IS.state_bit_2 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 3.176 ; ; 2.956 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ;
; 2.956 ; PS[1] ; nRAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.177 ;
; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; ; 2.957 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; ; 2.958 ; IS.state_bit_0 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
; 2.957 ; IS.state_bit_2 ; FCS ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ; ; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
; 2.958 ; PS[1] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; ; 2.958 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
; 2.958 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ; ; 2.966 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.187 ;
; 2.959 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ; ; 2.971 ; IS.state_bit_2 ; IS.state_bit_2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.192 ;
; 2.976 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; ; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
; 2.976 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ; ; 2.982 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.203 ;
; 2.985 ; PS[1] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ; ; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ;
; 3.037 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.258 ;
; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ;
; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
; 3.060 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
; 3.060 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
; 3.060 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ; ; 3.060 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
; 3.067 ; Addr[8] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.288 ;
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+ +-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
@ -384,35 +384,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+ +--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+ +--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; 33.179 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
; 33.179 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.488 ; ; 33.394 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.273 ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+ +--------+-----------+----------+--------------+-------------+--------------+------------+------------+
@ -421,35 +421,35 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+ +-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+ +-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; 6.267 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
; 6.267 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.488 ; ; 6.052 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.273 ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+ +-------+-----------+----------+--------------+-------------+--------------+------------+------------+
@ -458,7 +458,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------+----------+------------+------------+----------+----------+ +------------+----------+------------+------------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+------------+----------+----------+ +------------+----------+------------+------------+----------+----------+
; C25M ; C25M ; 1285 ; 0 ; 56 ; 0 ; ; C25M ; C25M ; 1291 ; 0 ; 56 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ; ; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ;
+------------+----------+------------+------------+----------+----------+ +------------+----------+------------+------------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -469,7 +469,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------+----------+------------+------------+----------+----------+ +------------+----------+------------+------------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+------------+----------+----------+ +------------+----------+------------+------------+----------+----------+
; C25M ; C25M ; 1285 ; 0 ; 56 ; 0 ; ; C25M ; C25M ; 1291 ; 0 ; 56 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ; ; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ;
+------------+----------+------------+------------+----------+----------+ +------------+----------+------------+------------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -514,10 +514,10 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+---------------------------------+-------+------+ +---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ; ; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 44 ; 44 ; ; Unconstrained Input Ports ; 43 ; 43 ;
; Unconstrained Input Port Paths ; 390 ; 390 ; ; Unconstrained Input Port Paths ; 407 ; 407 ;
; Unconstrained Output Ports ; 45 ; 45 ; ; Unconstrained Output Ports ; 45 ; 45 ;
; Unconstrained Output Port Paths ; 136 ; 136 ; ; Unconstrained Output Port Paths ; 152 ; 152 ;
+---------------------------------+-------+------+ +---------------------------------+-------+------+
@ -552,7 +552,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
@ -657,7 +656,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
@ -747,7 +745,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Fri Apr 14 00:01:41 2023 Info: Processing started: Fri Apr 14 01:52:18 2023
Info: Command: quartus_sta GR8RAM -c GR8RAM Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1 Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@ -759,22 +757,22 @@ Info (334004): Delay annotation completed successfully
Info (332104): Reading SDC File: 'GR8RAM.sdc' Info (332104): Reading SDC File: 'GR8RAM.sdc'
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Info (332146): Worst-case setup slack is 14.252 Info (332146): Worst-case setup slack is 13.632
Info (332119): Slack End Point TNS Clock Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== ===================== Info (332119): ========= =================== =====================
Info (332119): 14.252 0.000 C25M Info (332119): 13.632 0.000 C25M
Info (332146): Worst-case hold slack is 1.394 Info (332146): Worst-case hold slack is 1.404
Info (332119): Slack End Point TNS Clock Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== ===================== Info (332119): ========= =================== =====================
Info (332119): 1.394 0.000 C25M Info (332119): 1.404 0.000 C25M
Info (332146): Worst-case recovery slack is 33.179 Info (332146): Worst-case recovery slack is 33.394
Info (332119): Slack End Point TNS Clock Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== ===================== Info (332119): ========= =================== =====================
Info (332119): 33.179 0.000 C25M Info (332119): 33.394 0.000 C25M
Info (332146): Worst-case removal slack is 6.267 Info (332146): Worst-case removal slack is 6.052
Info (332119): Slack End Point TNS Clock Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== ===================== Info (332119): ========= =================== =====================
Info (332119): 6.267 0.000 C25M Info (332119): 6.052 0.000 C25M
Info (332146): Worst-case minimum pulse width slack is 19.734 Info (332146): Worst-case minimum pulse width slack is 19.734
Info (332119): Slack End Point TNS Clock Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== ===================== Info (332119): ========= =================== =====================
@ -784,8 +782,8 @@ Info (332001): The selected device family is not supported by the report_metasta
Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13051 megabytes Info: Peak virtual memory: 13053 megabytes
Info: Processing ended: Fri Apr 14 00:01:43 2023 Info: Processing ended: Fri Apr 14 01:52:20 2023
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:01

8
cpld/output_files/GR8RAM.sta.summary
View File

@ -3,19 +3,19 @@ Timing Analyzer Summary
------------------------------------------------------------ ------------------------------------------------------------
Type : Setup 'C25M' Type : Setup 'C25M'
Slack : 14.252 Slack : 13.632
TNS : 0.000 TNS : 0.000
Type : Hold 'C25M' Type : Hold 'C25M'
Slack : 1.394 Slack : 1.404
TNS : 0.000 TNS : 0.000
Type : Recovery 'C25M' Type : Recovery 'C25M'
Slack : 33.179 Slack : 33.394
TNS : 0.000 TNS : 0.000
Type : Removal 'C25M' Type : Removal 'C25M'
Slack : 6.267 Slack : 6.052
TNS : 0.000 TNS : 0.000
Type : Minimum Pulse Width 'C25M' Type : Minimum Pulse Width 'C25M'