mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-05-28 14:41:27 +00:00
24-bit counter, CAS fixed
This commit is contained in:
Zane Kaminski
parent
2382fdfda6
commit
cf16763591
|
|
@ -85,7 +85,6 @@ set_location_assignment PIN_36 -to D[0]
|
||||||
set_location_assignment PIN_39 -to nCAS0
|
set_location_assignment PIN_39 -to nCAS0
|
||||||
set_location_assignment PIN_40 -to nCAS1
|
set_location_assignment PIN_40 -to nCAS1
|
||||||
set_location_assignment PIN_41 -to nRCS
|
set_location_assignment PIN_41 -to nRCS
|
||||||
set_location_assignment PIN_44 -to MODE
|
|
||||||
set_location_assignment PIN_45 -to nROE
|
set_location_assignment PIN_45 -to nROE
|
||||||
set_location_assignment PIN_46 -to RA[9]
|
set_location_assignment PIN_46 -to RA[9]
|
||||||
set_location_assignment PIN_48 -to RA[10]
|
set_location_assignment PIN_48 -to RA[10]
|
||||||
|
|
@ -161,4 +160,5 @@ set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI0seen
|
||||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
|
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1reg
|
||||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
|
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to S
|
||||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
|
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to PHI1b0_MC
|
||||||
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to IOROMEN
|
set_instance_assignment -name MAX7000_INDIVIDUAL_TURBO_BIT ON -to IOROMEN
|
||||||
|
set_location_assignment PIN_44 -to nMode
|
||||||
BIN
cpld/GR8RAM.qws
BIN
cpld/GR8RAM.qws
Binary file not shown.
|
|
@ -54,7 +54,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
|
||||||
wire DOE = CSDBEN & nWE &
|
wire DOE = CSDBEN & nWE &
|
||||||
((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
|
((~nDEVSEL & REGEN) | ~nIOSEL | (~nIOSTRB & IOROMEN));
|
||||||
wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] :
|
wire [7:0] Dout = (nDEVSEL | RAMSELA) ? RD[7:0] :
|
||||||
AddrHSELA ? {nMode, Addr[22:16]} :
|
AddrHSELA ? {Addr[23:16]} :
|
||||||
AddrMSELA ? Addr[15:8] :
|
AddrMSELA ? Addr[15:8] :
|
||||||
AddrLSELA ? Addr[7:0] : 8'h00;
|
AddrLSELA ? Addr[7:0] : 8'h00;
|
||||||
inout [7:0] D = DOE ? Dout : 8'bZ;
|
inout [7:0] D = DOE ? Dout : 8'bZ;
|
||||||
|
|
@ -69,19 +69,20 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
|
||||||
output nROE = ~nWE; // need this for flash ROM
|
output nROE = ~nWE; // need this for flash ROM
|
||||||
output nRWE = nWE | (nDEVSEL & nIOSEL & nIOSTRB); // for ROM & DRAM
|
output nRWE = nWE | (nDEVSEL & nIOSEL & nIOSTRB); // for ROM & DRAM
|
||||||
output nRAS = ~(RASr | RASf);
|
output nRAS = ~(RASr | RASf);
|
||||||
output nCAS0 = ~(CASr | (CASf & RAMSEL & ~Addr[22])); // DRAM CAS bank 0
|
output nCAS0 = ~(CAS0r | (CASf & RAMSEL & ~Addr[22])); // DRAM CAS bank 0
|
||||||
output nCAS1 = ~(CASr | (CASf & RAMSEL & Addr[22])); // DRAM CAS bank 1
|
output nCAS1 = ~(CAS1r | (CASf & RAMSEL & Addr[22])); // DRAM CAS bank 1
|
||||||
|
|
||||||
/* 6502-accessible Registers */
|
/* 6502-accessible Registers */
|
||||||
reg [7:0] Bank = 8'h00; // Bank register for ROM access
|
reg [7:0] Bank = 8'h00; // Bank register for ROM access
|
||||||
reg [22:0] Addr = 23'h00000; // RAM address register
|
reg [23:0] Addr = 24'h00000; // RAM address register
|
||||||
|
|
||||||
/* Increment Control */
|
/* Increment Control */
|
||||||
reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
|
reg IncAddrL = 0, IncAddrM = 0, IncAddrH = 0;
|
||||||
|
|
||||||
/* CAS rising/falling edge components */
|
/* CAS rising/falling edge components */
|
||||||
// These are combined to create the CAS outputs.
|
// These are combined to create the CAS outputs.
|
||||||
reg CASr = 1'b0;
|
reg CAS0r = 1'b0;
|
||||||
|
reg CAS1r = 1'b0;
|
||||||
reg CASf = 1'b0;
|
reg CASf = 1'b0;
|
||||||
reg RASr = 1'b0;
|
reg RASr = 1'b0;
|
||||||
reg RASf = 1'b0;
|
reg RASf = 1'b0;
|
||||||
|
|
@ -119,6 +120,12 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
|
||||||
REGEN <= 1'b0;
|
REGEN <= 1'b0;
|
||||||
IOROMEN <= 1'b0;
|
IOROMEN <= 1'b0;
|
||||||
CSDBEN <= 1'b0;
|
CSDBEN <= 1'b0;
|
||||||
|
Addr <= 24'hF00000;
|
||||||
|
Bank <= 8'h00;
|
||||||
|
FullIOEN <= 1'b0;
|
||||||
|
IncAddrL <= 1'b0;
|
||||||
|
IncAddrM <= 1'b0;
|
||||||
|
IncAddrH <= 1'b0;
|
||||||
end else begin
|
end else begin
|
||||||
// Synchronize state counter to S1 when just entering PHI1
|
// Synchronize state counter to S1 when just entering PHI1
|
||||||
PHI1reg <= PHI1; // Save old PHI1
|
PHI1reg <= PHI1; // Save old PHI1
|
||||||
|
|
@ -146,18 +153,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
|
||||||
// This provides address setup time for write operations and
|
// This provides address setup time for write operations and
|
||||||
// minimizes power consumption.
|
// minimizes power consumption.
|
||||||
CSDBEN <= S==4 | S==5 | S==6 | S==7;
|
CSDBEN <= S==4 | S==5 | S==6 | S==7;
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(negedge C7M, negedge nRES) begin
|
|
||||||
if (~nRES) begin
|
|
||||||
Addr <= 23'h000000;
|
|
||||||
Bank <= 8'h00;
|
|
||||||
FullIOEN <= 1'b0;
|
|
||||||
IncAddrL <= 1'b0;
|
|
||||||
IncAddrM <= 1'b0;
|
|
||||||
IncAddrH <= 1'b0;
|
|
||||||
end else begin
|
|
||||||
// Increment address register
|
// Increment address register
|
||||||
if (S==1 & IncAddrL) begin
|
if (S==1 & IncAddrL) begin
|
||||||
Addr[7:0] <= Addr[7:0]+1;
|
Addr[7:0] <= Addr[7:0]+1;
|
||||||
|
|
@ -171,11 +167,11 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
|
||||||
end
|
end
|
||||||
if (S==3 & IncAddrH) begin
|
if (S==3 & IncAddrH) begin
|
||||||
IncAddrH <= 0;
|
IncAddrH <= 0;
|
||||||
Addr[22:16] <= Addr[22:16]+1;
|
Addr[23:16] <= Addr[23:16]+1;
|
||||||
end
|
end
|
||||||
|
|
||||||
// Set register during S6 if accessed.
|
// Set register at end of S5 if accessed.
|
||||||
if (S==6) begin
|
if (S==5) begin
|
||||||
if (BankWR) Bank[7:0] <= D[7:0]; // Bank
|
if (BankWR) Bank[7:0] <= D[7:0]; // Bank
|
||||||
if (SetWR) FullIOEN <= D[7:0] == 8'hE5;
|
if (SetWR) FullIOEN <= D[7:0] == 8'hE5;
|
||||||
|
|
||||||
|
|
@ -183,7 +179,7 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
|
||||||
IncAddrM <= AddrLWR & Addr[7] & ~D[7];
|
IncAddrM <= AddrLWR & Addr[7] & ~D[7];
|
||||||
IncAddrH <= AddrMWR & Addr[15] & ~D[7];
|
IncAddrH <= AddrMWR & Addr[15] & ~D[7];
|
||||||
|
|
||||||
if (AddrHWR) Addr[22:16] <= D[6:0]; // Addr hi
|
if (AddrHWR) Addr[23:16] <= D[7:0]; // Addr hi
|
||||||
if (AddrMWR) Addr[15:8] <= D[7:0]; // Addr mid
|
if (AddrMWR) Addr[15:8] <= D[7:0]; // Addr mid
|
||||||
if (AddrLWR) Addr[7:0] <= D[7:0]; // Addr lo
|
if (AddrLWR) Addr[7:0] <= D[7:0]; // Addr lo
|
||||||
end
|
end
|
||||||
|
|
@ -192,7 +188,11 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
|
||||||
|
|
||||||
/* DRAM RAS/CAS */
|
/* DRAM RAS/CAS */
|
||||||
always @(posedge C7M, negedge nRES) begin
|
always @(posedge C7M, negedge nRES) begin
|
||||||
if (~nRES) begin RASr <= 1'b0; CASr <= 1'b0; ASel <= 1'b0;
|
if (~nRES) begin
|
||||||
|
RASr <= 1'b0;
|
||||||
|
ASel <= 1'b0;
|
||||||
|
CAS0r <= 1'b0;
|
||||||
|
CAS1r <= 1'b0;
|
||||||
end else begin
|
end else begin
|
||||||
// RAS already asserted in middle of S4,
|
// RAS already asserted in middle of S4,
|
||||||
// so hold RAS through S5
|
// so hold RAS through S5
|
||||||
|
|
@ -203,7 +203,11 @@ module GR8RAM(C7M, C7M_2, Q3, PHI0in, PHI1in, nRES, nMode,
|
||||||
|
|
||||||
// Refresh at end of S1 (i.e. through S2)
|
// Refresh at end of S1 (i.e. through S2)
|
||||||
// CAS whenever RAM seleced
|
// CAS whenever RAM seleced
|
||||||
CASr <= (S==1 & Ref==0) | (S==5 & RAMSEL);
|
CAS0r <= (S==1 & Ref==0) | (S==5 & RAMSEL & ~Addr[22]);
|
||||||
|
|
||||||
|
// Refresh at end of S1 (i.e. through S2)
|
||||||
|
// CAS whenever RAM seleced
|
||||||
|
CAS1r <= (S==1 & Ref==0) | (S==5 & RAMSEL & Addr[22]);
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
always @(negedge C7M_2, negedge nRES) begin
|
always @(negedge C7M_2, negedge nRES) begin
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567905339785 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909565827 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567905339800 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 21:15:39 2019 " "Processing started: Sat Sep 07 21:15:39 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567905339800 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567905339800 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909565827 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:26:05 2019 " "Processing started: Sat Sep 07 22:26:05 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909565827 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567909565827 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567905339800 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567909565827 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567905341676 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567909565947 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567905342082 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 21:15:42 2019 " "Processing ended: Sat Sep 07 21:15:42 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567905342082 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567905342082 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567905342082 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567905342082 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4521 " "Peak virtual memory: 4521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909567106 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:26:07 2019 " "Processing ended: Sat Sep 07 22:26:07 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909567106 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909567106 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909567106 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567909567106 ""}
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,3 +1,3 @@
|
||||||
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
Version_Index = 302049280
|
Version_Index = 302049280
|
||||||
Creation_Time = Sat Sep 07 21:14:51 2019
|
Creation_Time = Sat Sep 07 22:06:23 2019
|
||||||
|
|
|
||||||
|
|
@ -1,4 +1,3 @@
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567905337363 ""}
|
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567909564817 ""}
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567905337394 ""}
|
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567909564817 ""}
|
||||||
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "MODE " "Node \"MODE\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "MODE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1567905337613 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1567905337613 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4708 " "Peak virtual memory: 4708 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909564997 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:26:04 2019 " "Processing ended: Sat Sep 07 22:26:04 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909564997 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909564997 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909564997 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567909564997 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567905338144 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 21:15:38 2019 " "Processing ended: Sat Sep 07 21:15:38 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567905338144 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567905338144 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567905338144 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567905338144 ""}
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,44 @@
|
||||||
|GR8RAM
|
|GR8RAM
|
||||||
C7M => always1.IN0
|
C7M => CAS1r.CLK
|
||||||
C7M => CASr.CLK
|
C7M => CAS0r.CLK
|
||||||
C7M => RASr.CLK
|
C7M => RASr.CLK
|
||||||
C7M => ASel.CLK
|
C7M => ASel.CLK
|
||||||
|
C7M => IncAddrH.CLK
|
||||||
|
C7M => IncAddrM.CLK
|
||||||
|
C7M => IncAddrL.CLK
|
||||||
|
C7M => FullIOEN.CLK
|
||||||
|
C7M => Bank[0].CLK
|
||||||
|
C7M => Bank[1].CLK
|
||||||
|
C7M => Bank[2].CLK
|
||||||
|
C7M => Bank[3].CLK
|
||||||
|
C7M => Bank[4].CLK
|
||||||
|
C7M => Bank[5].CLK
|
||||||
|
C7M => Bank[6].CLK
|
||||||
|
C7M => Bank[7].CLK
|
||||||
|
C7M => Addr[0].CLK
|
||||||
|
C7M => Addr[1].CLK
|
||||||
|
C7M => Addr[2].CLK
|
||||||
|
C7M => Addr[3].CLK
|
||||||
|
C7M => Addr[4].CLK
|
||||||
|
C7M => Addr[5].CLK
|
||||||
|
C7M => Addr[6].CLK
|
||||||
|
C7M => Addr[7].CLK
|
||||||
|
C7M => Addr[8].CLK
|
||||||
|
C7M => Addr[9].CLK
|
||||||
|
C7M => Addr[10].CLK
|
||||||
|
C7M => Addr[11].CLK
|
||||||
|
C7M => Addr[12].CLK
|
||||||
|
C7M => Addr[13].CLK
|
||||||
|
C7M => Addr[14].CLK
|
||||||
|
C7M => Addr[15].CLK
|
||||||
|
C7M => Addr[16].CLK
|
||||||
|
C7M => Addr[17].CLK
|
||||||
|
C7M => Addr[18].CLK
|
||||||
|
C7M => Addr[19].CLK
|
||||||
|
C7M => Addr[20].CLK
|
||||||
|
C7M => Addr[21].CLK
|
||||||
|
C7M => Addr[22].CLK
|
||||||
|
C7M => Addr[23].CLK
|
||||||
C7M => CSDBEN.CLK
|
C7M => CSDBEN.CLK
|
||||||
C7M => IOROMEN.CLK
|
C7M => IOROMEN.CLK
|
||||||
C7M => REGEN.CLK
|
C7M => REGEN.CLK
|
||||||
|
|
@ -15,13 +51,13 @@ C7M => S[1].CLK
|
||||||
C7M => S[2].CLK
|
C7M => S[2].CLK
|
||||||
C7M => PHI0seen.CLK
|
C7M => PHI0seen.CLK
|
||||||
C7M => PHI1reg.CLK
|
C7M => PHI1reg.CLK
|
||||||
C7M_2 => always3.IN0
|
C7M_2 => always2.IN0
|
||||||
Q3 => ~NO_FANOUT~
|
Q3 => ~NO_FANOUT~
|
||||||
PHI0in => ~NO_FANOUT~
|
PHI0in => ~NO_FANOUT~
|
||||||
PHI1in => comb.IN0
|
PHI1in => comb.IN0
|
||||||
PHI1in => PHI1b0_MC.DATAIN
|
PHI1in => PHI1b0_MC.DATAIN
|
||||||
nRES => always0.IN0
|
nRES => always0.IN0
|
||||||
nMode => comb.DATAB
|
nMode => ~NO_FANOUT~
|
||||||
A[0] => Equal0.IN7
|
A[0] => Equal0.IN7
|
||||||
A[0] => Equal1.IN7
|
A[0] => Equal1.IN7
|
||||||
A[0] => Equal2.IN7
|
A[0] => Equal2.IN7
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,40 +1,34 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567905323534 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909562928 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567905323534 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 21:15:23 2019 " "Processing started: Sat Sep 07 21:15:23 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567905323534 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567905323534 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909562928 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:26:02 2019 " "Processing started: Sat Sep 07 22:26:02 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909562928 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567909562928 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567905323534 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567909562928 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567905327409 ""}
|
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567909563131 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567905327550 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567909563157 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567905327550 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567909563157 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 194 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567905327550 ""}
|
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(190) " "Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 190 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567909563157 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567905327550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567905327550 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567909563167 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567909563167 ""}
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567905328081 ""}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567909563197 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(133) " "Verilog HDL assignment warning at GR8RAM.v(133): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 133 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(164) " "Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567905328081 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(170) " "Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909563197 "|GR8RAM"}
|
||||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567905328487 ""}
|
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567909563267 ""}
|
||||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905328487 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567905328487 ""}
|
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563267 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567909563267 ""}
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905329066 ""}
|
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563296 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329066 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329066 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329066 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567905329066 ""}
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563296 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563296 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567909563296 ""}
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""}
|
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329394 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567905329394 ""}
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563317 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567909563317 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329644 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563327 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329847 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563341 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905329862 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563341 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330112 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563356 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330378 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563366 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330378 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909563366 ""}
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""}
|
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567909563436 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567909563436 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330566 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567905330566 ""}
|
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 131 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1567909563441 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330581 ""}
|
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567909563527 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567909563527 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567909563527 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330613 ""}
|
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909563709 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567909563709 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330628 ""}
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567909563709 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567909563709 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567909563709 ""} { "Info" "ICUT_CUT_TM_MCELLS" "105 " "Implemented 105 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567909563709 ""} { "Info" "ICUT_CUT_TM_SEXPS" "2 " "Implemented 2 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567909563709 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567909563709 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330644 ""}
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567909563757 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567905330675 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4587 " "Peak virtual memory: 4587 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909563787 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:26:03 2019 " "Processing ended: Sat Sep 07 22:26:03 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909563787 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909563787 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909563787 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909563787 ""}
|
||||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567905330972 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567905330972 ""}
|
|
||||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567905331238 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567905331238 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567905331238 ""}
|
|
||||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "7 " "Design contains 7 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567905331613 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567905331613 ""}
|
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567905331628 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567905331628 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567905331628 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567905331628 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567905331628 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567905331628 ""}
|
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567905331925 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "304 " "Peak virtual memory: 304 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567905332050 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 21:15:32 2019 " "Processing ended: Sat Sep 07 21:15:32 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567905332050 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567905332050 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567905332050 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567905332050 ""}
|
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,22 +1,22 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567905345566 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909568834 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567905345582 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 21:15:43 2019 " "Processing started: Sat Sep 07 21:15:43 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567905345582 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567905345582 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909568834 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:26:08 2019 " "Processing started: Sat Sep 07 22:26:08 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909568834 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567909568834 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567905345582 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567909568834 ""}
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567905345723 ""}
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567909568889 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567905347942 ""}
|
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567909568980 ""}
|
||||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567905347973 ""}
|
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567909568985 ""}
|
||||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567905347973 ""}
|
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567909568990 ""}
|
||||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567905348004 ""}
|
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567909569009 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567905348098 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567909569019 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567905348098 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567909569019 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348098 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348098 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348098 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569019 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569019 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569019 ""}
|
||||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567905348113 ""}
|
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567909569019 ""}
|
||||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567905348238 ""}
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567909569029 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.500 " "Worst-case setup slack is -47.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.500 -1979.500 C7M " " -47.500 -1979.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567905348317 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -2056.000 C7M " " -47.000 -2056.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567905348332 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909569039 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567905348348 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567909569049 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567905348363 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567909569049 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -450.000 C7M " " -4.500 -450.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567905348379 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -468.000 C7M " " -4.500 -468.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909569049 ""}
|
||||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567905348488 ""}
|
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567909569219 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567905348535 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567909569239 ""}
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567905348535 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567909569239 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "259 " "Peak virtual memory: 259 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567905348676 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 21:15:48 2019 " "Processing ended: Sat Sep 07 21:15:48 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567905348676 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567905348676 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567905348676 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567905348676 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909569380 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:26:09 2019 " "Processing ended: Sat Sep 07 22:26:09 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909569380 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909569380 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909569380 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909569380 ""}
|
||||||
|
|
|
||||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
||||||
start_full_compilation:s:00:00:28
|
start_full_compilation:s:00:00:07
|
||||||
start_analysis_synthesis:s:00:00:11-start_full_compilation
|
start_analysis_synthesis:s:00:00:02-start_full_compilation
|
||||||
start_analysis_elaboration:s-start_full_compilation
|
start_analysis_elaboration:s-start_full_compilation
|
||||||
start_fitter:s:00:00:06-start_full_compilation
|
start_fitter:s:00:00:01-start_full_compilation
|
||||||
start_assembler:s:00:00:04-start_full_compilation
|
start_assembler:s:00:00:03-start_full_compilation
|
||||||
start_timing_analyzer:s:00:00:07-start_full_compilation
|
start_timing_analyzer:s:00:00:01-start_full_compilation
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
|
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
|
||||||
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END
|
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
|
||||||
|
|
||||||
|
|
||||||
-- Copyright (C) 1991-2013 Altera Corporation
|
-- Copyright (C) 1991-2013 Altera Corporation
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
|
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
|
||||||
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END
|
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
|
||||||
|
|
||||||
|
|
||||||
-- Copyright (C) 1991-2013 Altera Corporation
|
-- Copyright (C) 1991-2013 Altera Corporation
|
||||||
|
|
|
||||||
|
|
@ -1,78 +1,72 @@
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567725517560 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909235870 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567725517560 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 19:18:37 2019 " "Processing started: Thu Sep 05 19:18:37 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567725517560 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567725517560 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909235870 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:20:35 2019 " "Processing started: Sat Sep 07 22:20:35 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909235870 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567909235870 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567725517560 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567909235870 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567725522623 ""}
|
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567909236067 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(38) " "Verilog HDL warning at GR8RAM.v(38): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567725522951 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(52) " "Verilog HDL warning at GR8RAM.v(52): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567909236087 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(46) " "Verilog HDL warning at GR8RAM.v(46): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 46 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567725522951 ""}
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(60) " "Verilog HDL warning at GR8RAM.v(60): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 60 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1567909236087 ""}
|
||||||
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(194) " "Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 194 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567725522951 ""}
|
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "GR8RAM.v(190) " "Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 190 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1567909236087 ""}
|
||||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567725522967 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567725522967 ""}
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1567909236087 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1567909236087 ""}
|
||||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567725523233 ""}
|
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1567909236207 ""}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523248 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(30) " "Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(126) " "Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 126 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 GR8RAM.v(133) " "Verilog HDL assignment warning at GR8RAM.v(133): truncated value with size 32 to match size of target (3)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 133 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(131) " "Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 131 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(163) " "Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(159) " "Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(168) " "Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(164) " "Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||||
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 GR8RAM.v(174) " "Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567725523264 "|GR8RAM"}
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(170) " "Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1567909236207 "|GR8RAM"}
|
||||||
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567725523811 ""}
|
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Ref_rtl_0 4 " "Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"Ref_rtl_0\"" { } { } 0 19001 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567909236297 ""}
|
||||||
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 168 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 163 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725523811 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567725523811 ""}
|
{ "Info" "ILPMS_INFERENCING_SUMMARY" "4 " "Inferred 4 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add0 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add0\"" { } { { "GR8RAM.v" "Add0" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add4 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add4\"" { } { { "GR8RAM.v" "Add4" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 164 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add3 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add3\"" { } { { "GR8RAM.v" "Add3" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 159 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "Add5 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"Add5\"" { } { { "GR8RAM.v" "Add5" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 170 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236297 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1567909236297 ""}
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725524280 ""}
|
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:Ref_rtl_0 " "Elaborated megafunction instantiation \"lpm_counter:Ref_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236367 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524280 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524280 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524280 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567725524280 ""}
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:Ref_rtl_0 " "Instantiated megafunction \"lpm_counter:Ref_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Parameter \"LPM_WIDTH\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Parameter \"LPM_DIRECTION\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236367 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236367 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567909236367 ""}
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""}
|
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524561 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567725524561 ""}
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Parameter \"LPM_WIDTH\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236387 ""} } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567909236387 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725524920 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\] lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 260 9 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236417 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525170 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236487 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525233 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 178 5 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236507 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525561 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|look_add:look_ahead_unit lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|look_add:look_ahead_unit\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 263 4 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236517 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525764 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236527 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725525811 ""}
|
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 270 2 0 } } { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 30 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567909236537 ""}
|
||||||
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""}
|
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567909236674 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567909236674 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add5 " "Instantiated megafunction \"lpm_add_sub:Add5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 7 " "Parameter \"LPM_WIDTH\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526061 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1567725526061 ""}
|
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 131 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 -1 1567909236681 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 250 4 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526108 ""}
|
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567909236777 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567909236777 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567909236777 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 86 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526139 ""}
|
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "nMode " "No output dependent on input pin \"nMode\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|nMode"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567909236968 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567909236968 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 191 5 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526170 ""}
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "168 " "Implemented 168 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567909236968 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567909236968 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567909236968 ""} { "Info" "ICUT_CUT_TM_MCELLS" "105 " "Implemented 105 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567909236968 ""} { "Info" "ICUT_CUT_TM_SEXPS" "2 " "Implemented 2 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567909236968 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567909236968 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "addcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf" 192 10 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526217 ""}
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567909237078 ""}
|
||||||
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add5\|altshift:result_ext_latency_ffs lpm_add_sub:Add5 " "Elaborated megafunction instantiation \"lpm_add_sub:Add5\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add5\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 2 0 } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 174 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1567725526264 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4586 " "Peak virtual memory: 4586 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909237128 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:20:37 2019 " "Processing ended: Sat Sep 07 22:20:37 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909237128 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909237128 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909237128 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909237128 ""}
|
||||||
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "32 " "Ignored 32 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "32 " "Ignored 32 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 -1 1567725526655 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 -1 1567725526655 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567909238337 ""}
|
||||||
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "C7M " "Promoted clock signal driven by pin \"C7M\" to global clock signal" { } { } 0 280014 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "Quartus II" 0 -1 1567725526874 ""} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "nRES " "Promoted clear signal driven by pin \"nRES\" to global clear signal" { } { } 0 280015 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0 "Quartus II" 0 -1 1567725526874 ""} } { } 0 280013 "Promoted pin-driven signal(s) to global signal" 0 0 "Quartus II" 0 -1 1567725526874 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909238337 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:20:37 2019 " "Processing started: Sat Sep 07 22:20:37 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909238337 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567909238337 ""}
|
||||||
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "8 " "Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "Q3 " "No output dependent on input pin \"Q3\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|Q3"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PHI0in " "No output dependent on input pin \"PHI0in\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 7 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|PHI0in"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "MODE " "No output dependent on input pin \"MODE\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 8 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|MODE"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[11\] " "No output dependent on input pin \"A\[11\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[12\] " "No output dependent on input pin \"A\[12\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[13\] " "No output dependent on input pin \"A\[13\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[14\] " "No output dependent on input pin \"A\[14\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "A\[15\] " "No output dependent on input pin \"A\[15\]\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 26 -1 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1567725527295 "|GR8RAM|A[15]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1567725527295 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567909238337 ""}
|
||||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "165 " "Implemented 165 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "27 " "Implemented 27 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1567725527311 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1567725527311 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "16 " "Implemented 16 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1567725527311 ""} { "Info" "ICUT_CUT_TM_MCELLS" "103 " "Implemented 103 macrocells" { } { } 0 21063 "Implemented %1!d! macrocells" 0 0 "Quartus II" 0 -1 1567725527311 ""} { "Info" "ICUT_CUT_TM_SEXPS" "1 " "Implemented 1 shareable expanders" { } { } 0 21073 "Implemented %1!d! shareable expanders" 0 0 "Quartus II" 0 -1 1567725527311 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1567725527311 ""}
|
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567909239087 ""}
|
||||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1567725527827 ""}
|
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567909239087 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "312 " "Peak virtual memory: 312 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567725527983 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 19:18:47 2019 " "Processing ended: Thu Sep 05 19:18:47 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567725527983 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567725527983 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567725527983 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567725527983 ""}
|
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567909239087 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1567725531546 ""}
|
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567909239177 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567725531561 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 19:18:49 2019 " "Processing started: Thu Sep 05 19:18:49 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567725531561 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1567725531561 ""}
|
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567909239187 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1567725531561 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4709 " "Peak virtual memory: 4709 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909239487 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:20:39 2019 " "Processing ended: Sat Sep 07 22:20:39 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909239487 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909239487 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909239487 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567909239487 ""}
|
||||||
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1567725531718 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567909240407 ""}
|
||||||
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1567725531718 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909240407 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:20:40 2019 " "Processing started: Sat Sep 07 22:20:40 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909240407 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567909240407 ""}
|
||||||
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1567725531718 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567909240407 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1567725533624 ""}
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567909240527 ""}
|
||||||
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM7128SLC84-15 " "Selected device EPM7128SLC84-15 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1567725533640 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4521 " "Peak virtual memory: 4521 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909240697 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:20:40 2019 " "Processing ended: Sat Sep 07 22:20:40 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909240697 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909240697 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909240697 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567909240697 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "287 " "Peak virtual memory: 287 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567725534390 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 19:18:54 2019 " "Processing ended: Thu Sep 05 19:18:54 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567725534390 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567725534390 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567725534390 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1567725534390 ""}
|
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567909241307 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1567725536421 ""}
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567909241748 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567725536437 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 19:18:56 2019 " "Processing started: Thu Sep 05 19:18:56 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567725536437 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1567725536437 ""}
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241748 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 07 22:20:41 2019 " "Processing started: Sat Sep 07 22:20:41 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567909241748 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567909241748 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1567725536437 ""}
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567909241748 ""}
|
||||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1567725538953 ""}
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567909241819 ""}
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567725539359 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 19:18:59 2019 " "Processing ended: Thu Sep 05 19:18:59 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567725539359 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567725539359 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567725539359 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1567725539359 ""}
|
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567909241914 ""}
|
||||||
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1567725540062 ""}
|
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567909241914 ""}
|
||||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1567725542547 ""}
|
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567909241924 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1567725542547 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 05 19:19:00 2019 " "Processing started: Thu Sep 05 19:19:00 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1567725542547 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1567725542547 ""}
|
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567909241954 ""}
|
||||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1567725542547 ""}
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567909241974 ""}
|
||||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1567725542640 ""}
|
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567909241974 ""}
|
||||||
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1567725544453 ""}
|
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241974 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241974 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241974 ""}
|
||||||
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1567725544469 ""}
|
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567909241974 ""}
|
||||||
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1567725544484 ""}
|
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567909241984 ""}
|
||||||
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." { } { } 0 335095 "TimeQuest Timing Analyzer does not support the analysis of latches as synchronous elements for the currently selected device family." 0 0 "Quartus II" 0 -1 1567725544547 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -47.000 " "Worst-case setup slack is -47.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -47.000 -2056.000 C7M " " -47.000 -2056.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -27.500 -33.000 C7M_2 " " -27.500 -33.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909241994 ""}
|
||||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1567725544594 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909242004 ""}
|
||||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1567725544594 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567909242004 ""}
|
||||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M C7M " "create_clock -period 1.000 -name C7M C7M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544594 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C7M_2 C7M_2 " "create_clock -period 1.000 -name C7M_2 C7M_2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544594 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544594 ""}
|
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567909242014 ""}
|
||||||
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1567725544609 ""}
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -468.000 C7M " " -4.500 -468.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567909242014 ""}
|
||||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1567725544719 ""}
|
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567909242084 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -21.500 " "Worst-case setup slack is -21.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -21.500 -926.500 C7M " " -21.500 -926.500 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -14.500 -20.000 C7M_2 " " -14.500 -20.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567725544766 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567909242100 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -1.500 " "Worst-case hold slack is -1.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.500 -3.000 C7M_2 " " -1.500 -3.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.000 0.000 C7M " " 5.000 0.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567725544781 ""}
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567909242100 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567725544797 ""}
|
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4530 " "Peak virtual memory: 4530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567909242170 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Sep 07 22:20:42 2019 " "Processing ended: Sat Sep 07 22:20:42 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567909242170 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567909242170 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567909242170 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909242170 ""}
|
||||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1567725544797 ""}
|
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567909242810 ""}
|
||||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -5.500 " "Worst-case minimum pulse width slack is -5.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.500 -22.000 C7M_2 " " -5.500 -22.000 C7M_2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.500 -450.000 C7M " " -4.500 -450.000 C7M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1567725544812 ""}
|
|
||||||
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1567725544953 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567725545000 ""}
|
|
||||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1567725545000 ""}
|
|
||||||
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "267 " "Peak virtual memory: 267 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1567725545125 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 05 19:19:05 2019 " "Processing ended: Thu Sep 05 19:19:05 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1567725545125 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1567725545125 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1567725545125 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567725545125 ""}
|
|
||||||
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus II Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1567725546000 ""}
|
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
||||||
Assembler report for GR8RAM
|
Assembler report for GR8RAM
|
||||||
Sat Sep 07 21:15:42 2019
|
Sat Sep 07 22:26:07 2019
|
||||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
|
@ -10,7 +10,7 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
2. Assembler Summary
|
2. Assembler Summary
|
||||||
3. Assembler Settings
|
3. Assembler Settings
|
||||||
4. Assembler Generated Files
|
4. Assembler Generated Files
|
||||||
5. Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof
|
5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof
|
||||||
6. Assembler Messages
|
6. Assembler Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -37,7 +37,7 @@ applicable agreement for further details.
|
||||||
+---------------------------------------------------------------+
|
+---------------------------------------------------------------+
|
||||||
; Assembler Summary ;
|
; Assembler Summary ;
|
||||||
+-----------------------+---------------------------------------+
|
+-----------------------+---------------------------------------+
|
||||||
; Assembler Status ; Successful - Sat Sep 07 21:15:42 2019 ;
|
; Assembler Status ; Successful - Sat Sep 07 22:26:07 2019 ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX7000S ;
|
; Family ; MAX7000S ;
|
||||||
|
|
@ -73,39 +73,39 @@ applicable agreement for further details.
|
||||||
+-----------------------------------------------------------------------------+----------+---------------+
|
+-----------------------------------------------------------------------------+----------+---------------+
|
||||||
|
|
||||||
|
|
||||||
+----------------------------------------------+
|
+--------------------------------------------------------------------+
|
||||||
; Assembler Generated Files ;
|
; Assembler Generated Files ;
|
||||||
+----------------------------------------------+
|
+--------------------------------------------------------------------+
|
||||||
; File Name ;
|
; File Name ;
|
||||||
+----------------------------------------------+
|
+--------------------------------------------------------------------+
|
||||||
; Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||||
+----------------------------------------------+
|
+--------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------------------------+
|
||||||
; Assembler Device Options: Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
; Assembler Device Options: C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pof ;
|
||||||
+----------------+-------------------------------------------------------+
|
+----------------+-----------------------------------------------------------------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+----------------+-------------------------------------------------------+
|
+----------------+-----------------------------------------------------------------------------+
|
||||||
; Device ; EPM7128SLC84-15 ;
|
; Device ; EPM7128SLC84-15 ;
|
||||||
; JTAG usercode ; 0x00000000 ;
|
; JTAG usercode ; 0x00000000 ;
|
||||||
; Checksum ; 0x0017B9A5 ;
|
; Checksum ; 0x0017D2F6 ;
|
||||||
+----------------+-------------------------------------------------------+
|
+----------------+-----------------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+--------------------+
|
+--------------------+
|
||||||
; Assembler Messages ;
|
; Assembler Messages ;
|
||||||
+--------------------+
|
+--------------------+
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus II 32-bit Assembler
|
Info: Running Quartus II 64-Bit Assembler
|
||||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
Info: Processing started: Sat Sep 07 21:15:39 2019
|
Info: Processing started: Sat Sep 07 22:26:05 2019
|
||||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
Info (115030): Assembler is generating device programming files
|
Info (115030): Assembler is generating device programming files
|
||||||
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
|
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
|
||||||
Info: Peak virtual memory: 277 megabytes
|
Info: Peak virtual memory: 4521 megabytes
|
||||||
Info: Processing ended: Sat Sep 07 21:15:42 2019
|
Info: Processing ended: Sat Sep 07 22:26:07 2019
|
||||||
Info: Elapsed time: 00:00:03
|
Info: Elapsed time: 00:00:02
|
||||||
Info: Total CPU time (on all processors): 00:00:02
|
Info: Total CPU time (on all processors): 00:00:00
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1 +1 @@
|
||||||
Sat Sep 07 21:15:49 2019
|
Sat Sep 07 22:26:09 2019
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
Fitter report for GR8RAM
|
Fitter report for GR8RAM
|
||||||
Sat Sep 07 21:15:37 2019
|
Sat Sep 07 22:26:04 2019
|
||||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
|
@ -9,26 +9,27 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
1. Legal Notice
|
1. Legal Notice
|
||||||
2. Fitter Summary
|
2. Fitter Summary
|
||||||
3. Fitter Settings
|
3. Fitter Settings
|
||||||
4. Pin-Out File
|
4. Parallel Compilation
|
||||||
5. Fitter Resource Usage Summary
|
5. Pin-Out File
|
||||||
6. Input Pins
|
6. Fitter Resource Usage Summary
|
||||||
7. Output Pins
|
7. Input Pins
|
||||||
8. Bidir Pins
|
8. Output Pins
|
||||||
9. All Package Pins
|
9. Bidir Pins
|
||||||
10. I/O Standard
|
10. All Package Pins
|
||||||
11. Dedicated Inputs I/O
|
11. I/O Standard
|
||||||
12. Output Pin Default Load For Reported TCO
|
12. Dedicated Inputs I/O
|
||||||
13. Fitter Resource Utilization by Entity
|
13. Output Pin Default Load For Reported TCO
|
||||||
14. Control Signals
|
14. Fitter Resource Utilization by Entity
|
||||||
15. Global & Other Fast Signals
|
15. Control Signals
|
||||||
16. Non-Global High Fan-Out Signals
|
16. Global & Other Fast Signals
|
||||||
17. Other Routing Usage Summary
|
17. Non-Global High Fan-Out Signals
|
||||||
18. LAB External Interconnect
|
18. Other Routing Usage Summary
|
||||||
19. LAB Macrocells
|
19. LAB External Interconnect
|
||||||
20. Shareable Expander
|
20. LAB Macrocells
|
||||||
21. Logic Cell Interconnection
|
21. Shareable Expander
|
||||||
22. Fitter Device Options
|
22. Logic Cell Interconnection
|
||||||
23. Fitter Messages
|
23. Fitter Device Options
|
||||||
|
24. Fitter Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -54,14 +55,14 @@ applicable agreement for further details.
|
||||||
+-----------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------+
|
||||||
; Fitter Summary ;
|
; Fitter Summary ;
|
||||||
+---------------------------+-------------------------------------------------+
|
+---------------------------+-------------------------------------------------+
|
||||||
; Fitter Status ; Successful - Sat Sep 07 21:15:37 2019 ;
|
; Fitter Status ; Successful - Sat Sep 07 22:26:04 2019 ;
|
||||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX7000S ;
|
; Family ; MAX7000S ;
|
||||||
; Device ; EPM7128SLC84-15 ;
|
; Device ; EPM7128SLC84-15 ;
|
||||||
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
||||||
; Total macrocells ; 103 / 128 ( 80 % ) ;
|
; Total macrocells ; 105 / 128 ( 82 % ) ;
|
||||||
; Total pins ; 65 / 68 ( 96 % ) ;
|
; Total pins ; 65 / 68 ( 96 % ) ;
|
||||||
+---------------------------+-------------------------------------------------+
|
+---------------------------+-------------------------------------------------+
|
||||||
|
|
||||||
|
|
@ -86,10 +87,21 @@ applicable agreement for further details.
|
||||||
+----------------------------------------------------------------------------+-----------------------+---------------+
|
+----------------------------------------------------------------------------+-----------------------+---------------+
|
||||||
|
|
||||||
|
|
||||||
|
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||||
|
+-------------------------------------+
|
||||||
|
; Parallel Compilation ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
; Processors ; Number ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
; Number detected on machine ; 8 ;
|
||||||
|
; Maximum allowed ; 1 ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
|
||||||
|
|
||||||
+--------------+
|
+--------------+
|
||||||
; Pin-Out File ;
|
; Pin-Out File ;
|
||||||
+--------------+
|
+--------------+
|
||||||
The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
The pin-out file can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------+
|
+---------------------------------------------------+
|
||||||
|
|
@ -97,21 +109,21 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
+------------------------------+--------------------+
|
+------------------------------+--------------------+
|
||||||
; Resource ; Usage ;
|
; Resource ; Usage ;
|
||||||
+------------------------------+--------------------+
|
+------------------------------+--------------------+
|
||||||
; Logic cells ; 103 / 128 ( 80 % ) ;
|
; Logic cells ; 105 / 128 ( 82 % ) ;
|
||||||
; Registers ; 52 / 128 ( 41 % ) ;
|
; Registers ; 54 / 128 ( 42 % ) ;
|
||||||
; Number of pterms used ; 260 ;
|
; Number of pterms used ; 267 ;
|
||||||
; I/O pins ; 65 / 68 ( 96 % ) ;
|
; I/O pins ; 65 / 68 ( 96 % ) ;
|
||||||
; -- Clock pins ; 2 / 2 ( 100 % ) ;
|
; -- Clock pins ; 2 / 2 ( 100 % ) ;
|
||||||
; -- Dedicated input pins ; 2 / 2 ( 100 % ) ;
|
; -- Dedicated input pins ; 2 / 2 ( 100 % ) ;
|
||||||
; ; ;
|
; ; ;
|
||||||
; Global signals ; 2 ;
|
; Global signals ; 2 ;
|
||||||
; Shareable expanders ; 1 / 128 ( < 1 % ) ;
|
; Shareable expanders ; 2 / 128 ( 2 % ) ;
|
||||||
; Parallel expanders ; 0 / 120 ( 0 % ) ;
|
; Parallel expanders ; 0 / 120 ( 0 % ) ;
|
||||||
; Cells using turbo bit ; 16 / 128 ( 13 % ) ;
|
; Cells using turbo bit ; 16 / 128 ( 13 % ) ;
|
||||||
; Maximum fan-out ; 52 ;
|
; Maximum fan-out ; 54 ;
|
||||||
; Highest non-global fan-out ; 51 ;
|
; Highest non-global fan-out ; 54 ;
|
||||||
; Total fan-out ; 831 ;
|
; Total fan-out ; 862 ;
|
||||||
; Average fan-out ; 4.92 ;
|
; Average fan-out ; 5.01 ;
|
||||||
+------------------------------+--------------------+
|
+------------------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -136,7 +148,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; A[7] ; 5 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
|
; A[7] ; 5 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; A[8] ; 9 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
|
; A[8] ; 9 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; A[9] ; 10 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
|
; A[9] ; 10 ; -- ; 1 ; 1 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; C7M ; 83 ; -- ; -- ; 50 ; 0 ; yes ; no ; TTL ; User ;
|
; C7M ; 83 ; -- ; -- ; 52 ; 0 ; yes ; no ; TTL ; User ;
|
||||||
; C7M_2 ; 84 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
|
; C7M_2 ; 84 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
|
; PHI0in ; 8 ; -- ; 1 ; 0 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
|
; PHI1in ; 2 ; -- ; -- ; 2 ; 0 ; no ; no ; TTL ; User ;
|
||||||
|
|
@ -144,8 +156,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; nDEVSEL ; 21 ; -- ; 2 ; 16 ; 0 ; no ; no ; TTL ; User ;
|
; nDEVSEL ; 21 ; -- ; 2 ; 16 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; nIOSEL ; 74 ; -- ; 8 ; 13 ; 0 ; no ; no ; TTL ; User ;
|
; nIOSEL ; 74 ; -- ; 8 ; 13 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ;
|
; nIOSTRB ; 24 ; -- ; 3 ; 12 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; nMode ; 37 ; -- ; 4 ; 1 ; 0 ; no ; no ; TTL ; Fitter ;
|
; nMode ; 44 ; -- ; 5 ; 0 ; 0 ; no ; no ; TTL ; User ;
|
||||||
; nRES ; 1 ; -- ; -- ; 52 ; 0 ; yes ; no ; TTL ; User ;
|
; nRES ; 1 ; -- ; -- ; 54 ; 0 ; yes ; no ; TTL ; User ;
|
||||||
; nWE ; 20 ; -- ; 2 ; 10 ; 0 ; no ; no ; TTL ; User ;
|
; nWE ; 20 ; -- ; 2 ; 10 ; 0 ; no ; no ; TTL ; User ;
|
||||||
+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
|
+---------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
|
||||||
|
|
||||||
|
|
@ -188,7 +200,7 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; D[4] ; 29 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
|
; D[4] ; 29 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
|
||||||
; D[5] ; 28 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
|
; D[5] ; 28 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
|
||||||
; D[6] ; 27 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
|
; D[6] ; 27 ; -- ; 3 ; 6 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
|
||||||
; D[7] ; 25 ; -- ; 3 ; 7 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
|
; D[7] ; 25 ; -- ; 3 ; 8 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; DOE~5 ; - ;
|
||||||
; RD[0] ; 73 ; -- ; 8 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
|
; RD[0] ; 73 ; -- ; 8 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
|
||||||
; RD[1] ; 70 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
|
; RD[1] ; 70 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
|
||||||
; RD[2] ; 69 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
|
; RD[2] ; 69 ; -- ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; TTL ; User ; 10 pF ; RDOE~1 ; - ;
|
||||||
|
|
@ -241,14 +253,14 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
|
||||||
; 34 ; 33 ; -- ; D[2] ; bidir ; TTL ; ; Y ;
|
; 34 ; 33 ; -- ; D[2] ; bidir ; TTL ; ; Y ;
|
||||||
; 35 ; 34 ; -- ; D[1] ; bidir ; TTL ; ; Y ;
|
; 35 ; 34 ; -- ; D[1] ; bidir ; TTL ; ; Y ;
|
||||||
; 36 ; 35 ; -- ; D[0] ; bidir ; TTL ; ; Y ;
|
; 36 ; 35 ; -- ; D[0] ; bidir ; TTL ; ; Y ;
|
||||||
; 37 ; 36 ; -- ; nMode ; input ; TTL ; ; N ;
|
; 37 ; 36 ; -- ; RESERVED ; ; ; ; ;
|
||||||
; 38 ; 37 ; -- ; VCCIO ; power ; ; 5.0V ; ;
|
; 38 ; 37 ; -- ; VCCIO ; power ; ; 5.0V ; ;
|
||||||
; 39 ; 38 ; -- ; nCAS0 ; output ; TTL ; ; Y ;
|
; 39 ; 38 ; -- ; nCAS0 ; output ; TTL ; ; Y ;
|
||||||
; 40 ; 39 ; -- ; nCAS1 ; output ; TTL ; ; Y ;
|
; 40 ; 39 ; -- ; nCAS1 ; output ; TTL ; ; Y ;
|
||||||
; 41 ; 40 ; -- ; nRCS ; output ; TTL ; ; Y ;
|
; 41 ; 40 ; -- ; nRCS ; output ; TTL ; ; Y ;
|
||||||
; 42 ; 41 ; -- ; GND ; gnd ; ; ; ;
|
; 42 ; 41 ; -- ; GND ; gnd ; ; ; ;
|
||||||
; 43 ; 42 ; -- ; VCCINT ; power ; ; 5.0V ; ;
|
; 43 ; 42 ; -- ; VCCINT ; power ; ; 5.0V ; ;
|
||||||
; 44 ; 43 ; -- ; RESERVED ; ; ; ; ;
|
; 44 ; 43 ; -- ; nMode ; input ; TTL ; ; Y ;
|
||||||
; 45 ; 44 ; -- ; nROE ; output ; TTL ; ; Y ;
|
; 45 ; 44 ; -- ; nROE ; output ; TTL ; ; Y ;
|
||||||
; 46 ; 45 ; -- ; RA[9] ; output ; TTL ; ; Y ;
|
; 46 ; 45 ; -- ; RA[9] ; output ; TTL ; ; Y ;
|
||||||
; 47 ; 46 ; -- ; GND ; gnd ; ; ; ;
|
; 47 ; 46 ; -- ; GND ; gnd ; ; ; ;
|
||||||
|
|
@ -331,7 +343,7 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
+----------------------------+------------+------+-------------------------------+--------------+
|
+----------------------------+------------+------+-------------------------------+--------------+
|
||||||
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
|
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
|
||||||
+----------------------------+------------+------+-------------------------------+--------------+
|
+----------------------------+------------+------+-------------------------------+--------------+
|
||||||
; |GR8RAM ; 103 ; 65 ; |GR8RAM ; work ;
|
; |GR8RAM ; 105 ; 65 ; |GR8RAM ; work ;
|
||||||
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
|
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
|
||||||
+----------------------------+------------+------+-------------------------------+--------------+
|
+----------------------------+------------+------+-------------------------------+--------------+
|
||||||
|
|
||||||
|
|
@ -345,17 +357,17 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ;
|
; A[1] ; PIN_76 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||||
; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ;
|
; A[2] ; PIN_77 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||||
; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ;
|
; A[3] ; PIN_79 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||||
; BankWR_MC ; LC106 ; 8 ; Clock enable ; no ; -- ; -- ;
|
; BankWR_MC ; LC102 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||||
; C7M ; PIN_83 ; 50 ; Clock ; yes ; On ; -- ;
|
; C7M ; PIN_83 ; 52 ; Clock ; yes ; On ; -- ;
|
||||||
; C7M_2 ; PIN_84 ; 2 ; Clock ; no ; -- ; -- ;
|
; C7M_2 ; PIN_84 ; 2 ; Clock ; no ; -- ; -- ;
|
||||||
; PHI1b9_MC ; LC50 ; 5 ; Clock enable ; no ; -- ; -- ;
|
; PHI1b9_MC ; LC123 ; 5 ; Clock enable ; no ; -- ; -- ;
|
||||||
; REGEN ; LC41 ; 7 ; Clock enable ; no ; -- ; -- ;
|
; REGEN ; LC36 ; 7 ; Clock enable ; no ; -- ; -- ;
|
||||||
; S[0] ; LC123 ; 49 ; Clock enable ; no ; -- ; -- ;
|
; S[0] ; LC122 ; 50 ; Clock enable ; no ; -- ; -- ;
|
||||||
; S[1] ; LC113 ; 49 ; Clock enable ; no ; -- ; -- ;
|
; S[1] ; LC124 ; 53 ; Clock enable ; no ; -- ; -- ;
|
||||||
; S[2] ; LC127 ; 51 ; Clock enable ; no ; -- ; -- ;
|
; S[2] ; LC117 ; 54 ; Clock enable ; no ; -- ; -- ;
|
||||||
; nDEVSEL ; PIN_21 ; 16 ; Clock enable ; no ; -- ; -- ;
|
; nDEVSEL ; PIN_21 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||||
; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ;
|
; nIOSEL ; PIN_74 ; 13 ; Clock enable ; no ; -- ; -- ;
|
||||||
; nRES ; PIN_1 ; 52 ; Async. clear ; yes ; On ; -- ;
|
; nRES ; PIN_1 ; 54 ; Async. clear ; yes ; On ; -- ;
|
||||||
; nWE ; PIN_20 ; 10 ; Clock enable ; no ; -- ; -- ;
|
; nWE ; PIN_20 ; 10 ; Clock enable ; no ; -- ; -- ;
|
||||||
+-----------+----------+---------+--------------+--------+----------------------+------------------+
|
+-----------+----------+---------+--------------+--------+----------------------+------------------+
|
||||||
|
|
||||||
|
|
@ -365,8 +377,8 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
+------+----------+---------+----------------------+------------------+
|
+------+----------+---------+----------------------+------------------+
|
||||||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||||
+------+----------+---------+----------------------+------------------+
|
+------+----------+---------+----------------------+------------------+
|
||||||
; C7M ; PIN_83 ; 50 ; On ; -- ;
|
; C7M ; PIN_83 ; 52 ; On ; -- ;
|
||||||
; nRES ; PIN_1 ; 52 ; On ; -- ;
|
; nRES ; PIN_1 ; 54 ; On ; -- ;
|
||||||
+------+----------+---------+----------------------+------------------+
|
+------+----------+---------+----------------------+------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -375,9 +387,9 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
+-------------------------------+---------+
|
+-------------------------------+---------+
|
||||||
; Name ; Fan-Out ;
|
; Name ; Fan-Out ;
|
||||||
+-------------------------------+---------+
|
+-------------------------------+---------+
|
||||||
; S[2] ; 51 ;
|
; S[2] ; 54 ;
|
||||||
; S[1] ; 49 ;
|
; S[1] ; 53 ;
|
||||||
; S[0] ; 49 ;
|
; S[0] ; 50 ;
|
||||||
; nDEVSEL ; 16 ;
|
; nDEVSEL ; 16 ;
|
||||||
; A[3] ; 15 ;
|
; A[3] ; 15 ;
|
||||||
; A[2] ; 15 ;
|
; A[2] ; 15 ;
|
||||||
|
|
@ -385,36 +397,41 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; A[0] ; 15 ;
|
; A[0] ; 15 ;
|
||||||
; nIOSEL ; 13 ;
|
; nIOSEL ; 13 ;
|
||||||
; nIOSTRB ; 12 ;
|
; nIOSTRB ; 12 ;
|
||||||
; Addr[0] ; 11 ;
|
; IncAddrM ; 11 ;
|
||||||
; Addr[8] ; 11 ;
|
; Addr[8] ; 11 ;
|
||||||
|
; Addr[0] ; 11 ;
|
||||||
; ASel ; 11 ;
|
; ASel ; 11 ;
|
||||||
; IncAddrL ; 11 ;
|
|
||||||
; nWE ; 10 ;
|
; nWE ; 10 ;
|
||||||
; IncAddrM ; 10 ;
|
|
||||||
; Addr[9] ; 10 ;
|
; Addr[9] ; 10 ;
|
||||||
; Addr[1] ; 10 ;
|
; Addr[1] ; 10 ;
|
||||||
|
; Addr[16] ; 10 ;
|
||||||
|
; IncAddrL ; 10 ;
|
||||||
|
; IncAddrH ; 9 ;
|
||||||
; Addr[10] ; 9 ;
|
; Addr[10] ; 9 ;
|
||||||
|
; Addr[17] ; 9 ;
|
||||||
; Addr[2] ; 9 ;
|
; Addr[2] ; 9 ;
|
||||||
; Addr[16] ; 9 ;
|
|
||||||
; AddrLWR_MC ; 9 ;
|
; AddrLWR_MC ; 9 ;
|
||||||
; AddrMWR_MC ; 9 ;
|
; AddrMWR_MC ; 9 ;
|
||||||
|
; D[7]~7 ; 8 ;
|
||||||
; FullIOEN ; 8 ;
|
; FullIOEN ; 8 ;
|
||||||
; IncAddrH ; 8 ;
|
|
||||||
; Addr[11] ; 8 ;
|
; Addr[11] ; 8 ;
|
||||||
|
; Addr[18] ; 8 ;
|
||||||
; Addr[3] ; 8 ;
|
; Addr[3] ; 8 ;
|
||||||
; Addr[17] ; 8 ;
|
|
||||||
; Bank[0] ; 8 ;
|
; Bank[0] ; 8 ;
|
||||||
; BankWR_MC ; 8 ;
|
; BankWR_MC ; 8 ;
|
||||||
|
; AddrHWR_MC ; 8 ;
|
||||||
|
; RAMSEL_MC ; 8 ;
|
||||||
; RDOE~1 ; 8 ;
|
; RDOE~1 ; 8 ;
|
||||||
; DOE~5 ; 8 ;
|
; DOE~5 ; 8 ;
|
||||||
; D[7]~7 ; 7 ;
|
; Addr[22] ; 7 ;
|
||||||
; Addr[12] ; 7 ;
|
; Addr[12] ; 7 ;
|
||||||
; Addr[18] ; 7 ;
|
; Addr[19] ; 7 ;
|
||||||
; Addr[4] ; 7 ;
|
; Addr[4] ; 7 ;
|
||||||
; Bank[1] ; 7 ;
|
; Bank[1] ; 7 ;
|
||||||
; AddrHWR_MC ; 7 ;
|
; lpm_counter:Ref_rtl_0|dffs[3] ; 7 ;
|
||||||
; RAMSEL_MC ; 7 ;
|
; lpm_counter:Ref_rtl_0|dffs[2] ; 7 ;
|
||||||
; REGEN ; 7 ;
|
; REGEN ; 7 ;
|
||||||
|
; lpm_counter:Ref_rtl_0|dffs[0] ; 7 ;
|
||||||
; D[6]~6 ; 6 ;
|
; D[6]~6 ; 6 ;
|
||||||
; D[5]~5 ; 6 ;
|
; D[5]~5 ; 6 ;
|
||||||
; D[4]~4 ; 6 ;
|
; D[4]~4 ; 6 ;
|
||||||
|
|
@ -423,22 +440,17 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; D[1]~1 ; 6 ;
|
; D[1]~1 ; 6 ;
|
||||||
; D[0]~0 ; 6 ;
|
; D[0]~0 ; 6 ;
|
||||||
; Addr[13] ; 6 ;
|
; Addr[13] ; 6 ;
|
||||||
; Addr[19] ; 6 ;
|
; Addr[20] ; 6 ;
|
||||||
; Bank[2] ; 6 ;
|
; Bank[2] ; 6 ;
|
||||||
; Addr[5] ; 6 ;
|
; Addr[5] ; 6 ;
|
||||||
; lpm_counter:Ref_rtl_0|dffs[3] ; 6 ;
|
; lpm_counter:Ref_rtl_0|dffs[1] ; 6 ;
|
||||||
; lpm_counter:Ref_rtl_0|dffs[2] ; 6 ;
|
|
||||||
; lpm_counter:Ref_rtl_0|dffs[0] ; 6 ;
|
|
||||||
; Addr[6] ; 5 ;
|
; Addr[6] ; 5 ;
|
||||||
|
; Addr[21] ; 5 ;
|
||||||
; Addr[14] ; 5 ;
|
; Addr[14] ; 5 ;
|
||||||
; Addr[20] ; 5 ;
|
|
||||||
; Bank[3] ; 5 ;
|
; Bank[3] ; 5 ;
|
||||||
; lpm_counter:Ref_rtl_0|dffs[1] ; 5 ;
|
|
||||||
; PHI1b9_MC ; 5 ;
|
; PHI1b9_MC ; 5 ;
|
||||||
; Addr[15] ; 4 ;
|
; Addr[15] ; 4 ;
|
||||||
; Addr[7] ; 4 ;
|
; Addr[7] ; 4 ;
|
||||||
; Addr[22] ; 4 ;
|
|
||||||
; Addr[21] ; 4 ;
|
|
||||||
; Bank[4] ; 4 ;
|
; Bank[4] ; 4 ;
|
||||||
; Bank[5] ; 3 ;
|
; Bank[5] ; 3 ;
|
||||||
; IOROMEN ; 3 ;
|
; IOROMEN ; 3 ;
|
||||||
|
|
@ -447,8 +459,8 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; PHI1reg ; 3 ;
|
; PHI1reg ; 3 ;
|
||||||
; PHI1in ; 2 ;
|
; PHI1in ; 2 ;
|
||||||
; C7M_2 ; 2 ;
|
; C7M_2 ; 2 ;
|
||||||
|
; Addr[23] ; 2 ;
|
||||||
; Bank[6] ; 2 ;
|
; Bank[6] ; 2 ;
|
||||||
; CASr ; 2 ;
|
|
||||||
; CASf ; 2 ;
|
; CASf ; 2 ;
|
||||||
; RD[7]~7 ; 1 ;
|
; RD[7]~7 ; 1 ;
|
||||||
; RD[6]~6 ; 1 ;
|
; RD[6]~6 ; 1 ;
|
||||||
|
|
@ -465,7 +477,6 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; A[6] ; 1 ;
|
; A[6] ; 1 ;
|
||||||
; A[5] ; 1 ;
|
; A[5] ; 1 ;
|
||||||
; A[4] ; 1 ;
|
; A[4] ; 1 ;
|
||||||
; nMode ; 1 ;
|
|
||||||
; ~VCC~0 ; 1 ;
|
; ~VCC~0 ; 1 ;
|
||||||
; RA~120 ; 1 ;
|
; RA~120 ; 1 ;
|
||||||
; RA~108 ; 1 ;
|
; RA~108 ; 1 ;
|
||||||
|
|
@ -476,16 +487,19 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; RA~79 ; 1 ;
|
; RA~79 ; 1 ;
|
||||||
; RA~73 ; 1 ;
|
; RA~73 ; 1 ;
|
||||||
; Bank[7] ; 1 ;
|
; Bank[7] ; 1 ;
|
||||||
|
; IncAddrH~9 ; 1 ;
|
||||||
; IncAddrM~9 ; 1 ;
|
; IncAddrM~9 ; 1 ;
|
||||||
; comb~38 ; 1 ;
|
; comb~38 ; 1 ;
|
||||||
; comb~34 ; 1 ;
|
; comb~34 ; 1 ;
|
||||||
|
; CAS1r ; 1 ;
|
||||||
|
; CAS0r ; 1 ;
|
||||||
; RA~68 ; 1 ;
|
; RA~68 ; 1 ;
|
||||||
; RA~65 ; 1 ;
|
; RA~65 ; 1 ;
|
||||||
; RA~62 ; 1 ;
|
; RA~62 ; 1 ;
|
||||||
; comb~31 ; 1 ;
|
; comb~31 ; 1 ;
|
||||||
; RASf ; 1 ;
|
; RASf ; 1 ;
|
||||||
; comb~29 ; 1 ;
|
|
||||||
; RASr ; 1 ;
|
; RASr ; 1 ;
|
||||||
|
; comb~29 ; 1 ;
|
||||||
; PHI1b8_MC ; 1 ;
|
; PHI1b8_MC ; 1 ;
|
||||||
; PHI1b7_MC ; 1 ;
|
; PHI1b7_MC ; 1 ;
|
||||||
; PHI1b6_MC ; 1 ;
|
; PHI1b6_MC ; 1 ;
|
||||||
|
|
@ -522,15 +536,15 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; Other Routing Resource Type ; Usage ;
|
; Other Routing Resource Type ; Usage ;
|
||||||
+-----------------------------+--------------------+
|
+-----------------------------+--------------------+
|
||||||
; Output enables ; 2 / 6 ( 33 % ) ;
|
; Output enables ; 2 / 6 ( 33 % ) ;
|
||||||
; PIA buffers ; 208 / 288 ( 72 % ) ;
|
; PIA buffers ; 211 / 288 ( 73 % ) ;
|
||||||
; PIAs ; 246 / 288 ( 85 % ) ;
|
; PIAs ; 249 / 288 ( 86 % ) ;
|
||||||
+-----------------------------+--------------------+
|
+-----------------------------+--------------------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------+
|
||||||
; LAB External Interconnect ;
|
; LAB External Interconnect ;
|
||||||
+-----------------------------------------------+-----------------------------+
|
+-----------------------------------------------+-----------------------------+
|
||||||
; LAB External Interconnects (Average = 30.75) ; Number of LABs (Total = 8) ;
|
; LAB External Interconnects (Average = 31.13) ; Number of LABs (Total = 8) ;
|
||||||
+-----------------------------------------------+-----------------------------+
|
+-----------------------------------------------+-----------------------------+
|
||||||
; 0 - 2 ; 0 ;
|
; 0 - 2 ; 0 ;
|
||||||
; 3 - 5 ; 0 ;
|
; 3 - 5 ; 0 ;
|
||||||
|
|
@ -541,8 +555,8 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; 18 - 20 ; 0 ;
|
; 18 - 20 ; 0 ;
|
||||||
; 21 - 23 ; 0 ;
|
; 21 - 23 ; 0 ;
|
||||||
; 24 - 26 ; 0 ;
|
; 24 - 26 ; 0 ;
|
||||||
; 27 - 29 ; 2 ;
|
; 27 - 29 ; 1 ;
|
||||||
; 30 - 32 ; 5 ;
|
; 30 - 32 ; 6 ;
|
||||||
; 33 - 35 ; 1 ;
|
; 33 - 35 ; 1 ;
|
||||||
+-----------------------------------------------+-----------------------------+
|
+-----------------------------------------------+-----------------------------+
|
||||||
|
|
||||||
|
|
@ -550,7 +564,7 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
+-----------------------------------------------------------------------+
|
+-----------------------------------------------------------------------+
|
||||||
; LAB Macrocells ;
|
; LAB Macrocells ;
|
||||||
+-----------------------------------------+-----------------------------+
|
+-----------------------------------------+-----------------------------+
|
||||||
; Number of Macrocells (Average = 12.88) ; Number of LABs (Total = 8) ;
|
; Number of Macrocells (Average = 13.13) ; Number of LABs (Total = 8) ;
|
||||||
+-----------------------------------------+-----------------------------+
|
+-----------------------------------------+-----------------------------+
|
||||||
; 0 ; 0 ;
|
; 0 ; 0 ;
|
||||||
; 1 ; 0 ;
|
; 1 ; 0 ;
|
||||||
|
|
@ -561,136 +575,138 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
; 6 ; 0 ;
|
; 6 ; 0 ;
|
||||||
; 7 ; 0 ;
|
; 7 ; 0 ;
|
||||||
; 8 ; 0 ;
|
; 8 ; 0 ;
|
||||||
; 9 ; 2 ;
|
; 9 ; 1 ;
|
||||||
; 10 ; 0 ;
|
; 10 ; 1 ;
|
||||||
; 11 ; 1 ;
|
; 11 ; 1 ;
|
||||||
; 12 ; 1 ;
|
; 12 ; 1 ;
|
||||||
; 13 ; 0 ;
|
; 13 ; 0 ;
|
||||||
; 14 ; 0 ;
|
; 14 ; 0 ;
|
||||||
; 15 ; 2 ;
|
; 15 ; 1 ;
|
||||||
; 16 ; 2 ;
|
; 16 ; 3 ;
|
||||||
+-----------------------------------------+-----------------------------+
|
+-----------------------------------------+-----------------------------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------+
|
||||||
; Shareable Expander ;
|
; Shareable Expander ;
|
||||||
+-------------------------------------------------+-----------------------------+
|
+-------------------------------------------------+-----------------------------+
|
||||||
; Number of shareable expanders (Average = 0.13) ; Number of LABs (Total = 1) ;
|
; Number of shareable expanders (Average = 0.25) ; Number of LABs (Total = 2) ;
|
||||||
+-------------------------------------------------+-----------------------------+
|
+-------------------------------------------------+-----------------------------+
|
||||||
; 0 ; 7 ;
|
; 0 ; 6 ;
|
||||||
; 1 ; 1 ;
|
; 1 ; 2 ;
|
||||||
+-------------------------------------------------+-----------------------------+
|
+-------------------------------------------------+-----------------------------+
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Logic Cell Interconnection ;
|
; Logic Cell Interconnection ;
|
||||||
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; LAB ; Logic Cell ; Input ; Output ;
|
; LAB ; Logic Cell ; Input ; Output ;
|
||||||
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[0], S[2], S[1], Addr[2], IncAddrL, Addr[1], Addr[0] ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~79 ;
|
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[1], S[2], S[0], Addr[11], IncAddrM, Addr[10], Addr[9], Addr[8] ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~73 ;
|
||||||
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[0], S[2], S[1], Addr[1], IncAddrL, Addr[0] ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~120 ;
|
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[2], S[1], S[0], Addr[7], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[7]~120, Addr[7], IncAddrM, RA~108 ;
|
||||||
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[2], S[1], S[0], Addr[15], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[7]~120, IncAddrH, Addr[15], RA~87 ;
|
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[2], S[1], S[0], Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~101 ;
|
||||||
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[0], S[2], S[1], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~73 ;
|
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[2], S[1], S[0], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ;
|
||||||
; A ; LC8 ; C7M, nRES, D[7], AddrLWR_MC, S[0], S[2], S[1], Addr[7], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[7]~120, Addr[7], IncAddrM, RA~108 ;
|
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[1], S[2], S[0], Addr[9], IncAddrM, Addr[8] ; Dout[1]~84, Addr[9], Addr[10], Addr[11], RA~65, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||||
; A ; LC7 ; C7M, nRES, D[6], AddrLWR_MC, S[0], S[2], S[1], Addr[6], IncAddrL, Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[6]~114, Addr[6], Addr[7], IncAddrM, RA~101 ;
|
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[2], S[1], S[0], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~87 ;
|
||||||
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[2], S[1], S[0], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[6]~114, Addr[14], IncAddrH, Addr[15], RA~80 ;
|
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[1], S[2], S[0], Addr[10], IncAddrM, Addr[9], Addr[8] ; Dout[2]~90, Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], RA~68, Addr[15], IncAddrH ;
|
||||||
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[2], S[1], S[0], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], RA~62, Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15] ;
|
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[1], S[2], S[0], Addr[12], IncAddrM, Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[4]~102, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH, RA~120 ;
|
||||||
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[2], S[1], S[0], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[5]~108, Addr[13], Addr[14], IncAddrH, Addr[15], RA~79 ;
|
; A ; LC14 ; C7M, nRES, D[5], AddrMWR_MC, S[1], S[2], S[0], Addr[13], IncAddrM, Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[5]~108, Addr[13], Addr[14], Addr[15], IncAddrH, RA~79 ;
|
||||||
; A ; LC13 ; C7M, nRES, D[4], AddrMWR_MC, S[2], S[1], S[0], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[4]~102, Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15], RA~120 ;
|
; A ; LC3 ; C7M, nRES, D[2], AddrLWR_MC, S[2], S[1], S[0], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[2]~90, Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~79 ;
|
||||||
; A ; LC12 ; C7M, nRES, D[3], AddrMWR_MC, S[2], S[1], S[0], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[3]~96, Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15], RA~73 ;
|
; A ; LC15 ; C7M, nRES, D[6], AddrMWR_MC, S[1], S[2], S[0], Addr[14], IncAddrM, Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[6]~114, Addr[14], Addr[15], IncAddrH, RA~80 ;
|
||||||
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[0], S[2], S[1], Addr[5], IncAddrL, Addr[4], Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~94 ;
|
; A ; LC9 ; C7M, nRES, D[0], AddrMWR_MC, S[1], S[2], S[0], Addr[8], IncAddrM ; Dout[0]~78, Addr[8], Addr[9], Addr[10], Addr[11], RA~62, Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||||
; A ; LC11 ; C7M, nRES, D[2], AddrMWR_MC, S[2], S[1], S[0], Addr[10], Addr[9], Addr[8], IncAddrM ; Dout[2]~90, Addr[10], Addr[11], Addr[12], RA~68, Addr[13], Addr[14], IncAddrH, Addr[15] ;
|
; A ; LC2 ; C7M, nRES, D[1], AddrLWR_MC, S[2], S[1], S[0], Addr[1], Addr[0], IncAddrL ; Dout[1]~84, Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~120 ;
|
||||||
; A ; LC5 ; C7M, nRES, D[4], AddrLWR_MC, S[0], S[2], S[1], Addr[4], IncAddrL, Addr[3], Addr[2], Addr[1], Addr[0] ; Dout[4]~102, Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~87 ;
|
; A ; LC16 ; C7M, nRES, D[7], AddrMWR_MC, S[1], S[2], S[0], Addr[15], IncAddrM, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8] ; Dout[7]~120, Addr[15], IncAddrH, RA~87 ;
|
||||||
; A ; LC10 ; C7M, nRES, D[1], AddrMWR_MC, S[2], S[1], S[0], Addr[9], Addr[8], IncAddrM ; Dout[1]~84, Addr[9], Addr[10], Addr[11], Addr[12], RA~65, Addr[13], Addr[14], IncAddrH, Addr[15] ;
|
; A ; LC1 ; C7M, nRES, D[0], AddrLWR_MC, S[2], S[1], S[0], Addr[0], IncAddrL ; Dout[0]~78, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~73 ;
|
||||||
; A ; LC4 ; C7M, nRES, D[3], AddrLWR_MC, S[0], S[2], S[1], Addr[3], IncAddrL, Addr[2], Addr[1], Addr[0] ; Dout[3]~96, Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM, RA~80 ;
|
; A ; LC6 ; C7M, nRES, D[5], AddrLWR_MC, S[2], S[1], S[0], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrL ; Dout[5]~108, Addr[5], Addr[6], Addr[7], IncAddrM, RA~94 ;
|
||||||
; B ; LC22 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[0], S[1], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~68, Addr[22] ;
|
; B ; LC17 ; ; nINH ;
|
||||||
; B ; LC30 ; C7M, nRES, D[5], BankWR_MC, S[2], S[1], S[0] ; RA~94, RA~101, RA~108 ;
|
; B ; LC18 ; C7M, nRES, D[7], BankWR_MC, S[0], S[2], S[1] ; RA~108 ;
|
||||||
; B ; LC24 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[0], S[1], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], comb~34, comb~38 ;
|
; B ; LC32 ; C7M, nRES, D[7], AddrHWR_MC, S[2], S[1], S[0], Addr[23], IncAddrH, Addr[22], Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[7]~120, Addr[23] ;
|
||||||
; B ; LC18 ; C7M, nRES, D[6], BankWR_MC, S[2], S[1], S[0] ; RA~101, RA~108 ;
|
; B ; LC26 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[1], S[0], IncAddrM, IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrM, Addr[15], IncAddrH~9, IncAddrH ;
|
||||||
; B ; LC17 ; ; nINH ;
|
; B ; LC28 ; C7M, nRES, D[6], BankWR_MC, S[0], S[2], S[1] ; RA~101, RA~108 ;
|
||||||
; B ; LC31 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~29 ;
|
; B ; LC24 ; C7M, nRES, D[6], AddrHWR_MC, S[2], S[1], S[0], Addr[22], IncAddrH, Addr[21], Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[6]~114, Addr[22], CAS0r, CAS1r, comb~34, comb~38, Addr[23] ;
|
||||||
; B ; LC26 ; C7M, nRES, D[7], AddrLWR_MC, Addr[7], S[2], S[0], S[1], IncAddrL, Addr[6], Addr[5], Addr[4], Addr[3], Addr[2], Addr[1], Addr[0], IncAddrM, IncAddrM~9 ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, IncAddrM, Addr[15] ;
|
; B ; LC29 ; C7M, nRES, D[5], AddrHWR_MC, S[2], S[1], S[0], Addr[21], IncAddrH, Addr[20], Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[5]~108, Addr[21], RA~68, Addr[22], Addr[23] ;
|
||||||
; B ; LC32 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[0], S[1], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~101 ;
|
; B ; LC19 ; C7M, nRES, D[5], BankWR_MC, S[0], S[2], S[1] ; RA~94, RA~101, RA~108 ;
|
||||||
; B ; LC20 ; C7M, nRES, D[2], BankWR_MC, S[2], S[1], S[0] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108 ;
|
; B ; LC22 ; C7M, nRES, D[4], BankWR_MC, S[0], S[2], S[1] ; RA~87, RA~94, RA~101, RA~108 ;
|
||||||
; B ; LC23 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[0], S[1], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~108 ;
|
; B ; LC27 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[1], S[0], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~62, Addr[20], Addr[21], Addr[22], Addr[23] ;
|
||||||
; B ; LC25 ; C7M, nRES, D[3], AddrHWR_MC, S[2], S[0], S[1], Addr[19], IncAddrH, Addr[18], Addr[17], Addr[16] ; Dout[3]~96, Addr[19], RA~62, Addr[20], Addr[21], Addr[22] ;
|
; B ; LC30 ; C7M, nRES, D[3], BankWR_MC, S[0], S[2], S[1] ; RA~80, RA~87, RA~94, RA~101, RA~108 ;
|
||||||
; B ; LC21 ; C7M, nRES, D[3], BankWR_MC, S[2], S[1], S[0] ; RA~80, RA~87, RA~94, RA~101, RA~108 ;
|
; B ; LC21 ; C7M, nRES, D[1], AddrHWR_MC, S[2], S[1], S[0], Addr[17], IncAddrH, Addr[16] ; Dout[1]~84, Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~101 ;
|
||||||
; B ; LC19 ; C7M, nRES, D[1], BankWR_MC, S[2], S[1], S[0] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
; B ; LC23 ; C7M, nRES, D[2], BankWR_MC, S[0], S[2], S[1] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108 ;
|
||||||
; B ; LC27 ; C7M, nRES, D[4], BankWR_MC, S[2], S[1], S[0] ; RA~87, RA~94, RA~101, RA~108 ;
|
; B ; LC31 ; C7M, nRES, D[2], AddrHWR_MC, S[2], S[1], S[0], Addr[18], IncAddrH, Addr[17], Addr[16] ; Dout[2]~90, Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~108 ;
|
||||||
; B ; LC29 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[0], S[1], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~65, Addr[21], Addr[22] ;
|
; B ; LC20 ; C7M, nRES, D[1], BankWR_MC, S[0], S[2], S[1] ; RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
||||||
; C ; LC38 ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4] ; D[4] ;
|
; B ; LC25 ; C7M, nRES, D[4], AddrHWR_MC, S[2], S[1], S[0], Addr[20], IncAddrH, Addr[19], Addr[18], Addr[17], Addr[16] ; Dout[4]~102, Addr[20], RA~65, Addr[21], Addr[22], Addr[23] ;
|
||||||
; C ; LC40 ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5] ; D[5] ;
|
; C ; LC33 ; PHI1b4_MC ; PHI1b6_MC ;
|
||||||
; C ; LC43 ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6] ; D[6] ;
|
; C ; LC42 ; PHI1b2_MC ; PHI1b4_MC ;
|
||||||
; C ; LC45 ; RD[7], nDEVSEL, A[0], A[1], A[2], A[3], Addr[15], nMode, Addr[7] ; D[7] ;
|
; C ; LC34 ; PHI1b5_MC ; PHI1b7_MC ;
|
||||||
; C ; LC41 ; C7M, nRES, nIOSEL, S[2], S[1], S[0] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN ;
|
; C ; LC47 ; C7M, nRES, D[0], AddrHWR_MC, S[2], S[1], S[0], Addr[16], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23], RA~94 ;
|
||||||
; C ; LC35 ; PHI1b1_MC ; PHI1b3_MC ;
|
; C ; LC38 ; RD[4], nDEVSEL, A[0], A[1], A[2], A[3], Addr[12], Addr[20], Addr[4] ; D[4] ;
|
||||||
; C ; LC47 ; C7M, nRES, D[0], AddrHWR_MC, S[1], S[2], S[0], Addr[16], IncAddrH ; Dout[0]~78, Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], RA~94 ;
|
; C ; LC36 ; C7M, nRES, S[0], nIOSEL, S[2], S[1] ; DOE~5, RAMSEL_MC, AddrHWR_MC, AddrMWR_MC, AddrLWR_MC, BankWR_MC, FullIOEN ;
|
||||||
; C ; LC36 ; C7M, nRES, D[7], BankWR_MC, S[2], S[1], S[0] ; RA~108 ;
|
; C ; LC45 ; RD[7], nDEVSEL, A[0], A[1], A[2], A[3], Addr[15], Addr[23], Addr[7] ; D[7] ;
|
||||||
; C ; LC34 ; C7M, nRES, D[0], BankWR_MC, S[2], S[1], S[0] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
; C ; LC43 ; RD[6], nDEVSEL, A[0], A[1], A[2], A[3], Addr[14], Addr[22], Addr[6] ; D[6] ;
|
||||||
; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ;
|
; C ; LC35 ; PHI1b1_MC ; PHI1b3_MC ;
|
||||||
; D ; LC56 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
|
; C ; LC40 ; RD[5], nDEVSEL, A[0], A[1], A[2], A[3], Addr[13], Addr[21], Addr[5] ; D[5] ;
|
||||||
; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ;
|
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
|
||||||
; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ;
|
; D ; LC59 ; RD[1], nDEVSEL, A[0], A[1], A[2], A[3], Addr[9], Addr[17], Addr[1] ; D[1] ;
|
||||||
; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ;
|
; D ; LC61 ; RD[2], nDEVSEL, A[0], A[1], A[2], A[3], Addr[10], Addr[18], Addr[2] ; D[2] ;
|
||||||
; D ; LC49 ; CSDBEN, nIOSEL, IOROMEN, nIOSTRB ; nRCS ;
|
; D ; LC64 ; RD[3], nDEVSEL, A[0], A[1], A[2], A[3], Addr[11], Addr[19], Addr[3] ; D[3] ;
|
||||||
; D ; LC51 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS1 ;
|
; D ; LC57 ; RD[0], nDEVSEL, A[0], A[1], A[2], A[3], Addr[8], Addr[16], Addr[0] ; D[0] ;
|
||||||
; D ; LC53 ; Addr[22], CASf, RAMSEL_MC, CASr ; nCAS0 ;
|
; D ; LC53 ; Addr[22], CASf, RAMSEL_MC, CAS0r ; nCAS0 ;
|
||||||
; D ; LC52 ; PHI1in ; PHI1b1_MC ;
|
; D ; LC51 ; Addr[22], CASf, RAMSEL_MC, CAS1r ; nCAS1 ;
|
||||||
; D ; LC50 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ;
|
; D ; LC50 ; PHI1b0_MC ; PHI1b2_MC ;
|
||||||
; D ; LC54 ; PHI1b0_MC ; PHI1b2_MC ;
|
; D ; LC54 ; C7M, nRES, S[2] ; DOE~5, RDOE~1, comb~29 ;
|
||||||
; E ; LC67 ; nWE ; nROE ;
|
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
|
||||||
; E ; LC77 ; FullIOEN, Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[16], ASel, nIOSEL, Addr[5], Bank[5] ; RA[5] ;
|
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
|
||||||
; E ; LC66 ; PHI1b6_MC ; PHI1b8_MC ;
|
; E ; LC74 ; C7M, nRES, S[0], RAMSEL_MC, S[2], S[1] ; comb~31 ;
|
||||||
; E ; LC70 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
; E ; LC79 ; C7M, nRES, IncAddrL, S[0], S[1], RAMSEL_MC, S[2] ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
|
||||||
; E ; LC71 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
; E ; LC65 ; PHI1b6_MC ; PHI1b8_MC ;
|
||||||
; E ; LC65 ; PHI1b7_MC ; PHI1b9_MC ;
|
; E ; LC68 ; C7M, nRES, RAMSEL_MC, S[2], S[1] ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
||||||
; E ; LC76 ; C7M, nRES, S[1], S[2], RAMSEL_MC ; RA~62, RA~65, RA~68, RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
|
||||||
; E ; LC69 ; Addr[20], ASel, Addr[9] ; RA[9] ;
|
; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
|
||||||
; E ; LC72 ; Addr[21], ASel, Addr[10] ; RA[10] ;
|
; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
|
||||||
; E ; LC80 ; Bank[0], FullIOEN, nIOSTRB, Addr[11], ASel, nIOSEL, Addr[0] ; RA[0] ;
|
; E ; LC71 ; PHI1b7_MC ; PHI1b9_MC ;
|
||||||
; E ; LC75 ; FullIOEN, Bank[2], Bank[1], nIOSTRB, Bank[0], Addr[13], ASel, nIOSEL, Addr[2] ; RA[2] ;
|
; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
|
||||||
; E ; LC73 ; FullIOEN, Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[14], ASel, nIOSEL, Addr[3], Bank[3] ; RA[3] ;
|
; E ; LC67 ; nWE ; nROE ;
|
||||||
; F ; LC94 ; D[7] ; RD[7] ;
|
; F ; LC90 ; C7M, nRES, D[0], BankWR_MC, S[0], S[2], S[1] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
||||||
; F ; LC87 ; C7M, nRES, RAMSEL_MC, S[2], S[1], S[0] ; comb~31 ;
|
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
|
||||||
; F ; LC92 ; C7M, nRES, RAMSEL_MC, S[0], S[2], S[1], IncAddrL ; IncAddrL, Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM~9, IncAddrM ;
|
; F ; LC93 ; RASr, RASf ; nRAS ;
|
||||||
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
|
; F ; LC91 ; Addr[19], ASel, Addr[8] ; RA[8] ;
|
||||||
; F ; LC93 ; RASr, RASf ; nRAS ;
|
; F ; LC89 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
||||||
; F ; LC85 ; FullIOEN, Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[15], ASel, nIOSEL, Addr[4], Bank[4] ; RA[4] ;
|
; F ; LC87 ; C7M, nRES, PHI1b9_MC ; S[0], S[1], S[2] ;
|
||||||
; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
|
; F ; LC81 ; PHI1b3_MC ; PHI1b5_MC ;
|
||||||
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
|
; F ; LC94 ; D[7] ; RD[7] ;
|
||||||
; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
|
; F ; LC88 ; FullIOEN, Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[17], ASel, nIOSEL, Addr[6], Bank[6] ; RA[6] ;
|
||||||
; G ; LC112 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
|
; F ; LC86 ; FullIOEN, Bank[6], Bank[5], Bank[4], Bank[3], Bank[2], Bank[1], Bank[0], nIOSTRB, Addr[18], ASel, nIOSEL, Addr[7], Bank[7] ; RA[7] ;
|
||||||
; G ; LC109 ; D[1] ; RD[1] ;
|
; F ; LC83 ; Addr[12], ASel, nIOSEL, nIOSTRB, Addr[1], FullIOEN, Bank[1], Bank[0] ; RA[1] ;
|
||||||
; G ; LC105 ; D[3] ; RD[3] ;
|
; G ; LC103 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], Addr[15], IncAddrH ;
|
||||||
; G ; LC101 ; D[4] ; RD[4] ;
|
; G ; LC111 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], Addr[23] ;
|
||||||
; G ; LC97 ; D[5] ; RD[5] ;
|
; G ; LC108 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; ASel, IncAddrL, RASr, RASf, CAS0r, CAS1r, comb~34, comb~38 ;
|
||||||
; G ; LC99 ; D[6] ; RD[6] ;
|
; G ; LC110 ; C7M, nRES, S[0], nIOSEL, S[2], S[1], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~29 ;
|
||||||
; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ;
|
; G ; LC112 ; REGEN, nDEVSEL, CSDBEN, nWE, nIOSEL, IOROMEN, nIOSTRB ; D[0], D[1], D[2], D[3], D[4], D[5], D[6], D[7] ;
|
||||||
; G ; LC100 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[8], Addr[9], Addr[10], Addr[11], Addr[12], Addr[13], Addr[14], IncAddrH, Addr[15] ;
|
; G ; LC105 ; D[3] ; RD[3] ;
|
||||||
; G ; LC108 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
|
; G ; LC104 ; nDEVSEL, nIOSEL, nIOSTRB, nWE ; nRWE ;
|
||||||
; G ; LC102 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[2], S[1], S[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
; G ; LC99 ; D[6] ; RD[6] ;
|
||||||
; G ; LC106 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
|
; G ; LC97 ; D[5] ; RD[5] ;
|
||||||
; G ; LC107 ; D[2] ; RD[2] ;
|
; G ; LC101 ; D[4] ; RD[4] ;
|
||||||
; G ; LC98 ; C7M, nRES, nIOSEL, S[2], S[1], S[0], IOROMEN, A[0], A[4], A[5], A[6], A[7], A[8], A[9], A[10], nIOSTRB, A[1], A[2], A[3] ; DOE~5, IOROMEN, comb~29 ;
|
; G ; LC98 ; C7M, nRES, D[7], D[6], D[5], D[4], D[3], D[2], D[1], D[0], A[0], S[0], S[2], S[1], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; RA~73, RA~79, RA~80, RA~87, RA~94, RA~101, RA~108, RA~120 ;
|
||||||
; G ; LC111 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22] ;
|
; G ; LC107 ; D[2] ; RD[2] ;
|
||||||
; G ; LC110 ; REGEN, nDEVSEL, A[1], A[0], A[2], A[3] ; RASr, IncAddrL, ASel, CASr, RASf, comb~34, comb~38 ;
|
; G ; LC109 ; D[1] ; RD[1] ;
|
||||||
; H ; LC123 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[2], S[1], S[0] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], Bank[7], FullIOEN ;
|
; G ; LC102 ; A[0], nWE, REGEN, nDEVSEL, A[1], A[2], A[3] ; Bank[0], Bank[1], Bank[2], Bank[3], Bank[4], Bank[5], Bank[6], Bank[7] ;
|
||||||
; H ; LC120 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
|
; G ; LC106 ; A[1], A[0], A[2], A[3], nWE, REGEN, nDEVSEL ; Addr[0], Addr[1], Addr[2], Addr[3], Addr[4], Addr[5], Addr[6], Addr[7], IncAddrM ;
|
||||||
; H ; LC122 ; nRES, S[2], S[1], S[0], nWE, C7M_2 ; comb~34, comb~38 ;
|
; H ; LC117 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, CASf, lpm_counter:Ref_rtl_0|dffs[1], ASel, IncAddrL, RASr, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASf, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0r, CAS1r, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH~9, IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||||
; H ; LC128 ; PHI1b3_MC ; PHI1b5_MC ;
|
; H ; LC122 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[2], S[1] ; S[0], S[1], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, CASf, lpm_counter:Ref_rtl_0|dffs[1], IncAddrL, RASr, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASf, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0r, CAS1r, Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||||
; H ; LC127 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[1], S[2], S[0] ; S[0], S[1], S[2], CSDBEN, CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], Bank[7], FullIOEN ;
|
; H ; LC128 ; nRES, S[2], S[1], nWE, S[0], C7M_2 ; comb~34, comb~38 ;
|
||||||
; H ; LC116 ; PHI1b5_MC ; PHI1b7_MC ;
|
; H ; LC113 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASf, CAS0r, CAS1r ;
|
||||||
; H ; LC125 ; PHI1b4_MC ; PHI1b6_MC ;
|
; H ; LC123 ; PHI1in, PHI1b8_MC ; PHI1reg, PHI0seen, S[0], S[1], S[2] ;
|
||||||
; H ; LC119 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
|
; H ; LC126 ; C7M, nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], Addr[22], RAMSEL_MC ; comb~34 ;
|
||||||
; H ; LC124 ; C7M, nRES, S[1], S[0], S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], RAMSEL_MC ; comb~34, comb~38 ;
|
; H ; LC125 ; C7M, nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], Addr[22], RAMSEL_MC ; comb~38 ;
|
||||||
; H ; LC121 ; nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], RAMSEL_MC, C7M_2 ; comb~31 ;
|
; H ; LC116 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASf, CAS0r, CAS1r ;
|
||||||
; H ; LC118 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
|
; H ; LC118 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASf, CAS0r, CAS1r ;
|
||||||
; H ; LC114 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[1], S[2], S[0], IncAddrH, Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], IncAddrH, Addr[22] ;
|
; H ; LC119 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], RASf, CAS0r, CAS1r ;
|
||||||
; H ; LC115 ; D[0] ; RD[0] ;
|
; H ; LC120 ; CSDBEN, nWE ; RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7] ;
|
||||||
; H ; LC117 ; PHI1b2_MC ; PHI1b4_MC ;
|
; H ; LC115 ; D[0] ; RD[0] ;
|
||||||
; H ; LC113 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[2], S[1], S[0] ; S[0], S[1], S[2], CASf, lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, lpm_counter:Ref_rtl_0|dffs[1], RASr, IncAddrL, ASel, lpm_counter:Ref_rtl_0|dffs[2], Addr[8], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], CASr, RASf, Addr[1], Bank[0], Addr[16], Addr[2], Addr[17], Addr[3], Bank[1], Addr[9], Addr[4], Addr[10], Addr[5], Bank[2], Addr[18], Addr[19], Bank[3], Addr[11], Addr[12], Bank[4], Addr[20], Addr[21], Bank[5], Addr[13], Addr[14], IncAddrH, Addr[22], Bank[6], Addr[6], Addr[7], IncAddrM, Addr[15], Bank[7], FullIOEN ;
|
; H ; LC121 ; nRES, S[2], lpm_counter:Ref_rtl_0|dffs[3], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], S[1], S[0], RAMSEL_MC, C7M_2 ; comb~31 ;
|
||||||
; H ; LC126 ; C7M, nRES, lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], S[2], S[1], S[0] ; lpm_counter:Ref_rtl_0|dffs[0], lpm_counter:Ref_rtl_0|dffs[1], lpm_counter:Ref_rtl_0|dffs[2], lpm_counter:Ref_rtl_0|dffs[3], CASr, RASf ;
|
; H ; LC124 ; C7M, nRES, PHI1reg, PHI0seen, PHI1b9_MC, S[0], S[1], S[2] ; S[0], S[1], S[2], lpm_counter:Ref_rtl_0|dffs[0], REGEN, IOROMEN, CASf, lpm_counter:Ref_rtl_0|dffs[1], ASel, IncAddrL, RASr, lpm_counter:Ref_rtl_0|dffs[2], Addr[16], lpm_counter:Ref_rtl_0|dffs[3], Addr[0], RASf, Addr[1], Bank[0], Addr[8], Addr[2], Addr[9], Addr[3], Bank[1], Addr[17], Addr[4], Addr[18], Addr[5], Bank[2], Addr[10], Addr[11], Bank[3], Addr[19], Addr[20], Bank[4], Addr[12], Addr[13], Addr[14], Bank[5], Addr[21], Addr[22], CAS0r, CAS1r, Bank[6], Addr[6], Addr[7], IncAddrM~9, IncAddrM, Addr[15], IncAddrH~9, IncAddrH, Addr[23], Bank[7], FullIOEN ;
|
||||||
+-----+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
; H ; LC127 ; PHI1in ; PHI1b1_MC ;
|
||||||
|
; H ; LC114 ; C7M, nRES, D[7], AddrMWR_MC, Addr[15], S[2], S[0], S[1], Addr[14], Addr[13], Addr[12], Addr[11], Addr[10], Addr[9], Addr[8], IncAddrM, IncAddrH~9, IncAddrH ; Addr[16], Addr[17], Addr[18], Addr[19], Addr[20], Addr[21], Addr[22], IncAddrH, Addr[23] ;
|
||||||
|
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------+
|
+---------------------------------------------------------------+
|
||||||
|
|
@ -713,12 +729,10 @@ Note: User assignments will override these defaults. The user specified values a
|
||||||
+-----------------+
|
+-----------------+
|
||||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||||
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
|
Info (119006): Selected device EPM7128SLC84-15 for design "GR8RAM"
|
||||||
Warning (15705): Ignored locations or region assignments to the following nodes
|
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 1 warning
|
||||||
Warning (15706): Node "MODE" is assigned to location or region, but does not exist in design
|
Info: Peak virtual memory: 4708 megabytes
|
||||||
Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings
|
Info: Processing ended: Sat Sep 07 22:26:04 2019
|
||||||
Info: Peak virtual memory: 287 megabytes
|
Info: Elapsed time: 00:00:00
|
||||||
Info: Processing ended: Sat Sep 07 21:15:38 2019
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
Info: Elapsed time: 00:00:05
|
|
||||||
Info: Total CPU time (on all processors): 00:00:05
|
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,9 +1,9 @@
|
||||||
Fitter Status : Successful - Sat Sep 07 21:15:37 2019
|
Fitter Status : Successful - Sat Sep 07 22:26:04 2019
|
||||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||||
Revision Name : GR8RAM
|
Revision Name : GR8RAM
|
||||||
Top-level Entity Name : GR8RAM
|
Top-level Entity Name : GR8RAM
|
||||||
Family : MAX7000S
|
Family : MAX7000S
|
||||||
Device : EPM7128SLC84-15
|
Device : EPM7128SLC84-15
|
||||||
Timing Models : Final
|
Timing Models : Final
|
||||||
Total macrocells : 103 / 128 ( 80 % )
|
Total macrocells : 105 / 128 ( 82 % )
|
||||||
Total pins : 65 / 68 ( 96 % )
|
Total pins : 65 / 68 ( 96 % )
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
Flow report for GR8RAM
|
Flow report for GR8RAM
|
||||||
Sat Sep 07 21:15:48 2019
|
Sat Sep 07 22:26:09 2019
|
||||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
|
@ -40,14 +40,14 @@ applicable agreement for further details.
|
||||||
+-----------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------+
|
||||||
; Flow Summary ;
|
; Flow Summary ;
|
||||||
+---------------------------+-------------------------------------------------+
|
+---------------------------+-------------------------------------------------+
|
||||||
; Flow Status ; Successful - Sat Sep 07 21:15:42 2019 ;
|
; Flow Status ; Successful - Sat Sep 07 22:26:07 2019 ;
|
||||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX7000S ;
|
; Family ; MAX7000S ;
|
||||||
; Device ; EPM7128SLC84-15 ;
|
; Device ; EPM7128SLC84-15 ;
|
||||||
; Timing Models ; Final ;
|
; Timing Models ; Final ;
|
||||||
; Total macrocells ; 103 / 128 ( 80 % ) ;
|
; Total macrocells ; 105 / 128 ( 82 % ) ;
|
||||||
; Total pins ; 65 / 68 ( 96 % ) ;
|
; Total pins ; 65 / 68 ( 96 % ) ;
|
||||||
+---------------------------+-------------------------------------------------+
|
+---------------------------+-------------------------------------------------+
|
||||||
|
|
||||||
|
|
@ -57,40 +57,40 @@ applicable agreement for further details.
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Option ; Setting ;
|
; Option ; Setting ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
; Start date & time ; 09/07/2019 21:15:27 ;
|
; Start date & time ; 09/07/2019 22:26:03 ;
|
||||||
; Main task ; Compilation ;
|
; Main task ; Compilation ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
+-------------------+---------------------+
|
+-------------------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
+---------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Flow Non-Default Global Settings ;
|
; Flow Non-Default Global Settings ;
|
||||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
|
||||||
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
|
; AUTO_LCELL_INSERTION ; Off ; On ; -- ; -- ;
|
||||||
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
|
; AUTO_PARALLEL_EXPANDERS ; Off ; On ; -- ; -- ;
|
||||||
; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ;
|
; AUTO_TURBO_BIT ; Off ; On ; -- ; -- ;
|
||||||
; COMPILER_SIGNATURE_ID ; 52238299365.156790532703820 ; -- ; -- ; -- ;
|
; COMPILER_SIGNATURE_ID ; 207120313862967.156790956319700 ; -- ; -- ; -- ;
|
||||||
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
|
; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
|
||||||
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
|
; ECO_REGENERATE_REPORT ; On ; Off ; -- ; -- ;
|
||||||
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
; EXTRACT_VERILOG_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
||||||
; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
; EXTRACT_VHDL_STATE_MACHINES ; Off ; On ; -- ; -- ;
|
||||||
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
|
||||||
; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ;
|
; MAX7000_IGNORE_LCELL_BUFFERS ; Off ; Auto ; -- ; -- ;
|
||||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||||
; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ;
|
; OPTIMIZE_HOLD_TIMING ; Off ; -- ; -- ; -- ;
|
||||||
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
|
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
|
||||||
; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
|
; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
|
||||||
; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ;
|
; PRE_MAPPING_RESYNTHESIS ; On ; Off ; -- ; -- ;
|
||||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||||
; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ;
|
; SLOW_SLEW_RATE ; On ; Off ; -- ; -- ;
|
||||||
; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ;
|
; STATE_MACHINE_PROCESSING ; User-Encoded ; Auto ; -- ; -- ;
|
||||||
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
|
; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
|
||||||
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
|
; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
|
||||||
+--------------------------------------------+-----------------------------+---------------+-------------+------------+
|
+--------------------------------------------+---------------------------------+---------------+-------------+------------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
||||||
|
|
@ -98,24 +98,24 @@ applicable agreement for further details.
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
; Analysis & Synthesis ; 00:00:08 ; 1.0 ; 304 MB ; 00:00:08 ;
|
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4587 MB ; 00:00:01 ;
|
||||||
; Fitter ; 00:00:04 ; 1.0 ; 287 MB ; 00:00:05 ;
|
; Fitter ; 00:00:00 ; 1.0 ; 4708 MB ; 00:00:00 ;
|
||||||
; Assembler ; 00:00:03 ; 1.0 ; 275 MB ; 00:00:02 ;
|
; Assembler ; 00:00:02 ; 1.0 ; 4521 MB ; 00:00:00 ;
|
||||||
; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 259 MB ; 00:00:05 ;
|
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4530 MB ; 00:00:01 ;
|
||||||
; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ;
|
; Total ; 00:00:04 ; -- ; -- ; 00:00:02 ;
|
||||||
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------------------------------------------+
|
+----------------------------------------------------------------------------------------+
|
||||||
; Flow OS Summary ;
|
; Flow OS Summary ;
|
||||||
+---------------------------+------------------+------------+------------+----------------+
|
+---------------------------+------------------+-----------+------------+----------------+
|
||||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||||
+---------------------------+------------------+------------+------------+----------------+
|
+---------------------------+------------------+-----------+------------+----------------+
|
||||||
; Analysis & Synthesis ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||||
; Fitter ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||||
; Assembler ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||||
; TimeQuest Timing Analyzer ; zane-f8c4ec68a5 ; Windows XP ; 5.1 ; i686 ;
|
; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
|
||||||
+---------------------------+------------------+------------+------------+----------------+
|
+---------------------------+------------------+-----------+------------+----------------+
|
||||||
|
|
||||||
|
|
||||||
------------
|
------------
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
<sld_project_info>
|
<sld_project_info>
|
||||||
<project>
|
<project>
|
||||||
<hash md5_digest_80b="c391878a634f7d9b75fb"/>
|
<hash md5_digest_80b="6a2adcbd90906bf1bee8"/>
|
||||||
</project>
|
</project>
|
||||||
<file_info>
|
<file_info>
|
||||||
<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>
|
<file device="EPM7128SLC84-15" path="GR8RAM.sof" usercode="0x00000000"/>
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
Analysis & Synthesis report for GR8RAM
|
Analysis & Synthesis report for GR8RAM
|
||||||
Sat Sep 07 21:15:31 2019
|
Sat Sep 07 22:26:03 2019
|
||||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
|
@ -9,16 +9,17 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
1. Legal Notice
|
1. Legal Notice
|
||||||
2. Analysis & Synthesis Summary
|
2. Analysis & Synthesis Summary
|
||||||
3. Analysis & Synthesis Settings
|
3. Analysis & Synthesis Settings
|
||||||
4. Analysis & Synthesis Source Files Read
|
4. Parallel Compilation
|
||||||
5. Analysis & Synthesis Resource Usage Summary
|
5. Analysis & Synthesis Source Files Read
|
||||||
6. Analysis & Synthesis Resource Utilization by Entity
|
6. Analysis & Synthesis Resource Usage Summary
|
||||||
7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
|
7. Analysis & Synthesis Resource Utilization by Entity
|
||||||
8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
|
8. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
|
||||||
9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4
|
9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
|
||||||
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
|
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4
|
||||||
11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5
|
11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
|
||||||
12. Analysis & Synthesis Messages
|
12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5
|
||||||
13. Analysis & Synthesis Suppressed Messages
|
13. Analysis & Synthesis Messages
|
||||||
|
14. Analysis & Synthesis Suppressed Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -44,12 +45,12 @@ applicable agreement for further details.
|
||||||
+-------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Summary ;
|
; Analysis & Synthesis Summary ;
|
||||||
+-----------------------------+-------------------------------------------------+
|
+-----------------------------+-------------------------------------------------+
|
||||||
; Analysis & Synthesis Status ; Successful - Sat Sep 07 21:15:31 2019 ;
|
; Analysis & Synthesis Status ; Successful - Sat Sep 07 22:26:03 2019 ;
|
||||||
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
|
||||||
; Revision Name ; GR8RAM ;
|
; Revision Name ; GR8RAM ;
|
||||||
; Top-level Entity Name ; GR8RAM ;
|
; Top-level Entity Name ; GR8RAM ;
|
||||||
; Family ; MAX7000S ;
|
; Family ; MAX7000S ;
|
||||||
; Total macrocells ; 103 ;
|
; Total macrocells ; 105 ;
|
||||||
; Total pins ; 61 ;
|
; Total pins ; 61 ;
|
||||||
+-----------------------------+-------------------------------------------------+
|
+-----------------------------+-------------------------------------------------+
|
||||||
|
|
||||||
|
|
@ -118,12 +119,23 @@ applicable agreement for further details.
|
||||||
+----------------------------------------------------------------------------+-----------------+---------------+
|
+----------------------------------------------------------------------------+-----------------+---------------+
|
||||||
|
|
||||||
|
|
||||||
|
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||||
|
+-------------------------------------+
|
||||||
|
; Parallel Compilation ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
; Processors ; Number ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
; Number detected on machine ; 8 ;
|
||||||
|
; Maximum allowed ; 1 ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
|
||||||
|
|
||||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Analysis & Synthesis Source Files Read ;
|
; Analysis & Synthesis Source Files Read ;
|
||||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
|
||||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||||
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
|
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
|
||||||
; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
|
; GR8RAM.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/GR8RAM.v ; ;
|
||||||
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
|
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
|
||||||
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
|
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
|
||||||
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
|
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
|
||||||
|
|
@ -153,14 +165,14 @@ applicable agreement for further details.
|
||||||
+----------------------+----------------------+
|
+----------------------+----------------------+
|
||||||
; Resource ; Usage ;
|
; Resource ; Usage ;
|
||||||
+----------------------+----------------------+
|
+----------------------+----------------------+
|
||||||
; Logic cells ; 103 ;
|
; Logic cells ; 105 ;
|
||||||
; Total registers ; 52 ;
|
; Total registers ; 54 ;
|
||||||
; I/O pins ; 61 ;
|
; I/O pins ; 61 ;
|
||||||
; Shareable expanders ; 1 ;
|
; Shareable expanders ; 2 ;
|
||||||
; Maximum fan-out node ; nRES ;
|
; Maximum fan-out node ; S[2] ;
|
||||||
; Maximum fan-out ; 52 ;
|
; Maximum fan-out ; 54 ;
|
||||||
; Total fan-out ; 831 ;
|
; Total fan-out ; 862 ;
|
||||||
; Average fan-out ; 5.04 ;
|
; Average fan-out ; 5.13 ;
|
||||||
+----------------------+----------------------+
|
+----------------------+----------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -169,7 +181,7 @@ applicable agreement for further details.
|
||||||
+----------------------------+------------+------+-------------------------------+--------------+
|
+----------------------------+------------+------+-------------------------------+--------------+
|
||||||
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
|
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
|
||||||
+----------------------------+------------+------+-------------------------------+--------------+
|
+----------------------------+------------+------+-------------------------------+--------------+
|
||||||
; |GR8RAM ; 103 ; 61 ; |GR8RAM ; work ;
|
; |GR8RAM ; 105 ; 61 ; |GR8RAM ; work ;
|
||||||
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
|
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
|
||||||
+----------------------------+------------+------+-------------------------------+--------------+
|
+----------------------------+------------+------+-------------------------------+--------------+
|
||||||
|
|
||||||
|
|
@ -290,7 +302,7 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||||
+------------------------+-------------+----------------------------+
|
+------------------------+-------------+----------------------------+
|
||||||
; Parameter Name ; Value ; Type ;
|
; Parameter Name ; Value ; Type ;
|
||||||
+------------------------+-------------+----------------------------+
|
+------------------------+-------------+----------------------------+
|
||||||
; LPM_WIDTH ; 7 ; Untyped ;
|
; LPM_WIDTH ; 8 ; Untyped ;
|
||||||
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
|
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
|
||||||
; LPM_DIRECTION ; ADD ; Untyped ;
|
; LPM_DIRECTION ; ADD ; Untyped ;
|
||||||
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
|
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
|
||||||
|
|
@ -304,7 +316,7 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||||
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
|
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
|
||||||
; USE_WYS ; OFF ; Untyped ;
|
; USE_WYS ; OFF ; Untyped ;
|
||||||
; STYLE ; FAST ; Untyped ;
|
; STYLE ; FAST ; Untyped ;
|
||||||
; CBXI_PARAMETER ; add_sub_qnh ; Untyped ;
|
; CBXI_PARAMETER ; add_sub_rnh ; Untyped ;
|
||||||
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||||||
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||||||
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||||||
|
|
@ -317,20 +329,20 @@ Note: In order to hide this table in the UI and the text report file, please set
|
||||||
; Analysis & Synthesis Messages ;
|
; Analysis & Synthesis Messages ;
|
||||||
+-------------------------------+
|
+-------------------------------+
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus II 32-bit Analysis & Synthesis
|
Info: Running Quartus II 64-Bit Analysis & Synthesis
|
||||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
Info: Processing started: Sat Sep 07 21:15:23 2019
|
Info: Processing started: Sat Sep 07 22:26:02 2019
|
||||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
|
||||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||||
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
|
||||||
Info (12023): Found entity 1: GR8RAM
|
Info (12023): Found entity 1: GR8RAM
|
||||||
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(126): truncated value with size 32 to match size of target (3)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(133): truncated value with size 32 to match size of target (3)
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(131): truncated value with size 32 to match size of target (4)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (4)
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(163): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(159): truncated value with size 32 to match size of target (8)
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(168): truncated value with size 32 to match size of target (8)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(164): truncated value with size 32 to match size of target (8)
|
||||||
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(174): truncated value with size 32 to match size of target (7)
|
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(170): truncated value with size 32 to match size of target (8)
|
||||||
Info (19000): Inferred 1 megafunctions from design logic
|
Info (19000): Inferred 1 megafunctions from design logic
|
||||||
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
|
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
|
||||||
Info (278001): Inferred 4 megafunctions from design logic
|
Info (278001): Inferred 4 megafunctions from design logic
|
||||||
|
|
@ -355,47 +367,38 @@ Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:ad
|
||||||
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add0"
|
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add0"
|
||||||
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
|
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
|
||||||
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
|
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
|
||||||
Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add5"
|
|
||||||
Info (12133): Instantiated megafunction "lpm_add_sub:Add5" with the following parameter:
|
|
||||||
Info (12134): Parameter "LPM_WIDTH" = "7"
|
|
||||||
Info (12134): Parameter "LPM_DIRECTION" = "ADD"
|
|
||||||
Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
|
|
||||||
Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
|
|
||||||
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add5"
|
|
||||||
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add5"
|
|
||||||
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add5"
|
|
||||||
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder|addcore:adder[0]", which is child of megafunction instantiation "lpm_add_sub:Add5"
|
|
||||||
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add5|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add5"
|
|
||||||
Info (13014): Ignored 32 buffer(s)
|
Info (13014): Ignored 32 buffer(s)
|
||||||
Info (13019): Ignored 32 SOFT buffer(s)
|
Info (13019): Ignored 32 SOFT buffer(s)
|
||||||
|
Info (13000): Registers with preset signals will power-up high
|
||||||
Info (280013): Promoted pin-driven signal(s) to global signal
|
Info (280013): Promoted pin-driven signal(s) to global signal
|
||||||
Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal
|
Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal
|
||||||
Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal
|
Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal
|
||||||
Warning (21074): Design contains 7 input pin(s) that do not drive logic
|
Warning (21074): Design contains 8 input pin(s) that do not drive logic
|
||||||
Warning (15610): No output dependent on input pin "Q3"
|
Warning (15610): No output dependent on input pin "Q3"
|
||||||
Warning (15610): No output dependent on input pin "PHI0in"
|
Warning (15610): No output dependent on input pin "PHI0in"
|
||||||
|
Warning (15610): No output dependent on input pin "nMode"
|
||||||
Warning (15610): No output dependent on input pin "A[11]"
|
Warning (15610): No output dependent on input pin "A[11]"
|
||||||
Warning (15610): No output dependent on input pin "A[12]"
|
Warning (15610): No output dependent on input pin "A[12]"
|
||||||
Warning (15610): No output dependent on input pin "A[13]"
|
Warning (15610): No output dependent on input pin "A[13]"
|
||||||
Warning (15610): No output dependent on input pin "A[14]"
|
Warning (15610): No output dependent on input pin "A[14]"
|
||||||
Warning (15610): No output dependent on input pin "A[15]"
|
Warning (15610): No output dependent on input pin "A[15]"
|
||||||
Info (21057): Implemented 165 device resources after synthesis - the final resource count might be different
|
Info (21057): Implemented 168 device resources after synthesis - the final resource count might be different
|
||||||
Info (21058): Implemented 27 input pins
|
Info (21058): Implemented 27 input pins
|
||||||
Info (21059): Implemented 18 output pins
|
Info (21059): Implemented 18 output pins
|
||||||
Info (21060): Implemented 16 bidirectional pins
|
Info (21060): Implemented 16 bidirectional pins
|
||||||
Info (21063): Implemented 103 macrocells
|
Info (21063): Implemented 105 macrocells
|
||||||
Info (21073): Implemented 1 shareable expanders
|
Info (21073): Implemented 2 shareable expanders
|
||||||
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg
|
||||||
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 15 warnings
|
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 16 warnings
|
||||||
Info: Peak virtual memory: 304 megabytes
|
Info: Peak virtual memory: 4587 megabytes
|
||||||
Info: Processing ended: Sat Sep 07 21:15:32 2019
|
Info: Processing ended: Sat Sep 07 22:26:03 2019
|
||||||
Info: Elapsed time: 00:00:09
|
Info: Elapsed time: 00:00:01
|
||||||
Info: Total CPU time (on all processors): 00:00:08
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
||||||
+------------------------------------------+
|
+------------------------------------------+
|
||||||
; Analysis & Synthesis Suppressed Messages ;
|
; Analysis & Synthesis Suppressed Messages ;
|
||||||
+------------------------------------------+
|
+------------------------------------------+
|
||||||
The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,3 +1,3 @@
|
||||||
Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z"
|
Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z"
|
||||||
Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z"
|
Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z"
|
||||||
Warning (10268): Verilog HDL information at GR8RAM.v(194): always construct contains both blocking and non-blocking assignments
|
Warning (10268): Verilog HDL information at GR8RAM.v(190): always construct contains both blocking and non-blocking assignments
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
Analysis & Synthesis Status : Successful - Sat Sep 07 21:15:31 2019
|
Analysis & Synthesis Status : Successful - Sat Sep 07 22:26:03 2019
|
||||||
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
||||||
Revision Name : GR8RAM
|
Revision Name : GR8RAM
|
||||||
Top-level Entity Name : GR8RAM
|
Top-level Entity Name : GR8RAM
|
||||||
Family : MAX7000S
|
Family : MAX7000S
|
||||||
Total macrocells : 103
|
Total macrocells : 105
|
||||||
Total pins : 61
|
Total pins : 61
|
||||||
|
|
|
||||||
|
|
@ -56,7 +56,7 @@
|
||||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||||
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15
|
CHIP "GR8RAM" ASSIGNED TO AN: EPM7128SLC84-15
|
||||||
|
|
||||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||||
|
|
@ -97,14 +97,14 @@ D[3] : 33 : bidir : TTL :
|
||||||
D[2] : 34 : bidir : TTL : : : Y
|
D[2] : 34 : bidir : TTL : : : Y
|
||||||
D[1] : 35 : bidir : TTL : : : Y
|
D[1] : 35 : bidir : TTL : : : Y
|
||||||
D[0] : 36 : bidir : TTL : : : Y
|
D[0] : 36 : bidir : TTL : : : Y
|
||||||
nMode : 37 : input : TTL : : : N
|
RESERVED : 37 : : : : :
|
||||||
VCCIO : 38 : power : : 5.0V : :
|
VCCIO : 38 : power : : 5.0V : :
|
||||||
nCAS0 : 39 : output : TTL : : : Y
|
nCAS0 : 39 : output : TTL : : : Y
|
||||||
nCAS1 : 40 : output : TTL : : : Y
|
nCAS1 : 40 : output : TTL : : : Y
|
||||||
nRCS : 41 : output : TTL : : : Y
|
nRCS : 41 : output : TTL : : : Y
|
||||||
GND : 42 : gnd : : : :
|
GND : 42 : gnd : : : :
|
||||||
VCCINT : 43 : power : : 5.0V : :
|
VCCINT : 43 : power : : 5.0V : :
|
||||||
RESERVED : 44 : : : : :
|
nMode : 44 : input : TTL : : : Y
|
||||||
nROE : 45 : output : TTL : : : Y
|
nROE : 45 : output : TTL : : : Y
|
||||||
RA[9] : 46 : output : TTL : : : Y
|
RA[9] : 46 : output : TTL : : : Y
|
||||||
GND : 47 : gnd : : : :
|
GND : 47 : gnd : : : :
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
||||||
TimeQuest Timing Analyzer report for GR8RAM
|
TimeQuest Timing Analyzer report for GR8RAM
|
||||||
Sat Sep 07 21:15:48 2019
|
Sat Sep 07 22:26:09 2019
|
||||||
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
|
|
||||||
|
|
||||||
---------------------
|
---------------------
|
||||||
|
|
@ -8,35 +8,36 @@ Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
|
||||||
---------------------
|
---------------------
|
||||||
1. Legal Notice
|
1. Legal Notice
|
||||||
2. TimeQuest Timing Analyzer Summary
|
2. TimeQuest Timing Analyzer Summary
|
||||||
3. Clocks
|
3. Parallel Compilation
|
||||||
4. Fmax Summary
|
4. Clocks
|
||||||
5. Setup Summary
|
5. Fmax Summary
|
||||||
6. Hold Summary
|
6. Setup Summary
|
||||||
7. Recovery Summary
|
7. Hold Summary
|
||||||
8. Removal Summary
|
8. Recovery Summary
|
||||||
9. Minimum Pulse Width Summary
|
9. Removal Summary
|
||||||
10. Setup: 'C7M'
|
10. Minimum Pulse Width Summary
|
||||||
11. Setup: 'C7M_2'
|
11. Setup: 'C7M'
|
||||||
12. Hold: 'C7M_2'
|
12. Setup: 'C7M_2'
|
||||||
13. Hold: 'C7M'
|
13. Hold: 'C7M_2'
|
||||||
14. Minimum Pulse Width: 'C7M_2'
|
14. Hold: 'C7M'
|
||||||
15. Minimum Pulse Width: 'C7M'
|
15. Minimum Pulse Width: 'C7M_2'
|
||||||
16. Setup Times
|
16. Minimum Pulse Width: 'C7M'
|
||||||
17. Hold Times
|
17. Setup Times
|
||||||
18. Clock to Output Times
|
18. Hold Times
|
||||||
19. Minimum Clock to Output Times
|
19. Clock to Output Times
|
||||||
20. Propagation Delay
|
20. Minimum Clock to Output Times
|
||||||
21. Minimum Propagation Delay
|
21. Propagation Delay
|
||||||
22. Output Enable Times
|
22. Minimum Propagation Delay
|
||||||
23. Minimum Output Enable Times
|
23. Output Enable Times
|
||||||
24. Output Disable Times
|
24. Minimum Output Enable Times
|
||||||
25. Minimum Output Disable Times
|
25. Output Disable Times
|
||||||
26. Setup Transfers
|
26. Minimum Output Disable Times
|
||||||
27. Hold Transfers
|
27. Setup Transfers
|
||||||
28. Report TCCS
|
28. Hold Transfers
|
||||||
29. Report RSKM
|
29. Report TCCS
|
||||||
30. Unconstrained Paths
|
30. Report RSKM
|
||||||
31. TimeQuest Timing Analyzer Messages
|
31. Unconstrained Paths
|
||||||
|
32. TimeQuest Timing Analyzer Messages
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -72,6 +73,17 @@ applicable agreement for further details.
|
||||||
+--------------------+-------------------------------------------------------------------+
|
+--------------------+-------------------------------------------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
|
||||||
|
+-------------------------------------+
|
||||||
|
; Parallel Compilation ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
; Processors ; Number ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
; Number detected on machine ; 8 ;
|
||||||
|
; Maximum allowed ; 1 ;
|
||||||
|
+----------------------------+--------+
|
||||||
|
|
||||||
|
|
||||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||||
; Clocks ;
|
; Clocks ;
|
||||||
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
|
||||||
|
|
@ -87,7 +99,7 @@ applicable agreement for further details.
|
||||||
+-----------+-----------------+------------+------+
|
+-----------+-----------------+------------+------+
|
||||||
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
||||||
+-----------+-----------------+------------+------+
|
+-----------+-----------------+------------+------+
|
||||||
; 10.42 MHz ; 10.42 MHz ; C7M ; ;
|
; 20.83 MHz ; 20.83 MHz ; C7M ; ;
|
||||||
+-----------+-----------------+------------+------+
|
+-----------+-----------------+------------+------+
|
||||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||||
|
|
||||||
|
|
@ -97,7 +109,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||||
+-------+---------+---------------+
|
+-------+---------+---------------+
|
||||||
; Clock ; Slack ; End Point TNS ;
|
; Clock ; Slack ; End Point TNS ;
|
||||||
+-------+---------+---------------+
|
+-------+---------+---------------+
|
||||||
; C7M ; -47.500 ; -1979.500 ;
|
; C7M ; -47.000 ; -2056.000 ;
|
||||||
; C7M_2 ; -27.500 ; -33.000 ;
|
; C7M_2 ; -27.500 ; -33.000 ;
|
||||||
+-------+---------+---------------+
|
+-------+---------+---------------+
|
||||||
|
|
||||||
|
|
@ -130,7 +142,7 @@ No paths to report.
|
||||||
; Clock ; Slack ; End Point TNS ;
|
; Clock ; Slack ; End Point TNS ;
|
||||||
+-------+--------+---------------+
|
+-------+--------+---------------+
|
||||||
; C7M_2 ; -5.500 ; -22.000 ;
|
; C7M_2 ; -5.500 ; -22.000 ;
|
||||||
; C7M ; -4.500 ; -450.000 ;
|
; C7M ; -4.500 ; -468.000 ;
|
||||||
+-------+--------+---------------+
|
+-------+--------+---------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -139,106 +151,106 @@ No paths to report.
|
||||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
; -47.500 ; REGEN ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[10] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[18] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[19] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[11] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[12] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[20] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[21] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[13] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[14] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[14] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[22] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[22] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[23] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Addr[8] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Bank[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; Addr[8] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.500 ; REGEN ; Bank[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
|
||||||
; -47.500 ; REGEN ; Bank[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
|
||||||
; -47.500 ; REGEN ; Bank[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
|
||||||
; -47.500 ; REGEN ; Bank[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
|
||||||
; -47.500 ; REGEN ; Bank[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
|
||||||
; -47.500 ; REGEN ; Bank[6] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
|
||||||
; -47.500 ; REGEN ; Bank[7] ; C7M ; C7M ; 0.500 ; 0.000 ; 44.000 ;
|
|
||||||
; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
|
||||||
; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; ASel ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -47.000 ; REGEN ; CASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
; -47.000 ; REGEN ; RASr ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -46.500 ; S[0] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
|
; -47.000 ; REGEN ; Bank[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -46.500 ; S[2] ; IncAddrM ; C7M ; C7M ; 0.500 ; 0.000 ; 43.000 ;
|
; -47.000 ; REGEN ; Bank[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -46.000 ; IncAddrL ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
|
; -47.000 ; REGEN ; Bank[2] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -25.500 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -47.000 ; REGEN ; Bank[3] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -25.500 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -47.000 ; REGEN ; Bank[4] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -25.500 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -47.000 ; REGEN ; Bank[5] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -47.000 ; REGEN ; CAS0r ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -47.000 ; REGEN ; CAS1r ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -47.000 ; REGEN ; Bank[6] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -47.000 ; REGEN ; Bank[7] ; C7M ; C7M ; 1.000 ; 0.000 ; 44.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -46.000 ; S[2] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[1] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -46.000 ; S[2] ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -46.000 ; IncAddrM ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -46.000 ; S[1] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -46.000 ; S[1] ; IncAddrM ; C7M ; C7M ; 1.000 ; 0.000 ; 43.000 ;
|
||||||
; -25.500 ; S[2] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[0] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[2] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; IncAddrH ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[1] ; REGEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[0] ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[1] ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[2] ; IncAddrL ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[2] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[10] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[1] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[0] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[18] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[2] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[3] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; IncAddrM ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[19] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[11] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[11] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[12] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[15] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[0] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[14] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[20] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[13] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[12] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[11] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[4] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[10] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[9] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[8] ; IncAddrH ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[5] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[2] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[1] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[0] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[21] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; Addr[16] ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[2] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; IncAddrH ; Addr[16] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[1] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[2] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
; -25.500 ; S[0] ; Addr[13] ; C7M ; C7M ; 0.500 ; 0.000 ; 22.000 ;
|
; -25.000 ; S[1] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
|
; -25.000 ; S[0] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
|
; -25.000 ; Addr[17] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
|
; -25.000 ; IncAddrH ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
|
; -25.000 ; Addr[16] ; Addr[17] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
|
; -25.000 ; S[1] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
|
; -25.000 ; S[2] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
|
; -25.000 ; S[0] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
|
; -25.000 ; Addr[9] ; Addr[9] ; C7M ; C7M ; 1.000 ; 0.000 ; 22.000 ;
|
||||||
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
+---------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -285,29 +297,25 @@ No paths to report.
|
||||||
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||||
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||||
; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; PHI1reg ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; PHI0seen ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; S[0] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; S[1] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; S[2] ; S[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; PHI1reg ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; PHI0seen ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; S[1] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; S[2] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; S[0] ; S[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; PHI1reg ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; PHI0seen ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; S[0] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; S[2] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; S[1] ; S[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; IOROMEN ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; S[2] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; S[1] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; S[0] ; IOROMEN ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
|
||||||
; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; Addr[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; Addr[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; Addr[15] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
|
@ -330,50 +338,32 @@ No paths to report.
|
||||||
; 5.000 ; Addr[22] ; Addr[22] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; Addr[22] ; Addr[22] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; Addr[6] ; Addr[6] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; Addr[7] ; Addr[7] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; Addr[23] ; Addr[23] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
; 5.000 ; Addr[8] ; Addr[8] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 5.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 9.000 ;
|
||||||
|
; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[2] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[1] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; S[0] ; REGEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[2] ; CSDBEN ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; IncAddrL ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[0] ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[1] ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[2] ; IncAddrL ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[2] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[2] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[1] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[0] ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[3] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[2] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[1] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[0] ; lpm_counter:Ref_rtl_0|dffs[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[2] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[1] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[0] ; RASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[1] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[2] ; ASel ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[0] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; S[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[3] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[2] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[1] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; lpm_counter:Ref_rtl_0|dffs[0] ; CASr ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; IncAddrL ; Addr[0] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[2] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[1] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; Addr[0] ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; IncAddrL ; Addr[1] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[1] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[2] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[0] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; IncAddrM ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; Addr[14] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; Addr[13] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; Addr[12] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
|
@ -381,10 +371,32 @@ No paths to report.
|
||||||
; 18.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; Addr[10] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; Addr[9] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; Addr[8] ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; IncAddrM ; Addr[15] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; S[2] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[1] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; IncAddrH ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
; 18.000 ; IncAddrM ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
|
||||||
; 18.000 ; Addr[15] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
; 18.000 ; Addr[15] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[0] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; Addr[14] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; Addr[13] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; Addr[12] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; Addr[11] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; Addr[10] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; Addr[9] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; Addr[8] ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; IncAddrM ; IncAddrH ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[2] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[1] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[0] ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; IncAddrH ; Addr[16] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[2] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[1] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[0] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; IncAddrH ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; Addr[16] ; Addr[17] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[1] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[2] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; S[0] ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
|
; 18.000 ; IncAddrM ; Addr[9] ; C7M ; C7M ; 0.000 ; 0.000 ; 22.000 ;
|
||||||
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
+--------+-------------------------------+-------------------------------+--------------+-------------+--------------+------------+------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -413,82 +425,86 @@ No paths to report.
|
||||||
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; ASel ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; ASel ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; ASel ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; ASel ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[0] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[0] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[0] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[0] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[10] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[10] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[10] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[10] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[11] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[11] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[11] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[11] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[12] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[12] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[12] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[12] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[13] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[13] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[13] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[13] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[14] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[14] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[14] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[14] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[15] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[15] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[15] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[15] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[16] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[16] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[16] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[16] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[17] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[17] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[17] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[17] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[18] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[18] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[18] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[18] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[19] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[19] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[19] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[19] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[1] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[1] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[1] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[1] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[20] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[20] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[20] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[20] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[21] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[21] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[21] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[21] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[22] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[22] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[22] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[22] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[2] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[23] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[2] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[23] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[3] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[2] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[3] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[2] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[4] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[3] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[4] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[3] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[5] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[4] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[5] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[4] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[6] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[5] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[6] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[5] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[7] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[6] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[7] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[6] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[8] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[7] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[8] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[7] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Addr[9] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[8] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Addr[9] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[8] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[0] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Addr[9] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[0] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Addr[9] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[1] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[0] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[1] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[0] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[2] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[1] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[2] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[1] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[3] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[2] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[3] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[2] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[4] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[3] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[4] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[3] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[5] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[4] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[5] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[4] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[6] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[5] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[6] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[5] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; Bank[7] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[6] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; Bank[7] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[6] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CASr ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; Bank[7] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CASr ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; Bank[7] ;
|
||||||
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CAS0r ;
|
||||||
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CAS0r ;
|
||||||
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CAS1r ;
|
||||||
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CAS1r ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSDBEN ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; CSDBEN ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSDBEN ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; CSDBEN ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; FullIOEN ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; FullIOEN ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; FullIOEN ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; FullIOEN ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IOROMEN ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOROMEN ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IOROMEN ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrH ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IncAddrH ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrH ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IncAddrH ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrL ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IncAddrL ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrL ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IncAddrL ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Fall ; IncAddrM ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; IncAddrM ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Fall ; IncAddrM ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; IncAddrM ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI0seen ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI0seen ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI0seen ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; PHI0seen ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI1reg ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; PHI1reg ;
|
||||||
|
|
@ -507,10 +523,6 @@ No paths to report.
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[0] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[0] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[1] ;
|
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[1] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[1] ;
|
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[1] ;
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[2] ;
|
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[2] ;
|
|
||||||
; -4.500 ; 0.500 ; 5.000 ; High Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[3] ;
|
|
||||||
; -4.500 ; 0.500 ; 5.000 ; Low Pulse Width ; C7M ; Rise ; lpm_counter:Ref_rtl_0|dffs[3] ;
|
|
||||||
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
+--------+--------------+----------------+------------------+-------+------------+-------------------------------+
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -531,26 +543,20 @@ No paths to report.
|
||||||
; A[8] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
; A[8] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||||
; A[9] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
; A[9] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||||
; A[10] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
; A[10] ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||||
|
; D[*] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
|
; D[0] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
|
; D[1] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
|
; D[2] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
|
; D[3] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
|
; D[4] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
|
; D[5] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
|
; D[6] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
|
; D[7] ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
; PHI1in ; C7M ; 101.000 ; 101.000 ; Rise ; C7M ;
|
; PHI1in ; C7M ; 101.000 ; 101.000 ; Rise ; C7M ;
|
||||||
; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
||||||
; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
; nIOSEL ; C7M ; 24.000 ; 24.000 ; Rise ; C7M ;
|
||||||
; nIOSTRB ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
; nIOSTRB ; C7M ; 11.000 ; 11.000 ; Rise ; C7M ;
|
||||||
; A[*] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
|
; nWE ; C7M ; 46.000 ; 46.000 ; Rise ; C7M ;
|
||||||
; A[0] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
|
|
||||||
; A[1] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
|
|
||||||
; A[2] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
|
|
||||||
; A[3] ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
|
|
||||||
; D[*] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; D[0] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; D[1] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; D[2] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; D[3] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; D[4] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; D[5] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; D[6] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; D[7] ; C7M ; 24.000 ; 24.000 ; Fall ; C7M ;
|
|
||||||
; nDEVSEL ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
|
|
||||||
; nWE ; C7M ; 46.000 ; 46.000 ; Fall ; C7M ;
|
|
||||||
; A[*] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ;
|
; A[*] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ;
|
||||||
; A[0] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ;
|
; A[0] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ;
|
||||||
; A[1] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ;
|
; A[1] ; C7M_2 ; 26.000 ; 26.000 ; Fall ; C7M_2 ;
|
||||||
|
|
@ -578,26 +584,20 @@ No paths to report.
|
||||||
; A[8] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
; A[8] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||||
; A[9] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
; A[9] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||||
; A[10] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
; A[10] ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||||
|
; D[*] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
|
; D[0] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
|
; D[1] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
|
; D[2] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
|
; D[3] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
|
; D[4] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
|
; D[5] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
|
; D[6] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
|
; D[7] ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ;
|
; PHI1in ; C7M ; -12.000 ; -12.000 ; Rise ; C7M ;
|
||||||
; nDEVSEL ; C7M ; -38.000 ; -38.000 ; Rise ; C7M ;
|
; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
; nIOSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
; nIOSEL ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||||
; nIOSTRB ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
; nIOSTRB ; C7M ; -3.000 ; -3.000 ; Rise ; C7M ;
|
||||||
; A[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
; nWE ; C7M ; -16.000 ; -16.000 ; Rise ; C7M ;
|
||||||
; A[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; A[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; A[2] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; A[3] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[*] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[0] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[1] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[2] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[3] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[4] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[5] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[6] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; D[7] ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; nDEVSEL ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; nWE ; C7M ; -16.000 ; -16.000 ; Fall ; C7M ;
|
|
||||||
; A[*] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
; A[*] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
||||||
; A[0] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
; A[0] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
||||||
; A[1] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
; A[1] ; C7M_2 ; -18.000 ; -18.000 ; Fall ; C7M_2 ;
|
||||||
|
|
@ -613,6 +613,15 @@ No paths to report.
|
||||||
+-----------+------------+--------+--------+------------+-----------------+
|
+-----------+------------+--------+--------+------------+-----------------+
|
||||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||||
+-----------+------------+--------+--------+------------+-----------------+
|
+-----------+------------+--------+--------+------------+-----------------+
|
||||||
|
; D[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[2] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[3] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[4] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[5] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[6] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[7] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
|
@ -629,29 +638,6 @@ No paths to report.
|
||||||
; nCAS1 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ;
|
; nCAS1 ; C7M ; 56.000 ; 56.000 ; Rise ; C7M ;
|
||||||
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[8] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[9] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||||
; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||||
; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||||
|
|
@ -663,6 +649,15 @@ No paths to report.
|
||||||
+-----------+------------+--------+--------+------------+-----------------+
|
+-----------+------------+--------+--------+------------+-----------------+
|
||||||
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
||||||
+-----------+------------+--------+--------+------------+-----------------+
|
+-----------+------------+--------+--------+------------+-----------------+
|
||||||
|
; D[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[2] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[3] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[4] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[5] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[6] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
; D[7] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; RA[*] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; RA[0] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; RA[1] ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
|
|
@ -679,29 +674,6 @@ No paths to report.
|
||||||
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; nRAS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
; nRCS ; C7M ; 34.000 ; 34.000 ; Rise ; C7M ;
|
||||||
; D[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; D[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[*] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[0] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[1] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[2] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[3] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[4] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[5] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[6] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[7] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[8] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[9] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; RA[10] ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; nCAS0 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; nCAS1 ; C7M ; 34.000 ; 34.000 ; Fall ; C7M ;
|
|
||||||
; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
; nCAS0 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||||
; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
; nCAS1 ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||||
; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
; nRAS ; C7M_2 ; 54.000 ; 54.000 ; Fall ; C7M_2 ;
|
||||||
|
|
@ -816,7 +788,6 @@ No paths to report.
|
||||||
; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||||
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
|
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||||
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
|
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||||
; nMode ; D[7] ; 32.000 ; ; ; 32.000 ;
|
|
||||||
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
|
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
|
||||||
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
|
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
|
||||||
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
|
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
|
||||||
|
|
@ -946,7 +917,6 @@ No paths to report.
|
||||||
; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
; nIOSTRB ; RA[7] ; 32.000 ; 32.000 ; 32.000 ; 32.000 ;
|
||||||
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
|
; nIOSTRB ; nRCS ; ; 32.000 ; 32.000 ; ;
|
||||||
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
|
; nIOSTRB ; nRWE ; 32.000 ; ; ; 32.000 ;
|
||||||
; nMode ; D[7] ; 32.000 ; ; ; 32.000 ;
|
|
||||||
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
|
; nWE ; D[0] ; 39.000 ; ; ; 39.000 ;
|
||||||
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
|
; nWE ; D[1] ; 39.000 ; ; ; 39.000 ;
|
||||||
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
|
; nWE ; D[2] ; 39.000 ; ; ; 39.000 ;
|
||||||
|
|
@ -1077,7 +1047,7 @@ No paths to report.
|
||||||
+------------+----------+----------+----------+----------+----------+
|
+------------+----------+----------+----------+----------+----------+
|
||||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||||
+------------+----------+----------+----------+----------+----------+
|
+------------+----------+----------+----------+----------+----------+
|
||||||
; C7M ; C7M ; 87 ; 0 ; 324 ; 200 ;
|
; C7M ; C7M ; 644 ; 0 ; 0 ; 0 ;
|
||||||
; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ;
|
; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ;
|
||||||
+------------+----------+----------+----------+----------+----------+
|
+------------+----------+----------+----------+----------+----------+
|
||||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||||
|
|
@ -1088,7 +1058,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
|
||||||
+------------+----------+----------+----------+----------+----------+
|
+------------+----------+----------+----------+----------+----------+
|
||||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||||
+------------+----------+----------+----------+----------+----------+
|
+------------+----------+----------+----------+----------+----------+
|
||||||
; C7M ; C7M ; 87 ; 0 ; 324 ; 200 ;
|
; C7M ; C7M ; 644 ; 0 ; 0 ; 0 ;
|
||||||
; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ;
|
; C7M ; C7M_2 ; 0 ; 0 ; 14 ; 0 ;
|
||||||
+------------+----------+----------+----------+----------+----------+
|
+------------+----------+----------+----------+----------+----------+
|
||||||
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
||||||
|
|
@ -1113,8 +1083,8 @@ No dedicated SERDES Receiver circuitry present in device or used in design
|
||||||
+---------------------------------+-------+------+
|
+---------------------------------+-------+------+
|
||||||
; Illegal Clocks ; 0 ; 0 ;
|
; Illegal Clocks ; 0 ; 0 ;
|
||||||
; Unconstrained Clocks ; 0 ; 0 ;
|
; Unconstrained Clocks ; 0 ; 0 ;
|
||||||
; Unconstrained Input Ports ; 34 ; 34 ;
|
; Unconstrained Input Ports ; 33 ; 33 ;
|
||||||
; Unconstrained Input Port Paths ; 464 ; 464 ;
|
; Unconstrained Input Port Paths ; 477 ; 477 ;
|
||||||
; Unconstrained Output Ports ; 33 ; 33 ;
|
; Unconstrained Output Ports ; 33 ; 33 ;
|
||||||
; Unconstrained Output Port Paths ; 266 ; 266 ;
|
; Unconstrained Output Port Paths ; 266 ; 266 ;
|
||||||
+---------------------------------+-------+------+
|
+---------------------------------+-------+------+
|
||||||
|
|
@ -1124,9 +1094,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design
|
||||||
; TimeQuest Timing Analyzer Messages ;
|
; TimeQuest Timing Analyzer Messages ;
|
||||||
+------------------------------------+
|
+------------------------------------+
|
||||||
Info: *******************************************************************
|
Info: *******************************************************************
|
||||||
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
|
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
|
||||||
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||||
Info: Processing started: Sat Sep 07 21:15:43 2019
|
Info: Processing started: Sat Sep 07 22:26:08 2019
|
||||||
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
||||||
Info: qsta_default_script.tcl version: #1
|
Info: qsta_default_script.tcl version: #1
|
||||||
Warning (20028): Parallel compilation is not licensed and has been disabled
|
Warning (20028): Parallel compilation is not licensed and has been disabled
|
||||||
|
|
@ -1140,10 +1110,10 @@ Info (332105): Deriving Clocks
|
||||||
Info (332105): create_clock -period 1.000 -name C7M_2 C7M_2
|
Info (332105): create_clock -period 1.000 -name C7M_2 C7M_2
|
||||||
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||||||
Critical Warning (332148): Timing requirements not met
|
Critical Warning (332148): Timing requirements not met
|
||||||
Info (332146): Worst-case setup slack is -47.500
|
Info (332146): Worst-case setup slack is -47.000
|
||||||
Info (332119): Slack End Point TNS Clock
|
Info (332119): Slack End Point TNS Clock
|
||||||
Info (332119): ========= ============= =====================
|
Info (332119): ========= ============= =====================
|
||||||
Info (332119): -47.500 -1979.500 C7M
|
Info (332119): -47.000 -2056.000 C7M
|
||||||
Info (332119): -27.500 -33.000 C7M_2
|
Info (332119): -27.500 -33.000 C7M_2
|
||||||
Info (332146): Worst-case hold slack is -1.500
|
Info (332146): Worst-case hold slack is -1.500
|
||||||
Info (332119): Slack End Point TNS Clock
|
Info (332119): Slack End Point TNS Clock
|
||||||
|
|
@ -1156,14 +1126,14 @@ Info (332146): Worst-case minimum pulse width slack is -5.500
|
||||||
Info (332119): Slack End Point TNS Clock
|
Info (332119): Slack End Point TNS Clock
|
||||||
Info (332119): ========= ============= =====================
|
Info (332119): ========= ============= =====================
|
||||||
Info (332119): -5.500 -22.000 C7M_2
|
Info (332119): -5.500 -22.000 C7M_2
|
||||||
Info (332119): -4.500 -450.000 C7M
|
Info (332119): -4.500 -468.000 C7M
|
||||||
Info (332001): The selected device family is not supported by the report_metastability command.
|
Info (332001): The selected device family is not supported by the report_metastability command.
|
||||||
Info (332102): Design is not fully constrained for setup requirements
|
Info (332102): Design is not fully constrained for setup requirements
|
||||||
Info (332102): Design is not fully constrained for hold requirements
|
Info (332102): Design is not fully constrained for hold requirements
|
||||||
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
|
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
|
||||||
Info: Peak virtual memory: 259 megabytes
|
Info: Peak virtual memory: 4530 megabytes
|
||||||
Info: Processing ended: Sat Sep 07 21:15:48 2019
|
Info: Processing ended: Sat Sep 07 22:26:09 2019
|
||||||
Info: Elapsed time: 00:00:05
|
Info: Elapsed time: 00:00:01
|
||||||
Info: Total CPU time (on all processors): 00:00:05
|
Info: Total CPU time (on all processors): 00:00:01
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -3,8 +3,8 @@ TimeQuest Timing Analyzer Summary
|
||||||
------------------------------------------------------------
|
------------------------------------------------------------
|
||||||
|
|
||||||
Type : Setup 'C7M'
|
Type : Setup 'C7M'
|
||||||
Slack : -47.500
|
Slack : -47.000
|
||||||
TNS : -1979.500
|
TNS : -2056.000
|
||||||
|
|
||||||
Type : Setup 'C7M_2'
|
Type : Setup 'C7M_2'
|
||||||
Slack : -27.500
|
Slack : -27.500
|
||||||
|
|
@ -24,6 +24,6 @@ TNS : -22.000
|
||||||
|
|
||||||
Type : Minimum Pulse Width 'C7M'
|
Type : Minimum Pulse Width 'C7M'
|
||||||
Slack : -4.500
|
Slack : -4.500
|
||||||
TNS : -450.000
|
TNS : -468.000
|
||||||
|
|
||||||
------------------------------------------------------------
|
------------------------------------------------------------
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue
Block a user