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Revert "Updated slew rate/current strength assignments"

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This reverts commit 780fe32807.
This commit is contained in:
Zane Kaminski 2021-04-20 05:50:09 -04:00
parent 780fe32807
commit d2dbdc8193
45 changed files with 1337 additions and 1705 deletions
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503
cpld/GR8RAM.qsf
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@ -72,446 +72,93 @@ set_global_assignment -name SEED 235
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
set_global_assignment -name VERILOG_FILE GR8RAM.v
set_location_assignment PIN_1 -to RA[4]
set_location_assignment PIN_2 -to RA[5]
set_location_assignment PIN_3 -to RA[6]
set_location_assignment PIN_4 -to RA[3]
set_location_assignment PIN_5 -to nFCS
set_location_assignment PIN_6 -to RA[7]
set_location_assignment PIN_7 -to RA[8]
set_location_assignment PIN_8 -to RA[9]
set_location_assignment PIN_12 -to FCK
set_location_assignment PIN_14 -to RA[10]
set_location_assignment PIN_15 -to MOSI
set_location_assignment PIN_16 -to MISO
set_location_assignment PIN_30 -to nRESout
set_location_assignment PIN_34 -to RA[11]
set_location_assignment PIN_35 -to RA[12]
set_location_assignment PIN_36 -to RA[13]
set_location_assignment PIN_37 -to RA[14]
set_location_assignment PIN_38 -to RA[15]
set_location_assignment PIN_39 -to nIOSEL
set_location_assignment PIN_42 -to nIOSTRB
set_location_assignment PIN_40 -to nDEVSEL
set_location_assignment PIN_41 -to PHI0
set_location_assignment PIN_43 -to nWE
set_location_assignment PIN_44 -to nRES
set_location_assignment PIN_47 -to SD[1]
set_location_assignment PIN_50 -to SD[0]
set_location_assignment PIN_51 -to SD[4]
set_location_assignment PIN_100 -to RA[0]
set_location_assignment PIN_99 -to RD[7]
set_location_assignment PIN_52 -to SD[5]
set_location_assignment PIN_54 -to SD[7]
set_location_assignment PIN_55 -to SD[3]
set_location_assignment PIN_56 -to SD[2]
set_location_assignment PIN_53 -to SD[6]
set_location_assignment PIN_57 -to DQMH
set_location_assignment PIN_58 -to nSWE
set_location_assignment PIN_62 -to nRAS
set_location_assignment PIN_61 -to nCAS
set_location_assignment PIN_64 -to C25M
set_location_assignment PIN_66 -to RCKE
set_location_assignment PIN_67 -to nRCS
set_location_assignment PIN_68 -to SA[12]
set_location_assignment PIN_69 -to SBA[0]
set_location_assignment PIN_70 -to SA[11]
set_location_assignment PIN_71 -to SBA[1]
set_location_assignment PIN_72 -to SA[9]
set_location_assignment PIN_73 -to SA[10]
set_location_assignment PIN_74 -to SA[8]
set_location_assignment PIN_75 -to SA[0]
set_location_assignment PIN_76 -to SA[4]
set_location_assignment PIN_77 -to SA[6]
set_location_assignment PIN_78 -to SA[7]
set_location_assignment PIN_81 -to SA[1]
set_location_assignment PIN_82 -to SA[2]
set_location_assignment PIN_83 -to SA[5]
set_location_assignment PIN_84 -to SA[3]
set_location_assignment PIN_85 -to DQML
set_location_assignment PIN_86 -to RD[0]
set_location_assignment PIN_87 -to RD[1]
set_location_assignment PIN_88 -to RD[2]
set_location_assignment PIN_89 -to RD[3]
set_location_assignment PIN_90 -to RD[4]
set_location_assignment PIN_91 -to RD[5]
set_location_assignment PIN_92 -to RD[6]
set_location_assignment PIN_97 -to RA[2]
set_location_assignment PIN_98 -to RA[1]
set_location_assignment PIN_96 -to SetFW[0]
set_location_assignment PIN_95 -to SetFW[1]
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2
set_location_assignment PIN_41 -to PHI0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI0
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to PHI0
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to PHI0
set_location_assignment PIN_43 -to nWE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nWE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nWE
set_location_assignment PIN_44 -to nRES
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRES
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to nRES
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to nRES
set_location_assignment PIN_96 -to SetFW[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW[0]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW[0]
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW[0]
set_location_assignment PIN_95 -to SetFW[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SetFW[1]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SetFW[1]
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SetFW[1]
set_location_assignment PIN_39 -to nIOSEL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSEL
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSEL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nIOSEL
set_location_assignment PIN_42 -to nIOSTRB
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nIOSTRB
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIOSTRB
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nIOSTRB
set_location_assignment PIN_40 -to nDEVSEL
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDEVSEL
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDEVSEL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nDEVSEL
set_location_assignment PIN_100 -to RA[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[0]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[0]
set_location_assignment PIN_98 -to RA[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[1]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[1]
set_location_assignment PIN_97 -to RA[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[2]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[2]
set_location_assignment PIN_4 -to RA[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[3]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[3]
set_location_assignment PIN_1 -to RA[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[4]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[4]
set_location_assignment PIN_2 -to RA[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[5]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[5]
set_location_assignment PIN_3 -to RA[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[6]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[6]
set_location_assignment PIN_6 -to RA[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[7]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[7]
set_location_assignment PIN_7 -to RA[8]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[8]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[8]
set_location_assignment PIN_8 -to RA[9]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[9]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[9]
set_location_assignment PIN_14 -to RA[10]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[10]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[10]
set_location_assignment PIN_34 -to RA[11]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[11]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[11]
set_location_assignment PIN_35 -to RA[12]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[12]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[12]
set_location_assignment PIN_36 -to RA[13]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[13]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[13]
set_location_assignment PIN_37 -to RA[14]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[14]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[14]
set_location_assignment PIN_38 -to RA[15]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA[15]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RA[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RA[15]
set_location_assignment PIN_86 -to RD[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[0]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[0]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[0]
set_location_assignment PIN_87 -to RD[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[1]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[1]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[1]
set_location_assignment PIN_88 -to RD[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[2]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[2]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[2]
set_location_assignment PIN_89 -to RD[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[3]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[3]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[3]
set_location_assignment PIN_90 -to RD[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[4]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[4]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[4]
set_location_assignment PIN_91 -to RD[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[5]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[5]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[5]
set_location_assignment PIN_92 -to RD[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[6]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[6]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[6]
set_location_assignment PIN_99 -to RD[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD[7]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD[7]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RD[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RD[7]
set_location_assignment PIN_19 -to RAdir
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RAdir
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RAdir
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAdir
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAdir
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RAdir
set_location_assignment PIN_17 -to RDdir
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RDdir
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RDdir
set_instance_assignment -name SLOW_SLEW_RATE ON -to RDdir
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RDdir
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RDdir
set_location_assignment PIN_30 -to nRESout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRESout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRESout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRESout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRESout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRESout
set_location_assignment PIN_5 -to nFCS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nFCS
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nFCS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nFCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nFCS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nFCS
set_location_assignment PIN_12 -to FCK
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to FCK
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to FCK
set_instance_assignment -name SLOW_SLEW_RATE OFF -to FCK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to FCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FCK
set_location_assignment PIN_15 -to MOSI
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MOSI
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MOSI
set_instance_assignment -name SLOW_SLEW_RATE ON -to MOSI
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MOSI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MOSI
set_location_assignment PIN_16 -to MISO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to MISO
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to MISO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MISO
set_location_assignment PIN_64 -to C25M
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C25M
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to C25M
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to C25M
set_location_assignment PIN_66 -to RCKE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCKE
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCKE
set_instance_assignment -name SLOW_SLEW_RATE ON -to RCKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RCKE
set_location_assignment PIN_67 -to nRCS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRCS
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRCS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRCS
set_location_assignment PIN_62 -to nRAS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRAS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRAS
set_location_assignment PIN_61 -to nCAS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nCAS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nCAS
set_location_assignment PIN_58 -to nSWE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nSWE
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nSWE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nSWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSWE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nSWE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA[1]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA[1]
set_location_assignment PIN_69 -to SBA[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SBA[0]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SBA[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SBA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SBA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SBA[0]
set_location_assignment PIN_68 -to SBA[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[12]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[12]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[12]
set_location_assignment PIN_70 -to SA[12]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[11]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[11]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[11]
set_location_assignment PIN_73 -to SA[11]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[10]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[10]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[10]
set_location_assignment PIN_72 -to SA[10]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[9]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[9]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[9]
set_location_assignment PIN_74 -to SA[8]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[8]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[8]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[8]
set_location_assignment PIN_78 -to SA[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[7]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[7]
set_location_assignment PIN_77 -to SA[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[6]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[6]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[6]
set_location_assignment PIN_83 -to SA[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[5]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[5]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[5]
set_location_assignment PIN_76 -to SA[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[4]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[4]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[4]
set_location_assignment PIN_84 -to SA[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[3]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[3]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[3]
set_location_assignment PIN_82 -to SA[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[2]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[2]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[2]
set_location_assignment PIN_81 -to SA[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[1]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[1]
set_location_assignment PIN_75 -to SA[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SA[0]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to SA[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SA[0]
set_location_assignment PIN_57 -to DQMH
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQMH
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQMH
set_location_assignment PIN_85 -to DQML
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to DQML
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DQML
set_location_assignment PIN_50 -to SD[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[0]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[0]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[0]
set_location_assignment PIN_47 -to SD[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[1]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[1]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[1]
set_location_assignment PIN_56 -to SD[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[2]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[2]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[2]
set_location_assignment PIN_55 -to SD[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[3]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[3]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[3]
set_location_assignment PIN_51 -to SD[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[4]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[4]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[4]
set_location_assignment PIN_52 -to SD[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[5]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[5]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[5]
set_location_assignment PIN_53 -to SD[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[6]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[6]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[6]
set_location_assignment PIN_54 -to SD[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to SD[7]
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to SD[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to SD[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SD[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD[7]
set_location_assignment PIN_48 -to DMAin
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DMAin
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to DMAin
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to DMAin
set_location_assignment PIN_49 -to INTin
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to INTin
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to INTin
set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to INTin
set_location_assignment PIN_20 -to INTout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to INTout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to INTout
set_instance_assignment -name SLOW_SLEW_RATE ON -to INTout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to INTout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to INTout
set_location_assignment PIN_18 -to DMAout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DMAout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to DMAout
set_instance_assignment -name SLOW_SLEW_RATE ON -to DMAout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DMAout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DMAout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to MISO
set_location_assignment PIN_21 -to nDMAout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDMAout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nDMAout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDMAout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDMAout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nDMAout
set_location_assignment PIN_19 -to RAdir
set_location_assignment PIN_20 -to INTout
set_location_assignment PIN_26 -to nNMIout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nNMIout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nNMIout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nNMIout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nNMIout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nNMIout
set_location_assignment PIN_27 -to nINHout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nINHout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nINHout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nINHout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nINHout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nINHout
set_location_assignment PIN_28 -to nRDYout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nRDYout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nRDYout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRDYout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRDYout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nRDYout
set_location_assignment PIN_29 -to nIRQout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to nIRQout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nIRQout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nIRQout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nIRQout
set_location_assignment PIN_33 -to RWout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to RWout
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RWout
set_instance_assignment -name SLOW_SLEW_RATE ON -to RWout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RWout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RWout
set_location_assignment PIN_48 -to DMAin
set_location_assignment PIN_49 -to INTin
set_location_assignment PIN_17 -to RDdir
set_location_assignment PIN_18 -to DMAout

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cpld/GR8RAM.qws
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cpld/db/GR8RAM.ace_cmp.cdb
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cpld/db/GR8RAM.asm.qmsg
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@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911782409 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911782409 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:43:02 2021 " "Processing started: Tue Apr 20 05:43:02 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911782409 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618911782409 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618911782409 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618911783535 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618911783550 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911784113 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:43:04 2021 " "Processing ended: Tue Apr 20 05:43:04 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911784113 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911784113 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911784113 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618911784113 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906796813 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906796829 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:19:56 2021 " "Processing started: Tue Apr 20 04:19:56 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906796829 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618906796829 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618906796829 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618906798235 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618906798282 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:59 2021 " "Processing ended: Tue Apr 20 04:19:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906799032 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618906799032 ""}

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cpld/db/GR8RAM.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Tue Apr 20 05:31:27 2021
Creation_Time = Mon Apr 19 05:50:25 2021

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cpld/db/GR8RAM.fit.qmsg
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@ -1,42 +1,39 @@
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618911772581 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618911772612 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618911773628 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618911773628 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618911773862 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618911773878 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911774175 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618911774175 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 80 " "No exact pin location assignment(s) for 1 pins of 80 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SA\[9\]" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 436 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 258 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618911774206 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618911774206 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618911774346 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618911774346 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618911774362 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618911774362 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911774362 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911774362 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911774362 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911774362 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618911774362 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618911774378 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618911774378 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618911774378 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911774393 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618911774393 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618911774393 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911774393 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 461 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618911774393 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911774393 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618911774393 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618911774393 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618911774425 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618911774487 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618911774487 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618911774487 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618911774487 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618911774503 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618911774503 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618911774503 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618911774503 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 41 1 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618911774503 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618911774503 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618911774503 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911774534 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618911774971 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911775409 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618911775425 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618911777237 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911777237 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618911777315 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "35 " "Router estimated average interconnect usage is 35% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "35 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618911778081 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618911778081 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911778878 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.70 " "Total time spent on timing analysis during the Fitter is 0.70 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618911778894 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911778894 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618911778925 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618911779222 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "378 " "Peak virtual memory: 378 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911779472 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:42:59 2021 " "Processing ended: Tue Apr 20 05:42:59 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911779472 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911779472 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911779472 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618911779472 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618906787984 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618906788015 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906788219 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906788219 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618906788531 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618906788562 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906788906 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618906788906 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618906789062 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618906789062 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618906789078 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618906789078 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906789078 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618906789078 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906789094 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906789094 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906789094 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789125 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906789140 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906789140 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789140 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 379 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618906789140 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906789140 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906789140 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618906789140 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618906789203 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618906789265 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618906789265 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618906789281 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618906789281 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906789328 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618906789531 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906790203 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618906790234 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618906791859 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906791859 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618906791922 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "36 " "Router estimated average interconnect usage is 36% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618906792469 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618906792469 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906793250 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.56 " "Total time spent on timing analysis during the Fitter is 0.56 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618906793281 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906793281 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618906793344 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618906793750 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:53 2021 " "Processing ended: Tue Apr 20 04:19:53 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906794016 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618906794016 ""}

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@ -1,19 +1,19 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911761846 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911761861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:42:41 2021 " "Processing started: Tue Apr 20 05:42:41 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911761861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618911761861 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618911761861 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618911764424 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618911764830 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618911764846 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618911764846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618911764846 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618911764971 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911764986 "|GR8RAM"}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618911766190 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911766533 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618911766533 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618911767158 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618911767237 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618911767237 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618911767237 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618911767237 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618911767237 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618911767596 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911767799 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:42:47 2021 " "Processing ended: Tue Apr 20 05:42:47 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911767799 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911767799 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911767799 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911767799 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906780187 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:19:39 2021 " "Processing started: Tue Apr 20 04:19:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906780202 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906781718 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906781890 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906781890 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618906781905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618906781905 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618906782030 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906782062 "|GR8RAM"}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618906783140 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906783406 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618906783406 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618906783906 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618906783968 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618906783968 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618906783968 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618906784124 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:19:44 2021 " "Processing ended: Tue Apr 20 04:19:44 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906784281 ""}

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@ -1,23 +1,23 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911786832 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911786847 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:43:05 2021 " "Processing started: Tue Apr 20 05:43:05 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911786847 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618911786847 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618911786847 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618911787035 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618911787925 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618911788097 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618911788097 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618911788269 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618911788722 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618911788863 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618911788863 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911788879 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911788879 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911788879 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618911788894 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618911789019 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.844 " "Worst-case setup slack is -9.844" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.844 -724.767 C25M " " -9.844 -724.767 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.019 -0.019 PHI0 " " -0.019 -0.019 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789050 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.952 " "Worst-case hold slack is -0.952" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.952 -0.952 PHI0 " " -0.952 -0.952 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.385 0.000 C25M " " 1.385 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789066 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.389 " "Worst-case recovery slack is -4.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.389 -127.281 C25M " " -4.389 -127.281 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.835 " "Worst-case removal slack is 4.835" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.835 0.000 C25M " " 4.835 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789082 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -3.000 PHI0 " " -3.000 -3.000 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911789097 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618911789300 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618911789472 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618911789472 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "275 " "Peak virtual memory: 275 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911789722 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:43:09 2021 " "Processing ended: Tue Apr 20 05:43:09 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911789722 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911789722 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911789722 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911789722 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906802095 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:20:00 2021 " "Processing started: Tue Apr 20 04:20:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906802110 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618906802314 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906803173 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906803329 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906803329 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618906803517 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618906804204 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618906804392 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804407 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618906804423 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618906804595 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.005 " "Worst-case setup slack is -9.005" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.005 -699.357 C25M " " -9.005 -699.357 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.425 -0.425 PHI0 " " -0.425 -0.425 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804611 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.248 " "Worst-case hold slack is -0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.248 -0.248 PHI0 " " -0.248 -0.248 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.400 0.000 C25M " " 1.400 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804642 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.412 " "Worst-case recovery slack is -4.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.412 -127.948 C25M " " -4.412 -127.948 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804657 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.858 " "Worst-case removal slack is 4.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.858 0.000 C25M " " 4.858 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906804673 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618906804876 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906804986 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906804986 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:20:05 2021 " "Processing ended: Tue Apr 20 04:20:05 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906805220 ""}

BIN
cpld/db/GR8RAM.sta.rdb
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BIN
cpld/db/GR8RAM.sta_cmp.5_slow.tdb
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8
cpld/db/GR8RAM.tmw_info
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@ -1,6 +1,6 @@
start_full_compilation:s:00:00:32
start_analysis_synthesis:s:00:00:10-start_full_compilation
start_full_compilation:s:00:00:28
start_analysis_synthesis:s:00:00:07-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:12-start_full_compilation
start_fitter:s:00:00:10-start_full_compilation
start_assembler:s:00:00:04-start_full_compilation
start_timing_analyzer:s:00:00:06-start_full_compilation
start_timing_analyzer:s:00:00:07-start_full_compilation

BIN
cpld/db/GR8RAM.vpr.ammdb
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193
cpld/db/prev_cmp_GR8RAM.qmsg
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@ -1,98 +1,95 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911181095 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911181095 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:33:00 2021 " "Processing started: Tue Apr 20 05:33:00 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911181095 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618911181095 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618911181095 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618911183252 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618911183548 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618911183564 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618911183564 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618911183564 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618911183673 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618911183689 "|GR8RAM"}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618911185064 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618911185455 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618911185455 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618911185861 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618911185908 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618911185908 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618911185908 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618911185908 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618911185908 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618911186236 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "314 " "Peak virtual memory: 314 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911186423 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:33:06 2021 " "Processing ended: Tue Apr 20 05:33:06 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911186423 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911186423 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911186423 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911186423 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618911189470 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911189486 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:33:08 2021 " "Processing started: Tue Apr 20 05:33:08 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911189486 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618911189486 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618911189486 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618911189689 ""}
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618911189689 ""}
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618911189689 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618911190392 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618911190408 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618911191501 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618911191501 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618911192033 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618911192048 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618911192470 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618911192470 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 80 " "No exact pin location assignment(s) for 1 pins of 80 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SA\[9\] " "Pin SA\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { SA[9] } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "SA\[9\]" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 436 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { SA[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 258 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1618911192486 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1618911192486 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618911192642 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618911192642 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618911192642 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618911192642 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911192658 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911192658 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911192658 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618911192658 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618911192658 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618911192658 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618911192658 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618911192658 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911192689 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618911192689 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618911192689 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911192689 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 461 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618911192689 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618911192689 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618911192689 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618911192705 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618911192751 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618911192845 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618911192861 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618911192861 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618911192861 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1618911192876 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1618911192876 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1618911192876 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618911192892 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 41 1 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1618911192892 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1618911192892 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1618911192892 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911192923 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618911193251 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911193611 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618911193626 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618911195095 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911195095 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618911195142 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "35 " "Router estimated average interconnect usage is 35% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "35 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618911195579 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618911195579 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911196642 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618911196673 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618911196673 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618911196689 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618911196986 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911197283 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:33:17 2021 " "Processing ended: Tue Apr 20 05:33:17 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911197283 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911197283 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911197283 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618911197283 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618911200033 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911200048 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:33:19 2021 " "Processing started: Tue Apr 20 05:33:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911200048 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618911200048 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618911200048 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618911201251 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618911201283 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911201876 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:33:21 2021 " "Processing ended: Tue Apr 20 05:33:21 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911201876 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911201876 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911201876 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618911201876 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618911202783 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618911204829 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618911204829 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 05:33:23 2021 " "Processing started: Tue Apr 20 05:33:23 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618911204829 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618911204829 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618911204829 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618911205001 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618911205939 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618911206126 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618911206126 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618911206376 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618911206923 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618911207126 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618911207142 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207158 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207158 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207158 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618911207173 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618911207298 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.419 " "Worst-case setup slack is -9.419" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.419 -693.423 C25M " " -9.419 -693.423 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.996 -0.996 PHI0 " " -0.996 -0.996 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207329 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.373 " "Worst-case hold slack is -0.373" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.373 -0.373 PHI0 " " -0.373 -0.373 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.394 0.000 C25M " " 1.394 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207345 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.404 " "Worst-case recovery slack is -4.404" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.404 -127.716 C25M " " -4.404 -127.716 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.850 " "Worst-case removal slack is 4.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.850 0.000 C25M " " 4.850 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207376 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618911207392 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618911207642 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618911207783 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618911207783 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618911208095 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 05:33:28 2021 " "Processing ended: Tue Apr 20 05:33:28 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618911208095 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618911208095 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618911208095 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911208095 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 19 s " "Quartus II Full Compilation was successful. 0 errors, 19 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618911209392 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906713072 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:32 2021 " "Processing started: Tue Apr 20 04:18:32 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906713088 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906714666 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(106) " "Verilog HDL warning at GR8RAM.v(106): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 106 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906714838 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "GR8RAM.v(282) " "Verilog HDL warning at GR8RAM.v(282): extended using \"x\" or \"z\"" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 282 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1618906714854 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gr8ram.v 1 1 " "Found 1 design units, including 1 entities, in source file gr8ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 GR8RAM " "Found entity 1: GR8RAM" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1618906714854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1618906714854 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GR8RAM " "Elaborating entity \"GR8RAM\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1618906714979 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 GR8RAM.v(42) " "Verilog HDL assignment warning at GR8RAM.v(42): truncated value with size 32 to match size of target (4)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 42 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 GR8RAM.v(47) " "Verilog HDL assignment warning at GR8RAM.v(47): truncated value with size 32 to match size of target (14)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(130) " "Verilog HDL assignment warning at GR8RAM.v(130): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 130 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(138) " "Verilog HDL assignment warning at GR8RAM.v(138): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 138 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714979 "|GR8RAM"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 GR8RAM.v(145) " "Verilog HDL assignment warning at GR8RAM.v(145): truncated value with size 32 to match size of target (8)" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 145 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1618906714994 "|GR8RAM"}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 area 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"area\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" { } { } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 -1 1618906716541 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "nNMIout VCC " "Pin \"nNMIout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 553 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nNMIout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nIRQout VCC " "Pin \"nIRQout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 556 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nIRQout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nRDYout VCC " "Pin \"nRDYout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 555 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nRDYout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nINHout VCC " "Pin \"nINHout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 554 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nINHout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RWout VCC " "Pin \"RWout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 557 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|RWout"} { "Warning" "WMLS_MLS_STUCK_PIN" "nDMAout VCC " "Pin \"nDMAout\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 552 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|nDMAout"} { "Warning" "WMLS_MLS_STUCK_PIN" "RAdir VCC " "Pin \"RAdir\" is stuck at VCC" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 551 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1618906716822 "|GR8RAM|RAdir"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1618906716822 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 " "1 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 -1 1618906717276 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "321 " "Implemented 321 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "17 " "Implemented 17 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1618906717307 ""} { "Info" "ICUT_CUT_TM_LCELLS" "241 " "Implemented 241 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1618906717307 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1618906717307 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1618906717510 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "301 " "Peak virtual memory: 301 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:37 2021 " "Processing ended: Tue Apr 20 04:18:37 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906717666 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1618906720682 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906720698 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:39 2021 " "Processing started: Tue Apr 20 04:18:39 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906720698 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1618906720698 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_fit --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1618906720698 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1618906720885 ""}
{ "Info" "0" "" "Project = GR8RAM" { } { } 0 0 "Project = GR8RAM" 0 0 "Fitter" 0 0 1618906720885 ""}
{ "Info" "0" "" "Revision = GR8RAM" { } { } 0 0 "Revision = GR8RAM" 0 0 "Fitter" 0 0 1618906720885 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1618906721651 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "GR8RAM EPM240T100C5 " "Selected device EPM240T100C5 for design \"GR8RAM\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1618906721682 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906721948 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1618906721948 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1618906722260 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1618906722307 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1618906722666 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1618906722666 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1618906722838 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1618906722854 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1618906722885 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1618906722885 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 2 clocks " "Found 2 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 C25M " " 1.000 C25M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI0 " " 1.000 PHI0" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1618906722932 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1618906722932 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906722932 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1618906722948 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906722948 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C25M Global clock in PIN 64 " "Automatically promoted signal \"C25M\" to use Global clock in PIN 64" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722979 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI0 Global clock " "Automatically promoted some destinations of signal \"PHI0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~1 " "Destination \"comb~1\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906722979 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI0r1 " "Destination \"PHI0r1\" may be non-global or may not use global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 10 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1618906722979 ""} } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722979 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI0 " "Pin \"PHI0\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI0 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI0" } } } } { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 9 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 0 { 0 ""} 0 380 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1618906722979 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRESr Global clock " "Automatically promoted signal \"nRESr\" to use Global clock" { } { { "GR8RAM.v" "" { Text "Z:/Repos/GR8RAM/cpld/GR8RAM.v" 16 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1618906722995 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1618906722995 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1618906722995 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1618906723026 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1618906723073 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1618906723088 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1618906723088 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1618906723088 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906723135 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1618906723307 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906723667 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1618906723682 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1618906725120 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906725135 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1618906725214 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "36 " "Router estimated average interconnect usage is 36% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/GR8RAM/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1618906725682 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1618906725682 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906726260 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.67 " "Total time spent on timing analysis during the Fitter is 0.67 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1618906726276 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1618906726276 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1618906726307 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg " "Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1618906726589 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "382 " "Peak virtual memory: 382 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:46 2021 " "Processing ended: Tue Apr 20 04:18:46 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906726823 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1618906726823 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1618906729714 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906729714 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:49 2021 " "Processing started: Tue Apr 20 04:18:49 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906729714 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1618906729714 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1618906729714 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1618906730948 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1618906730979 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "293 " "Peak virtual memory: 293 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:51 2021 " "Processing ended: Tue Apr 20 04:18:51 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906731745 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1618906731745 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1618906732667 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1618906734839 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 20 04:18:53 2021 " "Processing started: Tue Apr 20 04:18:53 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GR8RAM -c GR8RAM " "Command: quartus_sta GR8RAM -c GR8RAM" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1618906734839 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1618906735042 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1618906735948 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906736105 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1618906736105 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1618906736308 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1618906737074 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GR8RAM.sdc " "Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1618906737308 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name C25M C25M " "create_clock -period 1.000 -name C25M C25M" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI0 PHI0 " "create_clock -period 1.000 -name PHI0 PHI0" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737308 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1618906737324 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1618906737495 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -9.005 " "Worst-case setup slack is -9.005" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.005 -699.357 C25M " " -9.005 -699.357 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.425 -0.425 PHI0 " " -0.425 -0.425 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737495 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.248 " "Worst-case hold slack is -0.248" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.248 -0.248 PHI0 " " -0.248 -0.248 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.400 0.000 C25M " " 1.400 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737527 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -4.412 " "Worst-case recovery slack is -4.412" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.412 -127.948 C25M " " -4.412 -127.948 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737542 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 4.858 " "Worst-case removal slack is 4.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.858 0.000 C25M " " 4.858 0.000 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737558 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.289 " "Worst-case minimum pulse width slack is -2.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 C25M " " -2.289 -2.289 C25M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI0 " " -2.289 -2.289 PHI0 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1618906737589 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1618906738136 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906738246 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1618906738246 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "278 " "Peak virtual memory: 278 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 20 04:18:58 2021 " "Processing ended: Tue Apr 20 04:18:58 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906738496 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 18 s " "Quartus II Full Compilation was successful. 0 errors, 18 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1618906739949 ""}

BIN
cpld/incremental_db/compiled_partitions/GR8RAM.root_partition.map.kpt
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Binary file not shown.

14
cpld/output_files/GR8RAM.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for GR8RAM
Tue Apr 20 05:43:03 2021
Tue Apr 20 04:19:58 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Apr 20 05:43:03 2021 ;
; Assembler Status ; Successful - Tue Apr 20 04:19:58 2021 ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX II ;
@ -90,8 +90,8 @@ applicable agreement for further details.
; Option ; Setting ;
+----------------+-------------------------------------------------------+
; Device ; EPM240T100C5 ;
; JTAG usercode ; 0x0016305B ;
; Checksum ; 0x001633DB ;
; JTAG usercode ; 0x001644CE ;
; Checksum ; 0x0016484E ;
+----------------+-------------------------------------------------------+
@ -101,14 +101,14 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Apr 20 05:43:02 2021
Info: Processing started: Tue Apr 20 04:19:56 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GR8RAM -c GR8RAM
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 293 megabytes
Info: Processing ended: Tue Apr 20 05:43:04 2021
Info: Elapsed time: 00:00:02
Info: Processing ended: Tue Apr 20 04:19:59 2021
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02

2
cpld/output_files/GR8RAM.done
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@ -1 +1 @@
Tue Apr 20 05:43:10 2021
Tue Apr 20 04:20:06 2021

533
cpld/output_files/GR8RAM.fit.rpt
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@ -1,5 +1,5 @@
Fitter report for GR8RAM
Tue Apr 20 05:42:59 2021
Tue Apr 20 04:19:53 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -57,7 +57,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Tue Apr 20 05:42:59 2021 ;
; Fitter Status ; Successful - Tue Apr 20 04:19:53 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -128,12 +128,12 @@ applicable agreement for further details.
; Number detected on machine ; 2 ;
; Maximum allowed ; 2 ;
; ; ;
; Average used ; 1.50 ;
; Average used ; 1.20 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 50.0% ;
; Processor 2 ; 20.0% ;
+----------------------------+-------------+
@ -179,8 +179,8 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
; UFM blocks ; 0 / 1 ( 0 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 45% / 50% / 40% ;
; Peak interconnect usage (total/H/V) ; 45% / 50% / 40% ;
; Average interconnect usage (total/H/V) ; 44% / 49% / 38% ;
; Peak interconnect usage (total/H/V) ; 44% / 49% / 38% ;
; Maximum fan-out ; 106 ;
; Highest non-global fan-out ; 45 ;
; Total fan-out ; 1050 ;
@ -188,40 +188,40 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+---------------------------------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+
; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 106 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3V Schmitt Trigger Input ; User ;
; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3V Schmitt Trigger Input ; User ;
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3-V LVTTL ; User ;
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3V Schmitt Trigger Input ; User ;
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ;
; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; On ; 3.3V Schmitt Trigger Input ; User ;
; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; yes ; Off ; 3.3V Schmitt Trigger Input ; User ;
; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+----------------------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; C25M ; 64 ; 2 ; 8 ; 3 ; 4 ; 106 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; DMAin ; 48 ; 1 ; 6 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; INTin ; 49 ; 1 ; 7 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; MISO ; 16 ; 1 ; 1 ; 2 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; PHI0 ; 41 ; 1 ; 5 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[0] ; 100 ; 2 ; 2 ; 5 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[10] ; 14 ; 1 ; 1 ; 2 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[11] ; 34 ; 1 ; 3 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[12] ; 35 ; 1 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[13] ; 36 ; 1 ; 4 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[14] ; 37 ; 1 ; 4 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[15] ; 38 ; 1 ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[1] ; 98 ; 2 ; 2 ; 5 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[2] ; 97 ; 2 ; 3 ; 5 ; 3 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[3] ; 4 ; 1 ; 1 ; 4 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[4] ; 1 ; 2 ; 2 ; 5 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[5] ; 2 ; 1 ; 1 ; 4 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[6] ; 3 ; 1 ; 1 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[7] ; 6 ; 1 ; 1 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[8] ; 7 ; 1 ; 1 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; RA[9] ; 8 ; 1 ; 1 ; 3 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; SetFW[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; SetFW[1] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; nDEVSEL ; 40 ; 1 ; 5 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; nIOSEL ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; nIOSTRB ; 42 ; 1 ; 5 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; nRES ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
; nWE ; 43 ; 1 ; 6 ; 0 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; User ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@ -229,41 +229,41 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[10] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[11] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[12] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SA[9] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; Fitter ; 10 pF ; - ; - ;
; SBA[0] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; SBA[1] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; - ; - ;
; DMAout ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; DQMH ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; DQML ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; FCK ; 12 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; yes ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; INTout ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RAdir ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RCKE ; 66 ; 2 ; 8 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RDdir ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RWout ; 33 ; 1 ; 3 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[0] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[10] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; SA[11] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[12] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[1] ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[2] ; 82 ; 2 ; 6 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[3] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[4] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[5] ; 83 ; 2 ; 6 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[6] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[7] ; 78 ; 2 ; 7 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[8] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SA[9] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SBA[0] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; SBA[1] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; nCAS ; 61 ; 2 ; 8 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nDMAout ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nFCS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nINHout ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nIRQout ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nNMIout ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRAS ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRCS ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRDYout ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nRESout ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; nSWE ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -272,23 +272,23 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; MOSIOE ; - ;
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; comb~1 ; - ;
; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 8mA ; yes ; User ; 10 pF ; SDOE ; - ;
; MOSI ; 15 ; 1 ; 1 ; 2 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; yes ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; MOSIOE ; - ;
; RD[0] ; 86 ; 2 ; 5 ; 5 ; 1 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[1] ; 87 ; 2 ; 5 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[2] ; 88 ; 2 ; 5 ; 5 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[4] ; 90 ; 2 ; 4 ; 5 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[6] ; 92 ; 2 ; 3 ; 5 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; RD[7] ; 99 ; 2 ; 2 ; 5 ; 1 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; comb~1 ; - ;
; SD[0] ; 50 ; 1 ; 7 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[1] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[2] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[3] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[4] ; 51 ; 1 ; 7 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[5] ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; SDOE ; - ;
; SD[6] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
; SD[7] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; SDOE ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -302,112 +302,112 @@ The pin-out file can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.pin.
+----------+-------------------+---------------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 6 ; 4 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 7 ; 5 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 8 ; 6 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 14 ; 8 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 16 ; 10 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 18 ; 12 ; 1 ; DMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 19 ; 13 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 20 ; 14 ; 1 ; INTout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 21 ; 15 ; 1 ; nDMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 33 ; 25 ; 1 ; RWout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 34 ; 26 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 35 ; 27 ; 1 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 36 ; 28 ; 1 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 37 ; 29 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 38 ; 30 ; 1 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 39 ; 31 ; 1 ; nIOSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 40 ; 32 ; 1 ; nDEVSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 41 ; 33 ; 1 ; PHI0 ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; Off ;
; 42 ; 34 ; 1 ; nIOSTRB ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 43 ; 35 ; 1 ; nWE ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 44 ; 36 ; 1 ; nRES ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; yes ; Off ;
; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 47 ; 37 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 48 ; 38 ; 1 ; DMAin ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; yes ; Off ;
; 49 ; 39 ; 1 ; INTin ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; yes ; Off ;
; 50 ; 40 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 51 ; 41 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 53 ; 43 ; 2 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 54 ; 44 ; 2 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 55 ; 45 ; 2 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 56 ; 46 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 57 ; 47 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 61 ; 49 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 62 ; 50 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 64 ; 51 ; 2 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 67 ; 53 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 68 ; 54 ; 2 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 69 ; 55 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 70 ; 56 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 71 ; 57 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
; 72 ; 58 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 73 ; 59 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 74 ; 60 ; 2 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 75 ; 61 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 76 ; 62 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 77 ; 63 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; 64 ; 2 ; SA[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 81 ; 65 ; 2 ; SA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 82 ; 66 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 83 ; 67 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 84 ; 68 ; 2 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 85 ; 69 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 86 ; 70 ; 2 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 87 ; 71 ; 2 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 88 ; 72 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 90 ; 74 ; 2 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 92 ; 76 ; 2 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 95 ; 77 ; 2 ; SetFW[1] ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; On ;
; 96 ; 78 ; 2 ; SetFW[0] ; input ; 3.3V Schmitt Trigger Input ; ; Column I/O ; Y ; no ; On ;
; 97 ; 79 ; 2 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 98 ; 80 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 99 ; 81 ; 2 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; yes ; Off ;
; 100 ; 82 ; 2 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+----------+------------+----------+----------------+--------+----------------------------+-----------+------------+-----------------+----------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
; 1 ; 83 ; 2 ; RA[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 2 ; 0 ; 1 ; RA[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 3 ; 1 ; 1 ; RA[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 4 ; 2 ; 1 ; RA[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 5 ; 3 ; 1 ; nFCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 6 ; 4 ; 1 ; RA[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 7 ; 5 ; 1 ; RA[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 8 ; 6 ; 1 ; RA[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 12 ; 7 ; 1 ; FCK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 14 ; 8 ; 1 ; RA[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 15 ; 9 ; 1 ; MOSI ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; yes ; Off ;
; 16 ; 10 ; 1 ; MISO ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 17 ; 11 ; 1 ; RDdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 18 ; 12 ; 1 ; DMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 19 ; 13 ; 1 ; RAdir ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 20 ; 14 ; 1 ; INTout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 21 ; 15 ; 1 ; nDMAout ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
; 26 ; 20 ; 1 ; nNMIout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 27 ; 21 ; 1 ; nINHout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 28 ; 22 ; 1 ; nRDYout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 29 ; 23 ; 1 ; nIRQout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 30 ; 24 ; 1 ; nRESout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 33 ; 25 ; 1 ; RWout ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 34 ; 26 ; 1 ; RA[11] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 35 ; 27 ; 1 ; RA[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 36 ; 28 ; 1 ; RA[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 37 ; 29 ; 1 ; RA[14] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 38 ; 30 ; 1 ; RA[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 39 ; 31 ; 1 ; nIOSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 40 ; 32 ; 1 ; nDEVSEL ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 41 ; 33 ; 1 ; PHI0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 42 ; 34 ; 1 ; nIOSTRB ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 43 ; 35 ; 1 ; nWE ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 44 ; 36 ; 1 ; nRES ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 47 ; 37 ; 1 ; SD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; DMAin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; INTin ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; SD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; SD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; SD[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; SD[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; SD[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; SD[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 56 ; 46 ; 2 ; SD[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; DQMH ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; nSWE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 61 ; 49 ; 2 ; nCAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 62 ; 50 ; 2 ; nRAS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
; 64 ; 51 ; 2 ; C25M ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
; 66 ; 52 ; 2 ; RCKE ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 67 ; 53 ; 2 ; nRCS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 68 ; 54 ; 2 ; SA[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 69 ; 55 ; 2 ; SBA[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 70 ; 56 ; 2 ; SA[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 71 ; 57 ; 2 ; SBA[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 72 ; 58 ; 2 ; SA[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 73 ; 59 ; 2 ; SA[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 74 ; 60 ; 2 ; SA[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ;
; 75 ; 61 ; 2 ; SA[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 76 ; 62 ; 2 ; SA[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 77 ; 63 ; 2 ; SA[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 78 ; 64 ; 2 ; SA[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 81 ; 65 ; 2 ; SA[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 82 ; 66 ; 2 ; SA[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 83 ; 67 ; 2 ; SA[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 84 ; 68 ; 2 ; SA[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 85 ; 69 ; 2 ; DQML ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 86 ; 70 ; 2 ; RD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 87 ; 71 ; 2 ; RD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 88 ; 72 ; 2 ; RD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 90 ; 74 ; 2 ; RD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 91 ; 75 ; 2 ; RD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 92 ; 76 ; 2 ; RD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 95 ; 77 ; 2 ; SetFW[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 96 ; 78 ; 2 ; SetFW[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 97 ; 79 ; 2 ; RA[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 98 ; 80 ; 2 ; RA[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 99 ; 81 ; 2 ; RD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
; 100 ; 82 ; 2 ; RA[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ;
+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@ -531,22 +531,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
; C25M ; PIN_64 ; 106 ; Clock ; yes ; Global Clock ; GCLK3 ;
; Decoder1~0 ; LC_X6_Y3_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal2~0 ; LC_X3_Y2_N9 ; 19 ; Clock enable ; no ; -- ; -- ;
; FCKOE ; LC_X2_Y2_N4 ; 2 ; Output enable ; no ; -- ; -- ;
; IOROMRES ; LC_X2_Y3_N1 ; 1 ; Async. clear ; no ; -- ; -- ;
; MOSIOE ; LC_X2_Y2_N6 ; 1 ; Output enable ; no ; -- ; -- ;
; Decoder1~0 ; LC_X4_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal2~0 ; LC_X3_Y2_N8 ; 19 ; Clock enable ; no ; -- ; -- ;
; FCKOE ; LC_X6_Y4_N4 ; 2 ; Output enable ; no ; -- ; -- ;
; IOROMRES ; LC_X2_Y3_N8 ; 1 ; Async. clear ; no ; -- ; -- ;
; MOSIOE ; LC_X6_Y4_N0 ; 1 ; Output enable ; no ; -- ; -- ;
; PHI0 ; PIN_41 ; 5 ; Clock ; yes ; Global Clock ; GCLK1 ;
; PS[0] ; LC_X3_Y2_N5 ; 44 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ;
; PS[2] ; LC_X3_Y2_N7 ; 26 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; SDOE ; LC_X4_Y1_N7 ; 8 ; Output enable ; no ; -- ; -- ;
; SetFWLoaded ; LC_X3_Y2_N6 ; 2 ; Clock enable ; no ; -- ; -- ;
; always7~1 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; always9~2 ; LC_X4_Y2_N8 ; 8 ; Sync. load ; no ; -- ; -- ;
; always9~3 ; LC_X5_Y2_N8 ; 9 ; Sync. load ; no ; -- ; -- ;
; always9~4 ; LC_X5_Y2_N9 ; 9 ; Sync. load ; no ; -- ; -- ;
; comb~1 ; LC_X4_Y1_N3 ; 9 ; Output enable ; no ; -- ; -- ;
; nRESr ; LC_X2_Y3_N6 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ;
; PS[0] ; LC_X4_Y2_N2 ; 44 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ;
; PS[2] ; LC_X4_Y2_N7 ; 26 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; SDOE ; LC_X4_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ;
; SetFWLoaded ; LC_X4_Y2_N6 ; 2 ; Clock enable ; no ; -- ; -- ;
; always7~1 ; LC_X2_Y3_N1 ; 2 ; Clock enable ; no ; -- ; -- ;
; always9~2 ; LC_X2_Y2_N9 ; 8 ; Sync. load ; no ; -- ; -- ;
; always9~3 ; LC_X2_Y1_N8 ; 9 ; Sync. load ; no ; -- ; -- ;
; always9~4 ; LC_X7_Y2_N8 ; 9 ; Sync. load ; no ; -- ; -- ;
; comb~1 ; LC_X5_Y1_N6 ; 9 ; Output enable ; no ; -- ; -- ;
; nRESr ; LC_X2_Y3_N4 ; 29 ; Async. clear ; yes ; Global Clock ; GCLK2 ;
+-------------+-------------+---------+---------------------------------------+--------+----------------------+------------------+
@ -557,7 +557,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------+-------------+---------+----------------------+------------------+
; C25M ; PIN_64 ; 106 ; Global Clock ; GCLK3 ;
; PHI0 ; PIN_41 ; 5 ; Global Clock ; GCLK1 ;
; nRESr ; LC_X2_Y3_N6 ; 29 ; Global Clock ; GCLK2 ;
; nRESr ; LC_X2_Y3_N4 ; 29 ; Global Clock ; GCLK2 ;
+-------+-------------+---------+----------------------+------------------+
@ -917,13 +917,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------+--------------------+
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
; C4s ; 259 / 784 ( 33 % ) ;
; Direct links ; 56 / 888 ( 6 % ) ;
; C4s ; 234 / 784 ( 30 % ) ;
; Direct links ; 69 / 888 ( 8 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; LAB clocks ; 11 / 32 ( 34 % ) ;
; LUT chains ; 35 / 216 ( 16 % ) ;
; Local interconnects ; 435 / 888 ( 49 % ) ;
; R4s ; 290 / 704 ( 41 % ) ;
; LAB clocks ; 12 / 32 ( 38 % ) ;
; LUT chains ; 39 / 216 ( 18 % ) ;
; Local interconnects ; 436 / 888 ( 49 % ) ;
; R4s ; 282 / 704 ( 40 % ) ;
+-----------------------------+--------------------+
@ -939,22 +939,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 4 ;
; 9 ; 2 ;
; 10 ; 18 ;
; 8 ; 3 ;
; 9 ; 4 ;
; 10 ; 17 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 2.04) ; Number of LABs (Total = 24) ;
; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 7 ;
; 1 Clock ; 22 ;
; 1 Clock enable ; 7 ;
; 1 Sync. clear ; 6 ;
; 1 Sync. load ; 5 ;
; 1 Clock enable ; 6 ;
; 1 Sync. clear ; 4 ;
; 1 Sync. load ; 2 ;
; 2 Clock enables ; 1 ;
; 2 Clocks ; 2 ;
+------------------------------------+------------------------------+
@ -972,11 +973,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 4 ;
; 9 ; 2 ;
; 8 ; 3 ;
; 9 ; 4 ;
; 10 ; 12 ;
; 11 ; 4 ;
; 12 ; 1 ;
; 11 ; 2 ;
; 12 ; 2 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
@ -986,19 +987,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.00) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced Out (Average = 6.92) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 5 ;
; 5 ; 1 ;
; 3 ; 3 ;
; 4 ; 4 ;
; 5 ; 2 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 5 ;
; 9 ; 6 ;
; 10 ; 2 ;
; 7 ; 1 ;
; 8 ; 3 ;
; 9 ; 3 ;
; 10 ; 5 ;
; 11 ; 1 ;
+-------------------------------------------------+------------------------------+
@ -1006,31 +1007,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 15.96) ; Number of LABs (Total = 24) ;
; Number of Distinct Inputs (Average = 15.54) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 3 ;
; 12 ; 3 ;
; 13 ; 2 ;
; 14 ; 2 ;
; 15 ; 2 ;
; 16 ; 3 ;
; 17 ; 0 ;
; 18 ; 2 ;
; 19 ; 1 ;
; 20 ; 2 ;
; 15 ; 3 ;
; 16 ; 2 ;
; 17 ; 2 ;
; 18 ; 1 ;
; 19 ; 2 ;
; 20 ; 1 ;
; 21 ; 4 ;
; 22 ; 1 ;
+----------------------------------------------+------------------------------+
@ -1064,8 +1064,6 @@ Info (176444): Device migration not selected. If you intend to use device migrat
Info (176445): Device EPM570T100C5 is compatible
Info (176445): Device EPM570T100I5 is compatible
Info (176445): Device EPM570T100A5 is compatible
Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 80 total pins
Info (169086): Pin SA[9] not assigned to an exact location on the device
Critical Warning (332012): Synopsys Design Constraints File file not found: 'GR8RAM.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332144): No user constrained base clocks found in the design
Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
@ -1087,32 +1085,25 @@ Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
Info (176212): I/O standards used: 3.3-V LVTTL.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
Info (176213): I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available
Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used -- 1 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 35% of the available device resources
Info (170196): Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170195): Router estimated average interconnect usage is 36% of the available device resources
Info (170196): Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.70 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.56 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.fit.smsg
Info: Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 378 megabytes
Info: Processing ended: Tue Apr 20 05:42:59 2021
Info: Elapsed time: 00:00:09
Info: Total CPU time (on all processors): 00:00:09
Info: Quartus II 32-bit Fitter was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 382 megabytes
Info: Processing ended: Tue Apr 20 04:19:53 2021
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:08
+----------------------------+

2
cpld/output_files/GR8RAM.fit.summary
View File

@ -1,4 +1,4 @@
Fitter Status : Successful - Tue Apr 20 05:42:59 2021
Fitter Status : Successful - Tue Apr 20 04:19:53 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM

18
cpld/output_files/GR8RAM.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for GR8RAM
Tue Apr 20 05:43:09 2021
Tue Apr 20 04:20:05 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,7 +40,7 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Apr 20 05:43:03 2021 ;
; Flow Status ; Successful - Tue Apr 20 04:19:58 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -59,7 +59,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/20/2021 05:42:44 ;
; Start date & time ; 04/20/2021 04:19:41 ;
; Main task ; Compilation ;
; Revision Name ; GR8RAM ;
+-------------------+---------------------+
@ -75,7 +75,7 @@ applicable agreement for further details.
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
; AUTO_PACKED_REGISTERS_MAXII ; Minimize Area ; Auto ; -- ; -- ;
; AUTO_RESOURCE_SHARING ; On ; Off ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 44085571633675.161891176303636 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 44085571633675.161890678100176 ; -- ; -- ; -- ;
; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IOBANK_VCCIO ; 3.3V ; -- ; -- ; 1 ;
@ -102,11 +102,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 301 MB ; 00:00:06 ;
; Fitter ; 00:00:09 ; 1.5 ; 378 MB ; 00:00:08 ;
; Assembler ; 00:00:01 ; 1.0 ; 292 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.0 ; 275 MB ; 00:00:04 ;
; Total ; 00:00:20 ; -- ; -- ; 00:00:20 ;
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 301 MB ; 00:00:04 ;
; Fitter ; 00:00:08 ; 1.2 ; 382 MB ; 00:00:07 ;
; Assembler ; 00:00:02 ; 1.0 ; 292 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 278 MB ; 00:00:04 ;
; Total ; 00:00:20 ; -- ; -- ; 00:00:17 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+

12
cpld/output_files/GR8RAM.map.rpt
View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for GR8RAM
Tue Apr 20 05:42:47 2021
Tue Apr 20 04:19:44 2021
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -45,7 +45,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Apr 20 05:42:47 2021 ;
; Analysis & Synthesis Status ; Successful - Tue Apr 20 04:19:44 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
@ -280,7 +280,7 @@ Encoding Type: Minimal Bits
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Apr 20 05:42:41 2021
Info: Processing started: Tue Apr 20 04:19:39 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
@ -309,9 +309,9 @@ Info (21057): Implemented 321 device resources after synthesis - the final resou
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 13 warnings
Info: Peak virtual memory: 301 megabytes
Info: Processing ended: Tue Apr 20 05:42:47 2021
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:06
Info: Processing ended: Tue Apr 20 04:19:44 2021
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:04
+------------------------------------------+

2
cpld/output_files/GR8RAM.map.summary
View File

@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Tue Apr 20 05:42:47 2021
Analysis & Synthesis Status : Successful - Tue Apr 20 04:19:44 2021
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : GR8RAM
Top-level Entity Name : GR8RAM

24
cpld/output_files/GR8RAM.pin
View File

@ -102,15 +102,15 @@ RA[14] : 37 : input : 3.3-V LVTTL :
RA[15] : 38 : input : 3.3-V LVTTL : : 1 : Y
nIOSEL : 39 : input : 3.3-V LVTTL : : 1 : Y
nDEVSEL : 40 : input : 3.3-V LVTTL : : 1 : Y
PHI0 : 41 : input : 3.3V Schmitt Trigger Input : : 1 : Y
PHI0 : 41 : input : 3.3-V LVTTL : : 1 : Y
nIOSTRB : 42 : input : 3.3-V LVTTL : : 1 : Y
nWE : 43 : input : 3.3-V LVTTL : : 1 : Y
nRES : 44 : input : 3.3V Schmitt Trigger Input : : 1 : Y
nRES : 44 : input : 3.3-V LVTTL : : 1 : Y
VCCIO1 : 45 : power : : 3.3V : 1 :
GNDIO : 46 : gnd : : : :
SD[1] : 47 : bidir : 3.3-V LVTTL : : 1 : Y
DMAin : 48 : input : 3.3V Schmitt Trigger Input : : 1 : Y
INTin : 49 : input : 3.3V Schmitt Trigger Input : : 1 : Y
DMAin : 48 : input : 3.3-V LVTTL : : 1 : Y
INTin : 49 : input : 3.3-V LVTTL : : 1 : Y
SD[0] : 50 : bidir : 3.3-V LVTTL : : 1 : Y
SD[4] : 51 : bidir : 3.3-V LVTTL : : 1 : Y
SD[5] : 52 : bidir : 3.3-V LVTTL : : 2 : Y
@ -129,12 +129,12 @@ C25M : 64 : input : 3.3-V LVTTL :
GNDINT : 65 : gnd : : : :
RCKE : 66 : output : 3.3-V LVTTL : : 2 : Y
nRCS : 67 : output : 3.3-V LVTTL : : 2 : Y
SBA[0] : 68 : output : 3.3-V LVTTL : : 2 : Y
SBA[1] : 69 : output : 3.3-V LVTTL : : 2 : Y
SA[12] : 70 : output : 3.3-V LVTTL : : 2 : Y
SA[9] : 71 : output : 3.3-V LVTTL : : 2 : N
SA[10] : 72 : output : 3.3-V LVTTL : : 2 : Y
SA[11] : 73 : output : 3.3-V LVTTL : : 2 : Y
SA[12] : 68 : output : 3.3-V LVTTL : : 2 : Y
SBA[0] : 69 : output : 3.3-V LVTTL : : 2 : Y
SA[11] : 70 : output : 3.3-V LVTTL : : 2 : Y
SBA[1] : 71 : output : 3.3-V LVTTL : : 2 : Y
SA[9] : 72 : output : 3.3-V LVTTL : : 2 : Y
SA[10] : 73 : output : 3.3-V LVTTL : : 2 : Y
SA[8] : 74 : output : 3.3-V LVTTL : : 2 : Y
SA[0] : 75 : output : 3.3-V LVTTL : : 2 : Y
SA[4] : 76 : output : 3.3-V LVTTL : : 2 : Y
@ -156,8 +156,8 @@ RD[5] : 91 : bidir : 3.3-V LVTTL :
RD[6] : 92 : bidir : 3.3-V LVTTL : : 2 : Y
GNDIO : 93 : gnd : : : :
VCCIO2 : 94 : power : : 3.3V : 2 :
SetFW[1] : 95 : input : 3.3V Schmitt Trigger Input : : 2 : Y
SetFW[0] : 96 : input : 3.3V Schmitt Trigger Input : : 2 : Y
SetFW[1] : 95 : input : 3.3-V LVTTL : : 2 : Y
SetFW[0] : 96 : input : 3.3-V LVTTL : : 2 : Y
RA[2] : 97 : input : 3.3-V LVTTL : : 2 : Y
RA[1] : 98 : input : 3.3-V LVTTL : : 2 : Y
RD[7] : 99 : bidir : 3.3-V LVTTL : : 2 : Y

BIN
cpld/output_files/GR8RAM.pof
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1524
cpld/output_files/GR8RAM.sta.rpt
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File diff suppressed because it is too large Load Diff

28
cpld/output_files/GR8RAM.sta.summary
View File

@ -3,35 +3,35 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'C25M'
Slack : -9.844
TNS : -724.767
Slack : -9.005
TNS : -699.357
Type : Setup 'PHI0'
Slack : -0.019
TNS : -0.019
Slack : -0.425
TNS : -0.425
Type : Hold 'PHI0'
Slack : -0.952
TNS : -0.952
Slack : -0.248
TNS : -0.248
Type : Hold 'C25M'
Slack : 1.385
Slack : 1.400
TNS : 0.000
Type : Recovery 'C25M'
Slack : -4.389
TNS : -127.281
Slack : -4.412
TNS : -127.948
Type : Removal 'C25M'
Slack : 4.835
Slack : 4.858
TNS : 0.000
Type : Minimum Pulse Width 'PHI0'
Slack : -3.000
TNS : -3.000
Type : Minimum Pulse Width 'C25M'
Slack : -2.289
TNS : -2.289
Type : Minimum Pulse Width 'PHI0'
Slack : -2.289
TNS : -2.289
------------------------------------------------------------