parent
5de2b60317
commit
e66f57ce88
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@ -21,9 +21,17 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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/* Firmware select */
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/* Firmware select */
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input [1:0] SetFW;
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input [1:0] SetFW;
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wire [1:0] SetROM = 2'b00;
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reg [1:0] SetFWr;
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wire SetEN16MB = 0;
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reg SetFWLoaded = 0;
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wire SetEN24bit = 1;
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always @(posedge C25M) begin
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if (~SetFWLoaded) begin
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SetFWLoaded <= 1;
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SetFWr[1:0] <= SetFW[1:0];
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end
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end
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wire [1:0] SetROM = ~SetFWr[1:0];
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wire SetEN16MB = SetROM[1:0]==2'b11;
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wire SetEN24bit = SetROM[1];
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/* State counter from PHI0 rising edge */
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/* State counter from PHI0 rising edge */
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reg [3:0] PS = 0;
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reg [3:0] PS = 0;
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@ -69,8 +77,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
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wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
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wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
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wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
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wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
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wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
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wire SPITX1SpecSEL = REGSpecSEL && RAr[3:0]==4'hD;
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wire SPITX0SpecSEL = REGSpecSEL && RAr[3:0]==4'hC;
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wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
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wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
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wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
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wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
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wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
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wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
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@ -147,19 +153,18 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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/* ROM bank register */
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/* ROM bank register */
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reg Bank = 0;
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reg Bank = 0;
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reg RestoreDone = 0;
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always @(posedge C25M, negedge nRESr) begin
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) Bank <= 0;
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if (~nRESr) Bank <= 0;
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else if (PS==8 && BankSEL && ~nWEr) begin
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else if (PS==8 && BankSEL && ~nWEr) begin
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if (!RestoreDone) begin
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Bank <= RD[0];
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RestoreDone <= RD[1:0]==2'b11;
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end else Bank <= RD[0];
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end
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end
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end
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end
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/* SPI flash control signals */
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/* SPI flash control signals */
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output reg nFCS = 1;
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output nFCS = FCKOE ? ~FCS : 1'bZ;
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output FCK = FCKout;
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reg FCS = 0;
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output FCK = FCKOE ? FCKout : 1'bZ;
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reg FCKOE = 0;
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reg FCKout = 0;
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reg FCKout = 0;
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inout MOSI = MOSIOE ? MOSIout : 1'bZ;
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inout MOSI = MOSIOE ? MOSIout : 1'bZ;
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reg MOSIOE = 0;
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reg MOSIOE = 0;
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@ -181,7 +186,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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end 6: begin // NOP CKE
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end 6: begin // NOP CKE
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FCKout <= 1'b1;
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FCKout <= 1'b1;
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end 7: begin // NOP CKE
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end 7: begin // NOP CKE
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FCKout <= ~(IS==5 || IS==6 || (!nDEVSEL && RestoreDone && (SPITX0SpecSEL || SPITX1SpecSEL)));
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FCKout <= ~(IS==5 || IS==6);
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end 8: begin // WR AP
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end 8: begin // WR AP
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FCKout <= 1'b1;
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FCKout <= 1'b1;
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end 9: begin // NOP CKE
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end 9: begin // NOP CKE
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@ -200,9 +205,9 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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FCKout <= ~(IS==5);
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FCKout <= ~(IS==5);
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end
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end
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endcase
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endcase
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FCS <= IS==4 || IS==5 || IS==6;
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nFCS <= !(IS==4 || IS==5 || IS==6 || Bank);
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MOSIOE <= IS==5;
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MOSIOE <= IS==5 || IS==7;
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FCKOE <= IS==1 || IS==4 || IS==5 || IS==6 || IS==7;
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end
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end
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/* SPI flash MOSI control */
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/* SPI flash MOSI control */
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@ -213,7 +218,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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case (LS[2:0])
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case (LS[2:0])
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3'h3: MOSIout <= 1'b0; // Command bit 7
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3'h3: MOSIout <= 1'b0; // Command bit 7
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3'h4: MOSIout <= 1'b0; // Address bit 23
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3'h4: MOSIout <= 1'b0; // Address bit 23
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3'h5: MOSIout <= 1'b1; // Address bit 15
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3'h5: MOSIout <= 1'b0; // Address bit 15
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3'h6: MOSIout <= 1'b0; // Address bit 7
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3'h6: MOSIout <= 1'b0; // Address bit 7
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default MOSIout <= 1'b0;
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default MOSIout <= 1'b0;
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endcase
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endcase
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@ -234,13 +239,13 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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default MOSIout <= 1'b0;
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default MOSIout <= 1'b0;
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endcase
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endcase
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end 7: begin
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end 7: begin
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if (nRES) case (LS[2:0])
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 4
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3'h3: MOSIout <= 1'b1; // Command bit 4
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3'h4: MOSIout <= 1'b0; // Address bit 20
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3'h4: MOSIout <= 1'b0; // Address bit 20
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3'h5: MOSIout <= 1'b0; // Address bit 12
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3'h5: MOSIout <= 1'b0; // Address bit 12
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3'h6: MOSIout <= 1'b0; // Address bit 4
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3'h6: MOSIout <= 1'b0; // Address bit 4
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default MOSIout <= 1'b0;
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default MOSIout <= 1'b0;
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endcase else MOSIout <= RAr[0];
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endcase
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end 9: begin
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end 9: begin
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case (LS[2:0])
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 3
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3'h3: MOSIout <= 1'b1; // Command bit 3
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@ -325,7 +330,6 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
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if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
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else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
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else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
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else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
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else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
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else if (BankSpecSEL) RDD[7:0] <= { MISO, 7'h7F };
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else RDD[7:0] <= SD[7:0];
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else RDD[7:0] <= SD[7:0];
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end
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end
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end
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end
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@ -450,19 +454,19 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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DQML <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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DQMH <= 1'b1;
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if (IS==6) begin
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if (IS==6) begin
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SBA[1:0] <= 2'b10;
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SBA[1:0] <= { 2'b10 };
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SA[12:0] <= { 10'b0011000100, LS[12:10] };
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SA[12:0] <= { 10'b0011000100, LS[12:10] };
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end else if (RAMSpecSEL) begin
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end else if (RAMSpecSEL) begin
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SBA[1:0] <= { 1'b0, 1'b0 };
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
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SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
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SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
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SA[9:0] <= Addr[19:10];
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SA[9:0] <= Addr[19:10];
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end else begin
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end else begin
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SBA[1:0] <= 2'b10;
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SBA[1:0] <= 2'b10;
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SA[12:0] <= { 10'b0011000100, RestoreDone ? (nIOSEL ? 1'b0 : Bank) : 1'b1, RAr[11:10] };
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SA[12:0] <= { 10'b0011000100, Bank, RAr[11:10] };
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end
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end
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end 2: begin // RD
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end 2: begin // RD
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if (RAMSpecSEL) begin
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if (RAMSpecSEL) begin
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SBA[1:0] <= 2'b00;
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
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SA[12:0] <= { 4'b0011, Addr[9:1] };
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SA[12:0] <= { 4'b0011, Addr[9:1] };
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DQML <= Addr[0];
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DQML <= Addr[0];
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DQMH <= ~Addr[0];
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DQMH <= ~Addr[0];
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@ -504,7 +508,7 @@ module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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DQML <= LS[0];
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DQML <= LS[0];
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DQMH <= ~LS[0];
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DQMH <= ~LS[0];
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end else begin
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end else begin
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SBA[1:0] <= 2'b00;
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SBA[1:0] <= { 1'b0, SetEN24bit ? Addr[23] : 1'b0 };
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SA[12:0] <= { 4'b0011, Addr[9:1] };
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SA[12:0] <= { 4'b0011, Addr[9:1] };
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DQML <= Addr[0];
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DQML <= Addr[0];
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DQMH <= ~Addr[0];
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DQMH <= ~Addr[0];
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