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https://github.com/garrettsworkshop/GR8RAM.git
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Update GR8RAM.qsf
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@ -57,7 +57,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scanset_location_assignment PIN_2 -to RA[5]
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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set_location_assignment PIN_2 -to RA[5]
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set_location_assignment PIN_3 -to RA[6]
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set_location_assignment PIN_3 -to RA[6]
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set_location_assignment PIN_4 -to RA[3]
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set_location_assignment PIN_4 -to RA[3]
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set_location_assignment PIN_5 -to nFCS
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set_location_assignment PIN_5 -to nFCS
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