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Update GR8RAM.qsf

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Zane Kaminski
2023-02-28 11:20:35 -05:00
parent da9197740a
commit eca42a0161
1 changed files with 2 additions and 1 deletions
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cpld2/GR8RAM.qsf
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@@ -57,7 +57,8 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scanset_location_assignment PIN_2 -to RA[5]
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_location_assignment PIN_2 -to RA[5]
set_location_assignment PIN_3 -to RA[6]
set_location_assignment PIN_4 -to RA[3]
set_location_assignment PIN_5 -to nFCS