mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2026-03-12 22:41:44 +00:00
123 lines
3.4 KiB
Plaintext
123 lines
3.4 KiB
Plaintext
[ START MERGED ]
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ic.MISOr.CN CLK
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RDOE_i ram/RDOE
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ic.SetRestoreEN_i ic/SetRestoreEN
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bi.nRESr.CN PHI0_c
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bi/S_i[1] bi/S[1]
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[ END MERGED ]
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[ START CLIPPED ]
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registers/GND
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CLKin_c
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CLKin
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BA_c[11]
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BA[11]
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BA_c[12]
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BA[12]
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BA_c[13]
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BA[13]
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BA_c[14]
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BA[14]
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BA_c[15]
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BA[15]
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registers/un1_Addr_2_s_7_0_S1
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registers/un1_Addr_2_s_7_0_COUT
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registers/un1_Addr_1_cry_0_0_S0
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registers/N_3
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registers/un1_Addr_1_s_7_0_S1
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registers/un1_Addr_1_s_7_0_COUT
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registers/un1_Addr_cry_0_0_S0
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registers/N_4
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registers/un1_Addr_s_7_0_S1
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registers/un1_Addr_s_7_0_COUT
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registers/un1_Addr_2_cry_0_0_S0
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registers/N_2
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ic/un2_LS_1_cry_0_0_S1
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ic/un2_LS_1_cry_0_0_S0
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ic/N_1
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ic/un2_LS_1_cry_11_0_COUT
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ic/un2_CS_cry_0_0_S1
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ic/un2_CS_cry_0_0_S0
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ic/N_2
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ic/un2_CS_cry_11_0_COUT
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OSCH_inst_SEDSTDBY
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[ END CLIPPED ]
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[ START OSC ]
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CLK 44.33
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[ END OSC ]
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[ START DESIGN PREFS ]
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SCHEMATIC START ;
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# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Sun Jul 14 06:18:49 2024
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SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
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LOCATE COMP "BD[0]" SITE "65" ;
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LOCATE COMP "LED" SITE "81" ;
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LOCATE COMP "PHI0" SITE "17" ;
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LOCATE COMP "FCK" SITE "96" ;
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LOCATE COMP "nFCS" SITE "88" ;
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LOCATE COMP "MOSI" SITE "97" ;
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LOCATE COMP "MISO" SITE "98" ;
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LOCATE COMP "RD[7]" SITE "31" ;
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LOCATE COMP "RD[6]" SITE "30" ;
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LOCATE COMP "RD[5]" SITE "29" ;
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LOCATE COMP "RD[4]" SITE "28" ;
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LOCATE COMP "RD[3]" SITE "27" ;
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LOCATE COMP "RD[2]" SITE "21" ;
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LOCATE COMP "RD[1]" SITE "24" ;
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LOCATE COMP "RD[0]" SITE "25" ;
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LOCATE COMP "DQMH" SITE "34" ;
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LOCATE COMP "DQML" SITE "32" ;
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LOCATE COMP "nRWE" SITE "35" ;
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LOCATE COMP "nCAS" SITE "36" ;
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LOCATE COMP "nRAS" SITE "37" ;
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LOCATE COMP "RCKE" SITE "40" ;
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LOCATE COMP "nRCS" SITE "41" ;
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LOCATE COMP "RA[12]" SITE "42" ;
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LOCATE COMP "RA[11]" SITE "45" ;
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LOCATE COMP "RA[10]" SITE "47" ;
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LOCATE COMP "RA[9]" SITE "49" ;
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LOCATE COMP "RA[8]" SITE "53" ;
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LOCATE COMP "RA[7]" SITE "57" ;
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LOCATE COMP "RA[6]" SITE "62" ;
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LOCATE COMP "RA[5]" SITE "52" ;
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LOCATE COMP "RA[4]" SITE "51" ;
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LOCATE COMP "RA[3]" SITE "60" ;
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LOCATE COMP "RA[2]" SITE "58" ;
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LOCATE COMP "RA[1]" SITE "59" ;
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LOCATE COMP "RA[0]" SITE "54" ;
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LOCATE COMP "RBA[1]" SITE "48" ;
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LOCATE COMP "RBA[0]" SITE "43" ;
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LOCATE COMP "RCLK" SITE "39" ;
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LOCATE COMP "nIOSTRB" SITE "18" ;
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LOCATE COMP "nDEVSEL" SITE "16" ;
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LOCATE COMP "nIOSEL" SITE "15" ;
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LOCATE COMP "nDinOE" SITE "77" ;
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LOCATE COMP "nDoutOE" SITE "1" ;
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LOCATE COMP "BD[7]" SITE "75" ;
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LOCATE COMP "BD[6]" SITE "71" ;
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LOCATE COMP "BD[5]" SITE "70" ;
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LOCATE COMP "BD[4]" SITE "69" ;
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LOCATE COMP "BD[3]" SITE "68" ;
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LOCATE COMP "BD[2]" SITE "67" ;
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LOCATE COMP "BD[1]" SITE "66" ;
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LOCATE COMP "nWE" SITE "19" ;
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LOCATE COMP "BA[10]" SITE "3" ;
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LOCATE COMP "BA[9]" SITE "2" ;
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LOCATE COMP "BA[8]" SITE "99" ;
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LOCATE COMP "BA[7]" SITE "87" ;
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LOCATE COMP "BA[6]" SITE "86" ;
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LOCATE COMP "BA[5]" SITE "85" ;
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LOCATE COMP "BA[4]" SITE "4" ;
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LOCATE COMP "BA[3]" SITE "84" ;
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LOCATE COMP "BA[2]" SITE "83" ;
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LOCATE COMP "BA[1]" SITE "78" ;
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LOCATE COMP "BA[0]" SITE "74" ;
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LOCATE COMP "SW[2]" SITE "63" ;
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LOCATE COMP "SW[1]" SITE "64" ;
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LOCATE COMP "nIRQout" SITE "12" ;
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LOCATE COMP "nRESout" SITE "7" ;
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LOCATE COMP "nRESin" SITE "20" ;
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FREQUENCY PORT "PHI0" 1.000000 MHz ;
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FREQUENCY NET "CLK" 44.300000 MHz ;
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SCHEMATIC END ;
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[ END DESIGN PREFS ]
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