2024-06-09 05:17:38 +00:00
|
|
|
<HTML> <HEAD><TITLE></TITLE> <STYLE TYPE="text/css"> <!-- body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00;
|
|
|
|
|
Starting: parse design source files
|
|
|
|
|
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
|
|
|
|
|
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v
|
2024-07-20 11:09:18 +00:00
|
|
|
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(140,9-140,25) (VERI-1362) CmdRWMaskSet is already implicitly declared on line 131
|
|
|
|
|
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(141,9-141,22) (VERI-1362) CmdLEDSet is already implicitly declared on line 131
|
2024-06-09 05:17:38 +00:00
|
|
|
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v
|
|
|
|
|
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/REFB.v
|
|
|
|
|
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-OFF.v
|
|
|
|
|
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module RAM2E
|
2024-07-20 11:09:18 +00:00
|
|
|
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-476,10) (VERI-9000) elaborating module 'RAM2E'
|
2024-06-09 05:17:38 +00:00
|
|
|
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-335,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
|
|
|
|
|
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-OFF.v(1,1-1,68) (VERI-9000) elaborating module 'DHGR_uniq_1'
|
|
|
|
|
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
|
|
|
|
|
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
|
|
|
|
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
|
|
|
|
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
|
2024-07-20 11:09:18 +00:00
|
|
|
Done: design load finished with (0) errors, and (2) warnings
|
2024-06-09 05:17:38 +00:00
|
|
|
|
|
|
|
|
</PRE></BODY></HTML>
|
