2023-09-21 09:45:21 +00:00
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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</HEAD>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
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Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1_map.ncd.
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Design name: RAM2E
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-1200HC
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Package: TQFP100
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Performance: 4
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Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.44.
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Performance Hardware Data Status: Final Version 34.4.
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Setup and Hold Report
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<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
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2023-12-29 04:12:12 +00:00
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Thu Dec 28 23:09:59 2023
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2023-09-21 09:45:21 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf
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Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd
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Preference file: ram2e_lcmxo2_1200hc_impl1.prf
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Device,speed: LCMXO2-1200HC,4
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Report level: verbose report, limited to 1 item per preference
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<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
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2023-12-29 04:12:12 +00:00
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<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1611 items scored, 0 timing errors detected.
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Report: 90.967MHz is the maximum frequency for this preference.
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2023-09-21 09:45:21 +00:00
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
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2023-12-29 04:12:12 +00:00
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1611 items scored, 0 timing errors detected.
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2023-09-21 09:45:21 +00:00
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--------------------------------------------------------------------------------
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2023-12-29 04:12:12 +00:00
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Passed: The following path meets requirements by 58.937ns
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2023-09-21 09:45:21 +00:00
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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2023-12-29 04:12:12 +00:00
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Source: FF Q S[2] (from C14M_c +)
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Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
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2023-09-21 09:45:21 +00:00
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2023-12-29 04:12:12 +00:00
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Delay: 10.827ns (31.6% logic, 68.4% route), 7 logic levels.
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2023-09-21 09:45:21 +00:00
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Constraint Details:
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2023-12-29 04:12:12 +00:00
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10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
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2023-09-21 09:45:21 +00:00
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69.930ns delay constraint less
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2023-12-29 04:12:12 +00:00
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0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
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2023-09-21 09:45:21 +00:00
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Physical Path Details:
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2023-12-29 04:12:12 +00:00
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Data path SLICE_34 to ram2e_ufm/SLICE_47:
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2023-09-21 09:45:21 +00:00
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Name Fanout Delay (ns) Site Resource
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2023-12-29 04:12:12 +00:00
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REG_DEL --- 0.452 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from C14M_c)
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ROUTE 50 e 1.234 SLICE_34.Q0 to SLICE_35.A0 S[2]
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CTOF_DEL --- 0.495 SLICE_35.A0 to SLICE_35.F0 SLICE_35
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ROUTE 7 e 1.234 SLICE_35.F0 to *m/SLICE_80.D1 N_551
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CTOF_DEL --- 0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
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ROUTE 8 e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
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CTOF_DEL --- 0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
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ROUTE 5 e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
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CTOF_DEL --- 0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
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ROUTE 1 e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
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CTOF_DEL --- 0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
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ROUTE 1 e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
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CTOF_DEL --- 0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
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ROUTE 1 e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
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2023-09-21 09:45:21 +00:00
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--------
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2023-12-29 04:12:12 +00:00
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10.827 (31.6% logic, 68.4% route), 7 logic levels.
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2023-09-21 09:45:21 +00:00
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2023-12-29 04:12:12 +00:00
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Report: 90.967MHz is the maximum frequency for this preference.
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2023-09-21 09:45:21 +00:00
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<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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2023-12-29 04:12:12 +00:00
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FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 90.967 MHz| 7
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2023-09-21 09:45:21 +00:00
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 1 clocks:
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2023-12-29 04:12:12 +00:00
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Clock Domain: C14M_c Source: C14M.PAD Loads: 89
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2023-09-21 09:45:21 +00:00
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Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
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<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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2023-12-29 04:12:12 +00:00
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Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
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2023-09-21 09:45:21 +00:00
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--------------------------------------------------------------------------------
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<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
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2023-12-29 04:12:12 +00:00
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Thu Dec 28 23:09:59 2023
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2023-09-21 09:45:21 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf
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Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd
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Preference file: ram2e_lcmxo2_1200hc_impl1.prf
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Device,speed: LCMXO2-1200HC,M
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
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2023-12-29 04:12:12 +00:00
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<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1611 items scored, 0 timing errors detected.
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2023-09-21 09:45:21 +00:00
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
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2023-12-29 04:12:12 +00:00
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1611 items scored, 0 timing errors detected.
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2023-09-21 09:45:21 +00:00
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.447ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q FS[0] (from C14M_c +)
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Destination: FF Data in FS[0] (to C14M_c +)
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Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
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Constraint Details:
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0.434ns physical path delay SLICE_0 to SLICE_0 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
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Physical Path Details:
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Data path SLICE_0 to SLICE_0:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
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2023-12-29 04:12:12 +00:00
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ROUTE 6 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
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2023-09-21 09:45:21 +00:00
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CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
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ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
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--------
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0.434 (53.9% logic, 46.1% route), 2 logic levels.
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<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 1 clocks:
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2023-12-29 04:12:12 +00:00
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Clock Domain: C14M_c Source: C14M.PAD Loads: 89
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2023-09-21 09:45:21 +00:00
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Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
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<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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2023-12-29 04:12:12 +00:00
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Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
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2023-09-21 09:45:21 +00:00
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<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
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---------------
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Timing errors: 0 (setup), 0 (hold)
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Score: 0 (setup), 0 (hold)
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Cumulative negative slack: 0 (0+0)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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