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RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo

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MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
RC
2023-09-21 09:45:45 +00:00
// ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
// Netlist created on Sat Jan 06 06:24:57 2024
// Netlist written on Sat Jan 06 06:25:00 2024
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
// Design is for device LCMXO256C
// Design is for package TQFP100
// Design is for performance grade 3
`timescale 1 ns / 1 ps
module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS,
UFMCLK, UFMSDI, UFMSDO );
input PHI2;
input [9:0] MAin;
input [1:0] CROW;
input [7:0] Din;
input nCCAS, nCRAS, nFWE, RCLK, UFMSDO;
output [7:0] Dout;
output LED;
output [1:0] RBA;
output [11:0] RA;
output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI;
inout [7:0] RD;
wire \FS[1] , \FS[0] , RCLK_c, \FS_cry[1] , \FS[17] , \FS[16] ,
\FS_cry[15] , \FS[15] , \FS[14] , \FS_cry[13] , \FS[13] , \FS[12] ,
\FS_cry[11] , \FS[11] , \FS[10] , \FS_cry[9] , \FS[9] , \FS[8] ,
\FS_cry[7] , \FS[7] , \FS[6] , \FS_cry[5] , \FS[5] , \FS[4] ,
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
\FS_cry[3] , \FS[3] , \FS[2] , C1WR, ADWR, CmdEnable16, CmdEnable17,
N_183_i, ADSubmitted, ADSubmitted_r, PHI2_c, un1_CmdEnable20_0_a3_0_2,
N_121, C1Submitted, C1Submitted_RNO, un1_CmdEnable20_i,
CmdEnable16_0_a3_4, CmdEnable16_0_a3_5, CmdEnable_0_sqmuxa, CmdEnable,
CmdEnable_s, N_45, \Din_c[1] , CmdLEDEN_4_u_i_a2_0_0, CmdLEDEN, N_95,
LEDEN, CmdLEDEN_4_u_i_0, N_14_i, XOR8MEG18, PHI2r3, PHI2r2, InitReady,
CmdSubmitted, CmdSubmitted_1_sqmuxa, N_428_0, N_134, \Din_c[0] ,
Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0, N_12_i, \IS[2] , \IS[1] ,
\IS[0] , Ready, N_148, N_77_i_i, CASr2, N_160, CASr3, N_74_i_i,
N_69_i, N_153_i, \IS[3] , N_75_i_i, RA10s_i, UFMSDI_ens2_i_a2_4_2,
N_128, N_34, InitReady3, N_429_0, UFMSDI_ens2_i_a0, nCRAS_c, CBR,
UFMSDO_c, N_49, N_26, LED_c, N_151, \RA_c[10] , g3, \Din_c[7] ,
\Din_c[6] , \Din_c[4] , XOR8MEG, RA11_2, Ready_fast, \RA_c[11] , N_36,
RCKEEN_8_u_0_a3_0_0, FWEr_fast, \S[1] , CO0, RCKEEN_8_u_0_1_1,
RCKEEN_8_u_0_0, RCKEEN_8, PHI2r, RCKEEN, RCKE_c, RASr2, RASr3, RASr,
RCKE_2, g0_i_a5_1, \S_0_i_o2[1] , Ready_0_sqmuxa_0_a3_2, N_430_0,
Ready_0_sqmuxa, N_431_0, nRRAS_0_sqmuxa, N_129, UFMCLK_r_i_a2_2_2,
CmdUFMCLK, UFMCLK_r_i_m4_xx_mm_1, UFMCLK_c, nUFMCS15, N_137_i,
UFMCLK_RNO, UFMSDI_r_xx_mm_1, UFMSDI_c, UFMSDI_RNO, N_94, CmdUFMSDI,
\Din_c[5] , nCCAS_c, \WRD[4] , \WRD[5] , FWEr, N_125, \WRD[6] , N_43,
\WRD[7] , N_163, XOR8MEG_3_u_0_a3_0_1, N_166, XOR8MEG_3, N_48, N_24,
un1_nRCAS_6_sqmuxa_i_0, nRCAS_0_sqmuxa_1, G_1_1, G_1_0, N_46_i,
nRCAS_c, CBR_fast, g0_i_a5_1_2, g0_i_0, N_184, N_143_i, nRCS_c,
nRRAS_5_u_i_0, N_154, N_142_i, nRRAS_c, m18_0_a2_1, G_17_1, N_144_i,
nRWE_c, N_112, nRowColSel_0_0, nRowColSel, nUFMCS_s_0_N_5_i_N_2L1,
nUFMCS_c, nUFMCS_s_0_N_5_i, m18_0_a3_3, CmdUFMCS, N_133_5, N_133_3,
\MAin_c[3] , \MAin_c[2] , \RowA[2] , \RowA[3] , g0_i_a5_2_1, N_9,
RCKEEN_8_u_0_1_a1_0, UFMSDI_ens2_i_o2_0_3, \MAin_c[1] , \MAin_c[0] ,
\RowA[0] , \RowA[1] , nFWE_c, CMDWR_2, C1WR_7, CMDWR,
un1_FS_13_i_a2_9_5, un1_FS_13_i_a2_9_4, un1_FS_14_i_a2_0_1,
un1_FS_13_i_a2_1, \Din_c[3] , \MAin_c[7] , \MAin_c[6] , \RowA[6] ,
\RowA[7] , N_180, N_156, N_122_5, CASr, \Din_c[2] , \Bank[6] ,
\Bank[7] , \MAin_c[4] , C1WR_2_0, \Bank[0] , \Bank[1] , \Bank[5] ,
\Bank[2] , un1_Bank_1_5, un1_Bank_1_4, ADWR_8, \MAin_c[5] , ADWR_8_2,
\Bank[3] , ADWR_8_4, m6_0_a2_2, \WRD[2] , \WRD[3] , \MAin_c[9] ,
\MAin_c[8] , \RowA[8] , \RowA[9] , \WRD[0] , \WRD[1] ,
CmdUFMCLK_1_sqmuxa, \RowA[4] , \RowA[5] , \CROW_c[1] , \CROW_c[0] ,
\RBA_c[0] , \RBA_c[1] , \RA_c[9] , RDQMH_c, \Bank[4] , \RA_c[1] ,
\RA_c[8] , RDQML_c, \RA_c[3] , \RA_c[0] , \RA_c[4] , \RA_c[2] ,
\RA_c[5] , \RA_c[7] , RD_1_i, \RA_c[6] , \RD_in[0] , \RD_in[7] ,
\RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , \RD_in[2] ,
\RD_in[1] , VCCI, GNDI_TSALL;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SLICE_0 SLICE_0( .A1(\FS[1] ), .A0(\FS[0] ), .CLK(RCLK_c), .Q0(\FS[0] ),
.Q1(\FS[1] ), .FCO(\FS_cry[1] ));
SLICE_1 SLICE_1( .A1(\FS[17] ), .A0(\FS[16] ), .CLK(RCLK_c),
.FCI(\FS_cry[15] ), .Q0(\FS[16] ), .Q1(\FS[17] ));
SLICE_2 SLICE_2( .A1(\FS[15] ), .A0(\FS[14] ), .CLK(RCLK_c),
.FCI(\FS_cry[13] ), .Q0(\FS[14] ), .Q1(\FS[15] ), .FCO(\FS_cry[15] ));
SLICE_3 SLICE_3( .A1(\FS[13] ), .A0(\FS[12] ), .CLK(RCLK_c),
.FCI(\FS_cry[11] ), .Q0(\FS[12] ), .Q1(\FS[13] ), .FCO(\FS_cry[13] ));
SLICE_4 SLICE_4( .A1(\FS[11] ), .A0(\FS[10] ), .CLK(RCLK_c),
.FCI(\FS_cry[9] ), .Q0(\FS[10] ), .Q1(\FS[11] ), .FCO(\FS_cry[11] ));
SLICE_5 SLICE_5( .A1(\FS[9] ), .A0(\FS[8] ), .CLK(RCLK_c), .FCI(\FS_cry[7] ),
.Q0(\FS[8] ), .Q1(\FS[9] ), .FCO(\FS_cry[9] ));
SLICE_6 SLICE_6( .A1(\FS[7] ), .A0(\FS[6] ), .CLK(RCLK_c), .FCI(\FS_cry[5] ),
.Q0(\FS[6] ), .Q1(\FS[7] ), .FCO(\FS_cry[7] ));
SLICE_7 SLICE_7( .A1(\FS[5] ), .A0(\FS[4] ), .CLK(RCLK_c), .FCI(\FS_cry[3] ),
.Q0(\FS[4] ), .Q1(\FS[5] ), .FCO(\FS_cry[5] ));
SLICE_8 SLICE_8( .A1(\FS[3] ), .A0(\FS[2] ), .CLK(RCLK_c), .FCI(\FS_cry[1] ),
.Q0(\FS[2] ), .Q1(\FS[3] ), .FCO(\FS_cry[3] ));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
SLICE_9 SLICE_9( .B1(C1WR), .A1(ADWR), .D0(CmdEnable16), .C0(CmdEnable17),
.B0(N_183_i), .A0(ADSubmitted), .DI0(ADSubmitted_r), .CLK(PHI2_c),
.F0(ADSubmitted_r), .Q0(ADSubmitted), .F1(N_183_i));
SLICE_14 SLICE_14( .D1(un1_CmdEnable20_0_a3_0_2), .C1(N_121),
.B1(CmdEnable16), .A1(C1Submitted), .D0(ADWR), .C0(C1WR), .B0(C1Submitted),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.A0(CmdEnable16), .DI0(C1Submitted_RNO), .CLK(PHI2_c),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(un1_CmdEnable20_i));
SLICE_20 SLICE_20( .D1(C1WR), .C1(CmdEnable16_0_a3_4),
.B1(CmdEnable16_0_a3_5), .A1(ADSubmitted), .D0(CmdEnable_0_sqmuxa),
.C0(un1_CmdEnable20_i), .B0(CmdEnable17), .A0(CmdEnable),
.DI0(CmdEnable_s), .CLK(PHI2_c), .F0(CmdEnable_s), .Q0(CmdEnable),
.F1(CmdEnable_0_sqmuxa));
SLICE_21 SLICE_21( .D1(N_45), .C1(\Din_c[1] ), .B1(CmdLEDEN_4_u_i_a2_0_0),
.A1(CmdLEDEN), .C0(N_95), .B0(LEDEN), .A0(CmdLEDEN_4_u_i_0), .DI0(N_14_i),
.CE(XOR8MEG18), .CLK(PHI2_c), .F0(N_14_i), .Q0(CmdLEDEN),
.F1(CmdLEDEN_4_u_i_0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SLICE_22 SLICE_22( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady),
.A1(CmdSubmitted), .B0(CmdSubmitted), .A0(CmdSubmitted_1_sqmuxa),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.DI0(N_428_0), .CLK(PHI2_c), .F0(N_428_0), .Q0(CmdSubmitted), .F1(N_134));
SLICE_26 SLICE_26( .D1(N_45), .C1(\Din_c[0] ), .B1(Cmdn8MEGEN),
.A1(CmdLEDEN_4_u_i_a2_0_0), .C0(n8MEGEN), .B0(N_95),
.A0(Cmdn8MEGEN_4_u_i_0), .DI0(N_12_i), .CE(XOR8MEG18), .CLK(PHI2_c),
.F0(N_12_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0));
SLICE_29 SLICE_29( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .C0(Ready),
.B0(N_148), .A0(\IS[0] ), .DI0(N_77_i_i), .M1(CASr2), .CLK(RCLK_c),
.F0(N_77_i_i), .Q0(\IS[0] ), .F1(N_160), .Q1(CASr3));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SLICE_30 SLICE_30( .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ), .B0(\IS[1] ),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.A0(\IS[0] ), .DI1(N_74_i_i), .DI0(N_69_i), .CE(N_153_i), .CLK(RCLK_c),
.F0(N_69_i), .Q0(\IS[1] ), .F1(N_74_i_i), .Q1(\IS[2] ));
SLICE_31 SLICE_31( .D1(Ready), .C1(N_148), .B1(\IS[3] ), .A1(\IS[0] ),
.D0(\IS[0] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(\IS[3] ), .DI0(N_75_i_i),
.CE(N_153_i), .CLK(RCLK_c), .F0(N_75_i_i), .Q0(\IS[3] ), .F1(RA10s_i));
SLICE_32 SLICE_32( .D1(UFMSDI_ens2_i_a2_4_2), .C1(N_128), .B1(N_34),
.A1(InitReady), .B0(InitReady), .A0(InitReady3), .DI0(N_429_0),
.CLK(RCLK_c), .F0(N_429_0), .Q0(InitReady), .F1(UFMSDI_ens2_i_a0));
SLICE_33 SLICE_33( .D1(nCRAS_c), .C1(Ready), .B1(LEDEN), .A1(CBR),
.C0(UFMSDO_c), .B0(InitReady), .A0(CmdLEDEN), .DI0(N_49), .CE(N_26),
.CLK(RCLK_c), .F0(N_49), .Q0(LEDEN), .F1(LED_c));
SLICE_38 SLICE_38( .D1(\IS[3] ), .C1(\IS[2] ), .B1(\IS[1] ), .A1(\IS[0] ),
.B0(\IS[2] ), .A0(\IS[1] ), .DI0(N_151), .LSR(RA10s_i), .CLK(RCLK_c),
.F0(N_151), .Q0(\RA_c[10] ), .F1(g3));
SLICE_39 SLICE_39( .C1(\Din_c[7] ), .B1(\Din_c[6] ), .A1(\Din_c[4] ),
.C0(n8MEGEN), .B0(XOR8MEG), .A0(\Din_c[6] ), .DI0(RA11_2),
.LSR(Ready_fast), .CLK(PHI2_c), .F0(RA11_2), .Q0(\RA_c[11] ), .F1(N_36));
SLICE_41 SLICE_41( .D1(RCKEEN_8_u_0_a3_0_0), .C1(FWEr_fast), .B1(\S[1] ),
.A1(CO0), .D0(Ready), .C0(RCKEEN_8_u_0_1_1), .B0(RCKEEN_8_u_0_0), .A0(CBR),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.DI0(RCKEEN_8), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.F1(RCKEEN_8_u_0_1_1), .Q1(PHI2r2));
SLICE_42 SLICE_42( .C1(Ready), .B1(RCKE_c), .A1(RASr2), .D0(RCKEEN),
.C0(RASr3), .B0(RASr2), .A0(RASr), .DI0(RCKE_2), .M1(PHI2_c), .CLK(RCLK_c),
.F0(RCKE_2), .Q0(RCKE_c), .F1(g0_i_a5_1), .Q1(PHI2r));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SLICE_43 SLICE_43( .D1(\S_0_i_o2[1] ), .C1(InitReady), .B1(RASr2),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.A1(Ready), .D0(InitReady), .C0(N_160), .B0(Ready_0_sqmuxa_0_a3_2),
.A0(Ready), .DI0(N_430_0), .M1(PHI2r2), .CLK(RCLK_c), .F0(N_430_0),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Q0(Ready), .F1(RCKEEN_8_u_0_0), .Q1(PHI2r3));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
SLICE_44 SLICE_44( .D1(Ready_0_sqmuxa_0_a3_2), .C1(Ready), .B1(N_160),
.A1(InitReady), .B0(Ready_fast), .A0(Ready_0_sqmuxa), .DI0(N_431_0),
.M1(RASr2), .CLK(RCLK_c), .F0(N_431_0), .Q0(Ready_fast),
.F1(Ready_0_sqmuxa), .Q1(RASr3));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SLICE_50 SLICE_50( .C1(CO0), .B1(\S[1] ), .A1(Ready), .B0(\S[1] ), .A0(CO0),
.DI0(\S_0_i_o2[1] ), .LSR(RASr2), .CLK(RCLK_c), .F0(\S_0_i_o2[1] ),
.Q0(\S[1] ), .F1(nRRAS_0_sqmuxa));
SLICE_51 SLICE_51( .D1(N_129), .C1(UFMCLK_r_i_a2_2_2), .B1(CmdUFMCLK),
.A1(InitReady), .D0(UFMCLK_r_i_m4_xx_mm_1), .C0(UFMCLK_c), .B0(nUFMCS15),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.A0(N_137_i), .DI0(UFMCLK_RNO), .CLK(RCLK_c), .F0(UFMCLK_RNO),
.Q0(UFMCLK_c), .F1(UFMCLK_r_i_m4_xx_mm_1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SLICE_52 SLICE_52( .D1(PHI2r3), .C1(PHI2r2), .B1(InitReady),
.A1(CmdSubmitted), .D0(UFMSDI_r_xx_mm_1), .C0(UFMSDI_c), .B0(nUFMCS15),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.A0(N_137_i), .DI0(UFMSDI_RNO), .CLK(RCLK_c), .F0(UFMSDI_RNO),
.Q0(UFMSDI_c), .F1(N_137_i));
SLICE_55 SLICE_55( .C0(N_94), .B0(UFMSDI_ens2_i_a0), .A0(CmdUFMSDI),
.M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(nCCAS_c), .F0(UFMSDI_r_xx_mm_1),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Q0(\WRD[4] ), .Q1(\WRD[5] ));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
SLICE_56 SLICE_56( .B1(\FS[11] ), .A1(\FS[4] ), .B0(FWEr), .A0(CO0),
.M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(nCCAS_c), .F0(N_125), .Q0(\WRD[6] ),
.F1(N_43), .Q1(\WRD[7] ));
SLICE_57 SLICE_57( .B1(XOR8MEG), .A1(N_163), .D0(XOR8MEG_3_u_0_a3_0_1),
.C0(N_166), .B0(LEDEN), .A0(\Din_c[1] ), .DI0(XOR8MEG_3), .CE(XOR8MEG18),
.CLK(PHI2_c), .F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_166));
SLICE_58 SLICE_58( .C1(N_128), .B1(InitReady), .A1(\FS[8] ), .C0(UFMSDO_c),
.B0(InitReady), .A0(Cmdn8MEGEN), .DI0(N_48), .CE(N_24), .CLK(RCLK_c),
.F0(N_48), .Q0(n8MEGEN), .F1(N_94));
SLICE_59 SLICE_59( .C1(\S[1] ), .B1(un1_nRCAS_6_sqmuxa_i_0), .A1(CBR),
.D0(\S[1] ), .C0(nRCAS_0_sqmuxa_1), .B0(G_1_1), .A0(G_1_0), .DI0(N_46_i),
.CLK(RCLK_c), .F0(N_46_i), .Q0(nRCAS_c), .F1(G_1_1));
SLICE_60 SLICE_60( .C1(\S[1] ), .B1(Ready), .A1(CBR_fast), .D0(g0_i_a5_1_2),
.C0(g0_i_0), .B0(N_184), .A0(N_125), .DI0(N_143_i), .CLK(RCLK_c),
.F0(N_143_i), .Q0(nRCS_c), .F1(N_184));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SLICE_61 SLICE_61( .D1(Ready), .C1(RCKE_c), .B1(RASr2), .A1(\S_0_i_o2[1] ),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.D0(nRRAS_5_u_i_0), .C0(N_154), .B0(N_148), .A0(\IS[0] ), .DI0(N_142_i),
.CLK(RCLK_c), .F0(N_142_i), .Q0(nRRAS_c), .F1(nRRAS_5_u_i_0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SLICE_62 SLICE_62( .D1(Ready), .C1(RASr2), .B1(\S_0_i_o2[1] ), .A1(CBR_fast),
.D0(m18_0_a2_1), .C0(nRCAS_0_sqmuxa_1), .B0(G_17_1), .A0(FWEr),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.DI0(N_144_i), .CLK(RCLK_c), .F0(N_144_i), .Q0(nRWE_c),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.F1(nRCAS_0_sqmuxa_1));
SLICE_63 SLICE_63( .D1(Ready), .C1(FWEr), .B1(CBR), .A1(CASr3), .D0(\S[1] ),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.C0(Ready), .B0(N_112), .A0(CO0), .DI0(nRowColSel_0_0),
MAX, MachXO, MachXO2 working
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.LSR(nRRAS_0_sqmuxa), .CLK(RCLK_c), .F0(nRowColSel_0_0), .Q0(nRowColSel),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.F1(N_112));
SLICE_64 SLICE_64( .D1(N_128), .C1(InitReady), .B1(\FS[11] ), .A1(\FS[10] ),
.D0(nUFMCS_s_0_N_5_i_N_2L1), .C0(nUFMCS_c), .B0(nUFMCS15), .A0(N_137_i),
MAX, MachXO, MachXO2 working
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.DI0(nUFMCS_s_0_N_5_i), .CLK(RCLK_c), .F0(nUFMCS_s_0_N_5_i), .Q0(nUFMCS_c),
.F1(nUFMCS15));
nRWE_RNO_1_SLICE_65 \nRWE_RNO_1/SLICE_65 ( .D1(RASr2), .C1(RCKE_c), .B1(CO0),
.A1(\S[1] ), .D0(InitReady), .C0(m18_0_a3_3), .B0(CO0), .A0(\S[1] ),
.M0(Ready), .OFX0(m18_0_a2_1));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
SLICE_66 SLICE_66( .D1(CO0), .C1(\S[1] ), .B1(InitReady), .A1(RASr2),
.D0(\S[1] ), .C0(Ready), .B0(N_154), .A0(N_148),
.F0(un1_nRCAS_6_sqmuxa_i_0), .F1(N_148));
SLICE_67 SLICE_67( .C1(UFMCLK_r_i_a2_2_2), .B1(InitReady), .A1(CmdUFMCS),
.D0(N_133_5), .C0(N_133_3), .B0(InitReady), .A0(\FS[13] ),
.M1(\MAin_c[3] ), .M0(\MAin_c[2] ), .LSR(Ready_fast), .CLK(nCRAS_c),
.F0(UFMCLK_r_i_a2_2_2), .Q0(\RowA[2] ), .F1(nUFMCS_s_0_N_5_i_N_2L1),
.Q1(\RowA[3] ));
SLICE_68 SLICE_68( .D1(g3), .C1(g0_i_a5_2_1), .B1(RASr2), .A1(CO0),
.D0(g0_i_a5_1), .C0(\S[1] ), .B0(N_9), .A0(CO0), .M0(RASr2),
.LSR(RCKEEN_8_u_0_1_a1_0), .CLK(RCLK_c), .F0(g0_i_0), .Q0(CO0), .F1(N_9));
SLICE_69 SLICE_69( .C1(UFMSDI_ens2_i_o2_0_3), .B1(\FS[16] ), .A1(\FS[13] ),
.D0(\FS[4] ), .C0(\FS[11] ), .B0(\FS[1] ), .A0(N_128), .M1(\MAin_c[1] ),
.M0(\MAin_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_129),
.Q0(\RowA[0] ), .F1(N_128), .Q1(\RowA[1] ));
SLICE_70 SLICE_70( .D1(nFWE_c), .C1(\MAin_c[0] ), .B1(CMDWR_2), .A1(C1WR_7),
.C0(CMDWR), .B0(C1WR), .A0(ADWR), .F0(N_121), .F1(CMDWR));
SLICE_71 SLICE_71( .D1(un1_FS_13_i_a2_9_5), .C1(un1_FS_13_i_a2_9_4),
.B1(N_43), .A1(\FS[5] ), .C0(un1_FS_14_i_a2_0_1), .B0(N_134), .A0(N_94),
.F0(N_24), .F1(un1_FS_14_i_a2_0_1));
SLICE_72 SLICE_72( .D1(un1_FS_13_i_a2_9_5), .C1(un1_FS_13_i_a2_9_4),
.B1(N_43), .A1(\FS[5] ), .C0(un1_FS_13_i_a2_1), .B0(N_134), .A0(N_94),
.F0(N_26), .F1(un1_FS_13_i_a2_1));
SLICE_73 SLICE_73( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36),
.A1(XOR8MEG18), .B0(CmdEnable), .A0(CMDWR), .M1(\MAin_c[7] ),
.M0(\MAin_c[6] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(XOR8MEG18),
.Q0(\RowA[6] ), .F1(CmdSubmitted_1_sqmuxa), .Q1(\RowA[7] ));
SLICE_74 SLICE_74( .B1(\Din_c[6] ), .A1(\Din_c[4] ), .D0(N_180), .C0(N_156),
.B0(N_122_5), .A0(ADWR), .M1(CASr), .M0(nCCAS_c), .CLK(RCLK_c),
.F0(CmdEnable17), .Q0(CASr), .F1(N_156), .Q1(CASr2));
SLICE_75 SLICE_75( .D1(\Din_c[4] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ),
.A1(\Din_c[1] ), .C0(CmdEnable16_0_a3_5), .B0(CmdEnable16_0_a3_4),
.A0(C1WR), .M1(\Din_c[7] ), .M0(\Din_c[6] ), .CLK(PHI2_c),
.F0(CmdEnable16), .Q0(\Bank[6] ), .F1(CmdEnable16_0_a3_5), .Q1(\Bank[7] ));
SLICE_76 SLICE_76( .D1(\MAin_c[4] ), .C1(\MAin_c[3] ), .B1(\MAin_c[1] ),
.A1(\MAin_c[0] ), .D0(nFWE_c), .C0(\MAin_c[2] ), .B0(C1WR_7),
.A0(C1WR_2_0), .M1(\Din_c[1] ), .M0(\Din_c[0] ), .CLK(PHI2_c), .F0(C1WR),
.Q0(\Bank[0] ), .F1(C1WR_2_0), .Q1(\Bank[1] ));
SLICE_77 SLICE_77( .D1(\Bank[7] ), .C1(\Bank[6] ), .B1(\Bank[5] ),
.A1(\Bank[2] ), .D0(un1_Bank_1_5), .C0(un1_Bank_1_4), .B0(nFWE_c),
.A0(ADWR_8), .F0(ADWR), .F1(un1_Bank_1_5));
SLICE_78 SLICE_78( .B1(\Din_c[2] ), .A1(\Din_c[0] ), .D0(N_180), .C0(N_156),
.B0(N_122_5), .A0(ADWR_8), .F0(un1_CmdEnable20_0_a3_0_2), .F1(N_180));
SLICE_79 SLICE_79( .B1(\MAin_c[7] ), .A1(\MAin_c[6] ), .D0(un1_Bank_1_5),
.C0(un1_Bank_1_4), .B0(\MAin_c[5] ), .A0(ADWR_8_2), .M1(\Din_c[3] ),
.M0(\Din_c[2] ), .CLK(PHI2_c), .F0(C1WR_7), .Q0(\Bank[2] ), .F1(ADWR_8_2),
.Q1(\Bank[3] ));
SLICE_80 SLICE_80( .B1(\FS[17] ), .A1(\FS[11] ), .D0(N_133_5), .C0(N_133_3),
.B0(\FS[13] ), .A0(\FS[10] ), .F0(InitReady3), .F1(N_133_3));
SLICE_81 SLICE_81( .D1(\MAin_c[5] ), .C1(\MAin_c[4] ), .B1(\MAin_c[1] ),
.A1(\MAin_c[0] ), .D0(\MAin_c[3] ), .C0(\MAin_c[2] ), .B0(ADWR_8_4),
.A0(ADWR_8_2), .F0(ADWR_8), .F1(ADWR_8_4));
SLICE_82 SLICE_82( .C1(Ready), .B1(CASr3), .A1(CASr2), .D0(m6_0_a2_2),
.C0(\S[1] ), .B0(CO0), .A0(CBR_fast), .M1(\Din_c[3] ), .M0(\Din_c[2] ),
.CLK(nCCAS_c), .F0(G_17_1), .Q0(\WRD[2] ), .F1(m6_0_a2_2), .Q1(\WRD[3] ));
SLICE_83 SLICE_83( .D1(\Din_c[4] ), .C1(\Din_c[6] ), .B1(\Din_c[5] ),
.A1(\Din_c[7] ), .D0(\Din_c[0] ), .C0(\Din_c[2] ), .B0(\Din_c[3] ),
.A0(N_163), .M1(\MAin_c[9] ), .M0(\MAin_c[8] ), .LSR(Ready_fast),
.CLK(nCRAS_c), .F0(XOR8MEG_3_u_0_a3_0_1), .Q0(\RowA[8] ), .F1(N_163),
MAX, MachXO, MachXO2 working
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.Q1(\RowA[9] ));
SPI/LCMXO RC
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SLICE_84 SLICE_84( .D1(FWEr_fast), .C1(CO0), .B1(CASr3), .A1(CASr2),
.D0(FWEr_fast), .C0(CO0), .B0(CASr3), .A0(CASr2), .M1(\Din_c[1] ),
.M0(\Din_c[0] ), .CLK(nCCAS_c), .F0(g0_i_a5_1_2), .Q0(\WRD[0] ),
.F1(G_1_0), .Q1(\WRD[1] ));
SLICE_85 SLICE_85( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .B1(N_36),
.A1(XOR8MEG18), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ),
.M1(\Din_c[2] ), .M0(\Din_c[1] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c),
.F0(N_95), .Q0(CmdUFMCLK), .F1(CmdUFMCLK_1_sqmuxa), .Q1(CmdUFMCS));
SLICE_86 SLICE_86( .D1(\FS[17] ), .C1(\FS[15] ), .B1(\FS[14] ),
.A1(\FS[12] ), .D0(\FS[16] ), .C0(\FS[15] ), .B0(\FS[14] ), .A0(\FS[12] ),
.F0(N_133_5), .F1(UFMSDI_ens2_i_o2_0_3));
SLICE_87 SLICE_87( .D1(\Din_c[4] ), .C1(\Din_c[6] ), .B1(\Din_c[7] ),
.A1(\Din_c[5] ), .D0(\Din_c[7] ), .C0(\Din_c[6] ), .B0(\Din_c[5] ),
.A0(\Din_c[0] ), .M1(nCCAS_c), .M0(nCCAS_c), .CLK(nCRAS_c),
.F0(CmdEnable16_0_a3_4), .Q0(CBR), .F1(CmdLEDEN_4_u_i_a2_0_0),
.Q1(CBR_fast));
SLICE_88 SLICE_88( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ),
.A1(\Din_c[1] ), .C0(N_36), .B0(\Din_c[5] ), .A0(\Din_c[3] ),
.M0(\Din_c[0] ), .CE(CmdUFMCLK_1_sqmuxa), .CLK(PHI2_c), .F0(N_45),
.Q0(CmdUFMSDI), .F1(N_122_5));
SLICE_89 SLICE_89( .D1(\FS[10] ), .C1(\FS[9] ), .B1(\FS[7] ), .A1(\FS[1] ),
.C0(\FS[9] ), .B0(\FS[7] ), .A0(\FS[5] ), .M1(\MAin_c[5] ),
.M0(\MAin_c[4] ), .LSR(Ready_fast), .CLK(nCRAS_c), .F0(N_34),
.Q0(\RowA[4] ), .F1(un1_FS_13_i_a2_9_5), .Q1(\RowA[5] ));
SLICE_90 SLICE_90( .B1(\S[1] ), .A1(CO0), .C0(\S[1] ), .B0(CO0), .A0(CASr2),
.M1(\CROW_c[1] ), .M0(\CROW_c[0] ), .LSR(Ready_fast), .CLK(nCRAS_c),
.F0(RCKEEN_8_u_0_a3_0_0), .Q0(\RBA_c[0] ), .F1(RCKEEN_8_u_0_1_a1_0),
MAX, MachXO, MachXO2 working
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.Q1(\RBA_c[1] ));
SPI/LCMXO RC
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SLICE_91 SLICE_91( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel),
.B0(\RowA[9] ), .A0(\MAin_c[9] ), .F0(\RA_c[9] ), .F1(RDQMH_c));
SLICE_92 SLICE_92( .C1(\IS[1] ), .B1(\IS[2] ), .A1(\IS[3] ), .D0(RASr2),
.C0(\IS[2] ), .B0(\IS[1] ), .A0(\IS[0] ), .F0(m18_0_a3_3), .F1(N_154));
SLICE_93 SLICE_93( .C1(nRowColSel), .B1(\RowA[1] ), .A1(\MAin_c[1] ),
.D0(\MAin_c[4] ), .C0(\MAin_c[3] ), .B0(\MAin_c[2] ), .A0(\MAin_c[1] ),
.M1(\Din_c[5] ), .M0(\Din_c[4] ), .CLK(PHI2_c), .F0(CMDWR_2),
.Q0(\Bank[4] ), .F1(\RA_c[1] ), .Q1(\Bank[5] ));
SLICE_94 SLICE_94( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[8] ), .A1(\FS[6] ),
.D0(\FS[6] ), .C0(\FS[3] ), .B0(\FS[2] ), .A0(\FS[0] ),
.F0(un1_FS_13_i_a2_9_4), .F1(UFMSDI_ens2_i_a2_4_2));
SLICE_95 SLICE_95( .B1(\S[1] ), .A1(InitReady), .D0(\S[1] ), .C0(RASr2),
.B0(\IS[3] ), .A0(CO0), .M1(RASr), .M0(nCRAS_c), .CLK(RCLK_c),
.F0(Ready_0_sqmuxa_0_a3_2), .Q0(RASr), .F1(g0_i_a5_2_1), .Q1(RASr2));
SLICE_96 SLICE_96( .B1(nRowColSel), .A1(\MAin_c[9] ), .C0(nRowColSel),
.B0(\RowA[8] ), .A0(\MAin_c[8] ), .F0(\RA_c[8] ), .F1(RDQML_c));
SLICE_97 SLICE_97( .C1(nRowColSel), .B1(\RowA[0] ), .A1(\MAin_c[0] ),
MAX, MachXO, MachXO2 working
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.C0(nRowColSel), .B0(\RowA[3] ), .A0(\MAin_c[3] ), .F0(\RA_c[3] ),
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
.F1(\RA_c[0] ));
SLICE_98 SLICE_98( .C1(nRowColSel), .B1(\RowA[2] ), .A1(\MAin_c[2] ),
.C0(nRowColSel), .B0(\RowA[4] ), .A0(\MAin_c[4] ), .F0(\RA_c[4] ),
.F1(\RA_c[2] ));
SLICE_99 SLICE_99( .C1(nRowColSel), .B1(\RowA[7] ), .A1(\MAin_c[7] ),
.C0(nRowColSel), .B0(\RowA[5] ), .A0(\MAin_c[5] ), .F0(\RA_c[5] ),
.F1(\RA_c[7] ));
SLICE_100 SLICE_100( .B1(nFWE_c), .A1(nCCAS_c), .D0(\Bank[4] ),
.C0(\Bank[3] ), .B0(\Bank[1] ), .A0(\Bank[0] ), .F0(un1_Bank_1_4),
.F1(RD_1_i));
SLICE_101 SLICE_101( .C1(nRowColSel), .B1(\RowA[6] ), .A1(\MAin_c[6] ),
.B0(Ready), .A0(N_148), .M1(nFWE_c), .M0(nFWE_c), .CLK(nCRAS_c),
.F0(N_153_i), .Q0(FWEr), .F1(\RA_c[6] ), .Q1(FWEr_fast));
MAX, MachXO, MachXO2 working
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RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RD_1_i), .PADDO(\WRD[0] ),
.RD0(RD[0]));
Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO));
UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI));
UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK));
nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS));
RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS));
nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS));
nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE));
RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS));
RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RD_1_i), .PADDO(\WRD[7] ),
.RD7(RD[7]));
RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RD_1_i), .PADDO(\WRD[6] ),
.RD6(RD[6]));
RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RD_1_i), .PADDO(\WRD[5] ),
.RD5(RD[5]));
RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RD_1_i), .PADDO(\WRD[4] ),
.RD4(RD[4]));
RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RD_1_i), .PADDO(\WRD[3] ),
.RD3(RD[3]));
RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RD_1_i), .PADDO(\WRD[2] ),
.RD2(RD[2]));
RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RD_1_i), .PADDO(\WRD[1] ),
.RD1(RD[1]));
RA_11_ \RA[11]_I ( .PADDO(\RA_c[11] ), .RA11(RA[11]));
RA_10_ \RA[10]_I ( .PADDO(\RA_c[10] ), .RA10(RA[10]));
RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
RBA_1_ \RBA[1]_I ( .PADDO(\RBA_c[1] ), .RBA1(RBA[1]));
RBA_0_ \RBA[0]_I ( .PADDO(\RBA_c[0] ), .RBA0(RBA[0]));
LED LED_I( .PADDO(LED_c), .LED(LED));
nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
VHI VHI_INST( .Z(VCCI));
PUR PUR_INST( .PUR(VCCI));
GSR GSR_INST( .GSR(VCCI));
VLO VLO_INST( .Z(GNDI_TSALL));
TSALL TSALL_INST( .TSALL(GNDI_TSALL));
endmodule
module SLICE_0 ( input A1, A0, CLK, output Q0, Q1, FCO );
wire VCCI, \SLICE_0/FS_cry_0[0]_S1 , GNDI, \SLICE_0/FS_cry_0[0]_S0 ,
A1_dly, CLK_dly, A0_dly;
vmuxregsre \FS[1] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[0] ( .D0(VCCI), .D1(\SLICE_0/FS_cry_0[0]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 \FS_cry_0[0] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(VCCI),
.S0(\SLICE_0/FS_cry_0[0]_S0 ), .S1(\SLICE_0/FS_cry_0[0]_S1 ), .CO0(),
.CO1(FCO));
specify
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
endspecify
endmodule
module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module vcc ( output PWR1 );
VHI INST1( .Z(PWR1));
endmodule
module gnd ( output PWR0 );
VLO INST1( .Z(PWR0));
endmodule
module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0,
CO1 );
CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
defparam inst1.INIT0 = 16'h300a;
defparam inst1.INIT1 = 16'h300a;
defparam inst1.INJECT1_0 = "NO";
defparam inst1.INJECT1_1 = "NO";
endmodule
module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1 );
wire VCCI, \SLICE_1/FS_cry_0[16]_S1 , GNDI, \SLICE_1/FS_cry_0[16]_S0 ,
A1_dly, CLK_dly, A0_dly, FCI_dly;
vmuxregsre \FS[17] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[16] ( .D0(VCCI), .D1(\SLICE_1/FS_cry_0[16]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20001 \FS_cry_0[16] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly),
.S0(\SLICE_1/FS_cry_0[16]_S0 ), .S1(\SLICE_1/FS_cry_0[16]_S1 ), .CO0(),
.CO1());
specify
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
$setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
endspecify
endmodule
module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0,
CO1 );
CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1));
defparam inst1.INIT0 = 16'h300a;
defparam inst1.INIT1 = 16'h5002;
defparam inst1.INJECT1_0 = "NO";
defparam inst1.INJECT1_1 = "NO";
endmodule
module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
wire VCCI, \SLICE_2/FS_cry_0[14]_S1 , GNDI, \SLICE_2/FS_cry_0[14]_S0 ,
A1_dly, CLK_dly, A0_dly, FCI_dly;
vmuxregsre \FS[15] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[14] ( .D0(VCCI), .D1(\SLICE_2/FS_cry_0[14]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 \FS_cry_0[14] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly),
.S0(\SLICE_2/FS_cry_0[14]_S0 ), .S1(\SLICE_2/FS_cry_0[14]_S1 ), .CO0(),
.CO1(FCO));
specify
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
$setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
endspecify
endmodule
module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
wire VCCI, \SLICE_3/FS_cry_0[12]_S1 , GNDI, \SLICE_3/FS_cry_0[12]_S0 ,
A1_dly, CLK_dly, A0_dly, FCI_dly;
vmuxregsre \FS[13] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[12] ( .D0(VCCI), .D1(\SLICE_3/FS_cry_0[12]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 \FS_cry_0[12] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly),
.S0(\SLICE_3/FS_cry_0[12]_S0 ), .S1(\SLICE_3/FS_cry_0[12]_S1 ), .CO0(),
.CO1(FCO));
specify
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
$setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
endspecify
endmodule
module SLICE_4 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
wire VCCI, \SLICE_4/FS_cry_0[10]_S1 , GNDI, \SLICE_4/FS_cry_0[10]_S0 ,
A1_dly, CLK_dly, A0_dly, FCI_dly;
vmuxregsre \FS[11] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[10] ( .D0(VCCI), .D1(\SLICE_4/FS_cry_0[10]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 \FS_cry_0[10] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly),
.S0(\SLICE_4/FS_cry_0[10]_S0 ), .S1(\SLICE_4/FS_cry_0[10]_S1 ), .CO0(),
.CO1(FCO));
specify
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
$setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
endspecify
endmodule
module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
wire VCCI, \SLICE_5/FS_cry_0[8]_S1 , GNDI, \SLICE_5/FS_cry_0[8]_S0 ,
A1_dly, CLK_dly, A0_dly, FCI_dly;
vmuxregsre \FS[9] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[8] ( .D0(VCCI), .D1(\SLICE_5/FS_cry_0[8]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 \FS_cry_0[8] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly),
.S0(\SLICE_5/FS_cry_0[8]_S0 ), .S1(\SLICE_5/FS_cry_0[8]_S1 ), .CO0(),
.CO1(FCO));
specify
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
$setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
endspecify
endmodule
module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
wire VCCI, \SLICE_6/FS_cry_0[6]_S1 , GNDI, \SLICE_6/FS_cry_0[6]_S0 ,
A1_dly, CLK_dly, A0_dly, FCI_dly;
vmuxregsre \FS[7] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[6] ( .D0(VCCI), .D1(\SLICE_6/FS_cry_0[6]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 \FS_cry_0[6] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly),
.S0(\SLICE_6/FS_cry_0[6]_S0 ), .S1(\SLICE_6/FS_cry_0[6]_S1 ), .CO0(),
.CO1(FCO));
specify
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
$setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
endspecify
endmodule
module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
wire VCCI, \SLICE_7/FS_cry_0[4]_S1 , GNDI, \SLICE_7/FS_cry_0[4]_S0 ,
A1_dly, CLK_dly, A0_dly, FCI_dly;
vmuxregsre \FS[5] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[4] ( .D0(VCCI), .D1(\SLICE_7/FS_cry_0[4]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 \FS_cry_0[4] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly),
.S0(\SLICE_7/FS_cry_0[4]_S0 ), .S1(\SLICE_7/FS_cry_0[4]_S1 ), .CO0(),
.CO1(FCO));
specify
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
$setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
endspecify
endmodule
module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO );
wire VCCI, \SLICE_8/FS_cry_0[2]_S1 , GNDI, \SLICE_8/FS_cry_0[2]_S0 ,
A1_dly, CLK_dly, A0_dly, FCI_dly;
vmuxregsre \FS[3] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S1 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[2] ( .D0(VCCI), .D1(\SLICE_8/FS_cry_0[2]_S0 ), .SD(VCCI),
.SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu2 \FS_cry_0[2] ( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI),
.A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly),
.S0(\SLICE_8/FS_cry_0[2]_S0 ), .S1(\SLICE_8/FS_cry_0[2]_S1 ), .CO0(),
.CO1(FCO));
specify
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly);
$setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly);
$setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly);
endspecify
endmodule
SPI/LCMXO RC
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module SLICE_9 ( input B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
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SPI/LCMXO RC
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lut4 ADSubmitted_r_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
lut40002 ADSubmitted_r( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
module lut4 ( input A, B, C, D, output Z );
SPI/LCMXO RC
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ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40002 ( input A, B, C, D, output Z );
ROM16X1 #(16'h00F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module inverter ( input I, output Z );
INV INST1( .A(I), .Z(Z));
endmodule
SPI/LCMXO RC
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module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
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SPI/LCMXO RC
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lut40003 CmdEnable_s_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
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lut40004 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
SPI/LCMXO RC
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gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
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specify
SPI/LCMXO RC
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(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
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(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
module lut40003 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40004 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40005 CmdEnable_0_sqmuxa( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40006 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
module lut40005 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40006 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hFFCA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_21 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40007 CmdLEDEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40008 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40007 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h5D0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40008 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h4545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module SLICE_22 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40009 un1_FS_14_i_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut4 CmdSubmitted_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40009 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module SLICE_26 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40010 Cmdn8MEGEN_4_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40011 Cmdn8MEGEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40010 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40011 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI0, M1, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40012 Ready_0_sqmuxa_0_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40013 \IS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre CASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(CLK => Q1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40012 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40013 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_30 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40014 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40015 IS_n1_0_x2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40014 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40015 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40016 RA10_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40017 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40016 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40017 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40018 UFMSDI_ens2_i_a0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut4 InitReady_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40018 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h5155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_33 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40019 LED_pad_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40020 LEDEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40019 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hFFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40020 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_38 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
lut40021 nRCS_RNO_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut4 RA10_2_sqmuxa_0_o2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0022 RA10( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40021 ( input A, B, C, D, output Z );
ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module vmuxregsre0022 ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module SLICE_39 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40023 Cmdn8MEGEN_4_u_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40024 RA11_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre0025 RA11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40023 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40024 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module vmuxregsre0025 ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
module SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output
F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40026 RCKEEN_8_u_0_1_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40027 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre PHI2r2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40026 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0CDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40027 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_42 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0,
Q0, F1, Q1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40028 nRCS_RNO_3( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
lut40029 RCKE_2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre PHI2r( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40028 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40029 ( input A, B, C, D, output Z );
ROM16X1 #(16'hFE30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_43 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output
F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40030 RCKEEN_8_u_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
lut40031 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40030 ( input A, B, C, D, output Z );
ROM16X1 #(16'h5072) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40031 ( input A, B, C, D, output Z );
ROM16X1 #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_44 ( input D1, C1, B1, A1, B0, A0, DI0, M1, CLK, output F0, Q0,
F1, Q1 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40032 Ready_0_sqmuxa_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut4 Ready_fast_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre RASr3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40032 ( input A, B, C, D, output Z );
ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
module SLICE_50 ( input C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40033 nRowColSel_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut4 \S_0_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
vmuxregsre0025 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40033 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
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lut40034 UFMCLK_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40035 UFMCLK_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre UFMCLK( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
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module lut40034 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'hF2F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
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module lut40035 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h1032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
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module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
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lut40036 PHI2r3_RNITCN41( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40037 UFMSDI_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre UFMSDI( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
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module lut40036 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
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module lut40037 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_55 ( input C0, B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
SPI/LCMXO RC
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lut40038 UFMSDI_RNO_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \WRD[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre \WRD[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
endspecify
endmodule
SPI/LCMXO RC
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module lut40038 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
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SPI/LCMXO RC
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ROM16X1 #(16'h3232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
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module SLICE_56 ( input B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
SPI/LCMXO RC
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lut40039 un1_FS_14_i_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40040 nRCS_9_u_i_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \WRD[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre \WRD[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
endspecify
endmodule
SPI/LCMXO RC
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module lut40039 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
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SPI/LCMXO RC
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ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
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module lut40040 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
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ROM16X1 #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
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module SLICE_57 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40041 XOR8MEG_3_u_0_a3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40042 XOR8MEG_3_u_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
SPI/LCMXO RC
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module lut40041 ( input A, B, C, D, output Z );
ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40042 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'hF7F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_58 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40043 UFMSDI_en_ss0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40020 n8MEGEN_5_i_m2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40043 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
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module SLICE_59 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40044 nRCAS_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40045 nRCAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0046 nRCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
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module lut40044 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40045 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0703) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module vmuxregsre0046 ( input D0, D1, SD, SP, CK, LSR, output Q );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_60 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40047 RCKEEN_8_u_0_a2_0_m1_0_a2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40048 nRCS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0046 nRCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40047 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40048 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0307) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40049 nRRAS_5_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40050 nRRAS_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0046 nRRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40049 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40050 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h00CD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40051 nRCAS_0_sqmuxa_1_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40052 nRWE_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0046 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40051 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40052 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'hF4F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output
F0, Q0, F1 );
wire VCCI, DI0_dly, CLK_dly, LSR_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40053 nRowColSel_0_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40054 nRowColSel_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0025 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40053 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40054 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'hDCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40055 nUFMCS15_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40056 nUFMCS_s_0_N_5_i( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0046 nUFMCS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40055 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40056 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'hDCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module nRWE_RNO_1_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output
OFX0 );
wire \nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ,
\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40057 \nRWE_RNO_1/SLICE_65_K1 ( .A(A1), .B(B1), .C(C1), .D(D1),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40058 \nRWE_RNO_1/GATE ( .A(A0), .B(B0), .C(C0), .D(D0),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Z(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ));
selmux2 \nRWE_RNO_1/SLICE_65_K0K1MUX (
.D0(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/GATE_H0 ),
.D1(\nRWE_RNO_1/SLICE_65/nRWE_RNO_1/SLICE_65_K1_H1 ), .SD(M0), .Z(OFX0));
specify
(D1 => OFX0) = (0:0:0,0:0:0);
(C1 => OFX0) = (0:0:0,0:0:0);
(B1 => OFX0) = (0:0:0,0:0:0);
(A1 => OFX0) = (0:0:0,0:0:0);
(D0 => OFX0) = (0:0:0,0:0:0);
(C0 => OFX0) = (0:0:0,0:0:0);
(B0 => OFX0) = (0:0:0,0:0:0);
(A0 => OFX0) = (0:0:0,0:0:0);
(M0 => OFX0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40057 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40058 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module selmux2 ( input D0, D1, SD, output Z );
MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
endmodule
module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40016 IS_0_sqmuxa_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40059 un1_nRCAS_6_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40059 ( input A, B, C, D, output Z );
ROM16X1 #(16'h0BFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40060 nUFMCS_s_0_N_5_i_N_2L1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40051 UFMCLK_r_i_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0025 \RowA[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre0025 \RowA[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40060 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1 #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output
F0, Q0, F1 );
wire VCCI, GNDI, M0_dly, CLK_dly, LSR_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40061 nRCS_RNO_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40027 nRCS_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0025 \S[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40061 ( input A, B, C, D, output Z );
ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_69 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output
F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
lut40062 UFMSDI_ens2_i_o2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40063 UFMCLK_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0025 \RowA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre0025 \RowA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40062 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40063 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hD888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_70 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40064 CMDWR( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40043 un1_CmdEnable20_0_a3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40064 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_71 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40053 un1_FS_14_i_a2_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40065 un1_FS_14_i_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40065 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40051 un1_FS_13_i_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40065 un1_FS_13_i_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module SLICE_73 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0,
Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
lut40066 CmdSubmitted_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40041 XOR8MEG18( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0025 \RowA[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0025 \RowA[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40066 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_74 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1,
Q1 );
wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut4 CmdEnable17_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40009 CmdEnable17_0_a3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre CASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40055 CmdEnable16_0_a3_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40067 CmdEnable16_0_a3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre \Bank[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre \Bank[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40067 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0,
Q0, F1, Q1 );
wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40061 C1WR_2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40064 C1WR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \Bank[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \Bank[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40061 un1_Bank_1_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40051 ADWR( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40041 CmdEnable17_0_a2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40009 un1_CmdEnable20_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_79 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
Q1 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40041 ADWR_8_2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40005 C1WR_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \Bank[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre \Bank[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40041 InitReady3_0_a2_3( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40005 InitReady3_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40005 ADWR_8_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40005 ADWR_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module SLICE_82 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
lut40068 nRWE_RNO_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40061 nRWE_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \WRD[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre \WRD[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40068 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40021 XOR8MEG_3_u_0_o2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40053 XOR8MEG_3_u_0_a3_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre0022 \RowA[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
gnd DRIVEGND( .PWR0(GNDI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0025 \RowA[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0,
Q0, F1, Q1 );
wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40069 nRCAS_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40051 nRCS_RNO_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \WRD[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre \WRD[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
endspecify
endmodule
module lut40069 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h200F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_85 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0,
Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40070 CmdUFMCLK_1_sqmuxa_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40071 Cmdn8MEGEN_4_u_i_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre CmdUFMCS( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre CmdUFMCLK( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
module lut40070 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40071 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40021 UFMSDI_ens2_i_o2_0_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40005 InitReady3_0_a2_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_87 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
Q0, F1, Q1 );
wire M1_NOTIN, VCCI, GNDI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40072 CmdLEDEN_4_u_i_a2_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40051 CmdEnable16_0_a3_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CBR_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre CBR( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
endspecify
endmodule
module lut40072 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_88 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
F1 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40061 CmdEnable17_0_a3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40073 Cmdn8MEGEN_4_u_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre CmdUFMSDI( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
module lut40073 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_89 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output
F0, Q0, F1, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40072 un1_FS_13_i_a2_9_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40074 UFMSDI_ens2_i_o2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre0022 \RowA[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre0025 \RowA[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40074 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h2C2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_90 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40075 RCKEEN_8_u_0_1_a1_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40076 RCKEEN_8_u_0_a3_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
vmuxregsre0025 \RBA[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
vmuxregsre0025 \RBA[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40075 ( input A, B, C, D, output Z );
ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
module lut40076 ( input A, B, C, D, output Z );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
ROM16X1 #(16'h7070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_91 ( input B1, A1, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40077 RDQMH( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module lut40077 ( input A, B, C, D, output Z );
ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40078 ( input A, B, C, D, output Z );
ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_92 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40062 un1_nRCAS_6_sqmuxa_i_o2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40032 nRWE_RNO_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_93 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
F1, Q1 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40061 CMDWR_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre \Bank[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
vmuxregsre \Bank[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40032 UFMSDI_ens2_i_a2_4_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40055 un1_FS_13_i_a2_9_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_95 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1,
Q1 );
wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40075 nRCS_RNO_4( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40009 Ready_0_sqmuxa_0_a3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre RASr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_96 ( input B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40039 RDQML( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40078 \un9_RA[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_97 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_98 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_99 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_100 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut4 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40005 un1_Bank_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module SLICE_101 ( input C1, B1, A1, B0, A0, M1, M0, CLK, output F0, Q0, F1,
Q1 );
wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40078 \un9_RA[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
lut40040 IS_0_sqmuxa_0_o2_0_RNIS63D( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
.Z(F0));
vmuxregsre FWEr_fast( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre FWEr( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
(CLK => Q1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
mjiobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
specify
(PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD0) = (0:0:0,0:0:0);
(RD0 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD0, 0:0:0);
$width (negedge RD0, 0:0:0);
endspecify
endmodule
module mjiobuf ( input I, T, output Z, PAD, input PADI );
IB INST1( .I(PADI), .O(Z));
OBW INST2( .I(I), .T(T), .O(PAD));
endmodule
module Dout_0_ ( input PADDO, output Dout0 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0079 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout0) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module mjiobuf0079 ( input I, output PAD );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
OB INST5( .I(I), .O(PAD));
endmodule
module PHI2 ( output PADDI, input PHI2 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0080 PHI2_pad( .Z(PADDI), .PAD(PHI2));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PHI2 => PADDI) = (0:0:0,0:0:0);
$width (posedge PHI2, 0:0:0);
$width (negedge PHI2, 0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module mjiobuf0080 ( output Z, input PAD );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
IB INST1( .I(PAD), .O(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module UFMSDO ( output PADDI, input UFMSDO );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0080 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(UFMSDO => PADDI) = (0:0:0,0:0:0);
$width (posedge UFMSDO, 0:0:0);
$width (negedge UFMSDO, 0:0:0);
endspecify
endmodule
module UFMSDI ( input PADDO, output UFMSDI );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 UFMSDI_pad( .I(PADDO), .PAD(UFMSDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => UFMSDI) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module mjiobuf0081 ( input I, output PAD );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
OB INST5( .I(I), .O(PAD));
endmodule
module UFMCLK ( input PADDO, output UFMCLK );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 UFMCLK_pad( .I(PADDO), .PAD(UFMCLK));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => UFMCLK) = (0:0:0,0:0:0);
endspecify
endmodule
module nUFMCS ( input PADDO, output nUFMCS );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 nUFMCS_pad( .I(PADDO), .PAD(nUFMCS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => nUFMCS) = (0:0:0,0:0:0);
endspecify
endmodule
module RDQML ( input PADDO, output RDQML );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 RDQML_pad( .I(PADDO), .PAD(RDQML));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RDQML) = (0:0:0,0:0:0);
endspecify
endmodule
module RDQMH ( input PADDO, output RDQMH );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RDQMH) = (0:0:0,0:0:0);
endspecify
endmodule
module nRCAS ( input PADDO, output nRCAS );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 nRCAS_pad( .I(PADDO), .PAD(nRCAS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => nRCAS) = (0:0:0,0:0:0);
endspecify
endmodule
module nRRAS ( input PADDO, output nRRAS );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 nRRAS_pad( .I(PADDO), .PAD(nRRAS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => nRRAS) = (0:0:0,0:0:0);
endspecify
endmodule
module nRWE ( input PADDO, output nRWE );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 nRWE_pad( .I(PADDO), .PAD(nRWE));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => nRWE) = (0:0:0,0:0:0);
endspecify
endmodule
module RCKE ( input PADDO, output RCKE );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 RCKE_pad( .I(PADDO), .PAD(RCKE));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RCKE) = (0:0:0,0:0:0);
endspecify
endmodule
module RCLK ( output PADDI, input RCLK );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0080 RCLK_pad( .Z(PADDI), .PAD(RCLK));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(RCLK => PADDI) = (0:0:0,0:0:0);
$width (posedge RCLK, 0:0:0);
$width (negedge RCLK, 0:0:0);
endspecify
endmodule
module nRCS ( input PADDO, output nRCS );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 nRCS_pad( .I(PADDO), .PAD(nRCS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => nRCS) = (0:0:0,0:0:0);
endspecify
endmodule
module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
mjiobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
specify
(PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD7) = (0:0:0,0:0:0);
(RD7 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD7, 0:0:0);
$width (negedge RD7, 0:0:0);
endspecify
endmodule
module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
mjiobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
specify
(PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD6) = (0:0:0,0:0:0);
(RD6 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD6, 0:0:0);
$width (negedge RD6, 0:0:0);
endspecify
endmodule
module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
mjiobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
specify
(PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD5) = (0:0:0,0:0:0);
(RD5 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD5, 0:0:0);
$width (negedge RD5, 0:0:0);
endspecify
endmodule
module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
mjiobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
specify
(PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD4) = (0:0:0,0:0:0);
(RD4 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD4, 0:0:0);
$width (negedge RD4, 0:0:0);
endspecify
endmodule
module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
mjiobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
specify
(PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD3) = (0:0:0,0:0:0);
(RD3 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD3, 0:0:0);
$width (negedge RD3, 0:0:0);
endspecify
endmodule
module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
mjiobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
specify
(PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD2) = (0:0:0,0:0:0);
(RD2 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD2, 0:0:0);
$width (negedge RD2, 0:0:0);
endspecify
endmodule
module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
mjiobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
specify
(PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(PADDO => RD1) = (0:0:0,0:0:0);
(RD1 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD1, 0:0:0);
$width (negedge RD1, 0:0:0);
endspecify
endmodule
module RA_11_ ( input PADDO, output RA11 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[11] ( .I(PADDO), .PAD(RA11));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA11) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_10_ ( input PADDO, output RA10 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[10] ( .I(PADDO), .PAD(RA10));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA10) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_9_ ( input PADDO, output RA9 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA9) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_8_ ( input PADDO, output RA8 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA8) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_7_ ( input PADDO, output RA7 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA7) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_6_ ( input PADDO, output RA6 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA6) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_5_ ( input PADDO, output RA5 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA5) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_4_ ( input PADDO, output RA4 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA4) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_3_ ( input PADDO, output RA3 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA3) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_2_ ( input PADDO, output RA2 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA2) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_1_ ( input PADDO, output RA1 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA1) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_0_ ( input PADDO, output RA0 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA0) = (0:0:0,0:0:0);
endspecify
endmodule
module RBA_1_ ( input PADDO, output RBA1 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RBA_pad[1] ( .I(PADDO), .PAD(RBA1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RBA1) = (0:0:0,0:0:0);
endspecify
endmodule
module RBA_0_ ( input PADDO, output RBA0 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0081 \RBA_pad[0] ( .I(PADDO), .PAD(RBA0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RBA0) = (0:0:0,0:0:0);
endspecify
endmodule
module LED ( input PADDO, output LED );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0082 LED_pad( .I(PADDO), .PAD(LED));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => LED) = (0:0:0,0:0:0);
endspecify
endmodule
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
module mjiobuf0082 ( input I, output PAD );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
OB INST5( .I(I), .O(PAD));
endmodule
module nFWE ( output PADDI, input nFWE );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0080 nFWE_pad( .Z(PADDI), .PAD(nFWE));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(nFWE => PADDI) = (0:0:0,0:0:0);
$width (posedge nFWE, 0:0:0);
$width (negedge nFWE, 0:0:0);
endspecify
endmodule
module nCRAS ( output PADDI, input nCRAS );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0080 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(nCRAS => PADDI) = (0:0:0,0:0:0);
$width (posedge nCRAS, 0:0:0);
$width (negedge nCRAS, 0:0:0);
endspecify
endmodule
module nCCAS ( output PADDI, input nCCAS );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0080 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(nCCAS => PADDI) = (0:0:0,0:0:0);
$width (posedge nCCAS, 0:0:0);
$width (negedge nCCAS, 0:0:0);
endspecify
endmodule
module Dout_7_ ( input PADDO, output Dout7 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0079 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout7) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_6_ ( input PADDO, output Dout6 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0079 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout6) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_5_ ( input PADDO, output Dout5 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0079 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout5) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_4_ ( input PADDO, output Dout4 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0079 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout4) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_3_ ( input PADDO, output Dout3 );
SPI/LCMXO RC
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mjiobuf0079 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
MAX, MachXO, MachXO2 working
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specify
(PADDO => Dout3) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_2_ ( input PADDO, output Dout2 );
SPI/LCMXO RC
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mjiobuf0079 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
MAX, MachXO, MachXO2 working
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specify
(PADDO => Dout2) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_1_ ( input PADDO, output Dout1 );
SPI/LCMXO RC
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mjiobuf0079 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
MAX, MachXO, MachXO2 working
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specify
(PADDO => Dout1) = (0:0:0,0:0:0);
endspecify
endmodule
module Din_7_ ( output PADDI, input Din7 );
SPI/LCMXO RC
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mjiobuf0080 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
MAX, MachXO, MachXO2 working
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specify
(Din7 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din7, 0:0:0);
$width (negedge Din7, 0:0:0);
endspecify
endmodule
module Din_6_ ( output PADDI, input Din6 );
SPI/LCMXO RC
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mjiobuf0080 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
MAX, MachXO, MachXO2 working
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specify
(Din6 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din6, 0:0:0);
$width (negedge Din6, 0:0:0);
endspecify
endmodule
module Din_5_ ( output PADDI, input Din5 );
SPI/LCMXO RC
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mjiobuf0080 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
MAX, MachXO, MachXO2 working
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specify
(Din5 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din5, 0:0:0);
$width (negedge Din5, 0:0:0);
endspecify
endmodule
module Din_4_ ( output PADDI, input Din4 );
SPI/LCMXO RC
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mjiobuf0080 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
MAX, MachXO, MachXO2 working
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specify
(Din4 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din4, 0:0:0);
$width (negedge Din4, 0:0:0);
endspecify
endmodule
module Din_3_ ( output PADDI, input Din3 );
SPI/LCMXO RC
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mjiobuf0080 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
MAX, MachXO, MachXO2 working
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specify
(Din3 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din3, 0:0:0);
$width (negedge Din3, 0:0:0);
endspecify
endmodule
module Din_2_ ( output PADDI, input Din2 );
SPI/LCMXO RC
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mjiobuf0080 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
MAX, MachXO, MachXO2 working
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specify
(Din2 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din2, 0:0:0);
$width (negedge Din2, 0:0:0);
endspecify
endmodule
module Din_1_ ( output PADDI, input Din1 );
SPI/LCMXO RC
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mjiobuf0080 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
MAX, MachXO, MachXO2 working
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specify
(Din1 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din1, 0:0:0);
$width (negedge Din1, 0:0:0);
endspecify
endmodule
module Din_0_ ( output PADDI, input Din0 );
SPI/LCMXO RC
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mjiobuf0080 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
MAX, MachXO, MachXO2 working
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specify
(Din0 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din0, 0:0:0);
$width (negedge Din0, 0:0:0);
endspecify
endmodule
module CROW_1_ ( output PADDI, input CROW1 );
SPI/LCMXO RC
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mjiobuf0080 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
MAX, MachXO, MachXO2 working
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specify
(CROW1 => PADDI) = (0:0:0,0:0:0);
$width (posedge CROW1, 0:0:0);
$width (negedge CROW1, 0:0:0);
endspecify
endmodule
module CROW_0_ ( output PADDI, input CROW0 );
SPI/LCMXO RC
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mjiobuf0080 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
MAX, MachXO, MachXO2 working
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specify
(CROW0 => PADDI) = (0:0:0,0:0:0);
$width (posedge CROW0, 0:0:0);
$width (negedge CROW0, 0:0:0);
endspecify
endmodule
module MAin_9_ ( output PADDI, input MAin9 );
SPI/LCMXO RC
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mjiobuf0080 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
MAX, MachXO, MachXO2 working
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specify
(MAin9 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin9, 0:0:0);
$width (negedge MAin9, 0:0:0);
endspecify
endmodule
module MAin_8_ ( output PADDI, input MAin8 );
SPI/LCMXO RC
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mjiobuf0080 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
MAX, MachXO, MachXO2 working
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specify
(MAin8 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin8, 0:0:0);
$width (negedge MAin8, 0:0:0);
endspecify
endmodule
module MAin_7_ ( output PADDI, input MAin7 );
SPI/LCMXO RC
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mjiobuf0080 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin7 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin7, 0:0:0);
$width (negedge MAin7, 0:0:0);
endspecify
endmodule
module MAin_6_ ( output PADDI, input MAin6 );
SPI/LCMXO RC
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mjiobuf0080 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin6 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin6, 0:0:0);
$width (negedge MAin6, 0:0:0);
endspecify
endmodule
module MAin_5_ ( output PADDI, input MAin5 );
SPI/LCMXO RC
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mjiobuf0080 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin5 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin5, 0:0:0);
$width (negedge MAin5, 0:0:0);
endspecify
endmodule
module MAin_4_ ( output PADDI, input MAin4 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0080 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin4 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin4, 0:0:0);
$width (negedge MAin4, 0:0:0);
endspecify
endmodule
module MAin_3_ ( output PADDI, input MAin3 );
SPI/LCMXO RC
2024-01-07 02:52:05 +00:00
mjiobuf0080 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin3 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin3, 0:0:0);
$width (negedge MAin3, 0:0:0);
endspecify
endmodule
module MAin_2_ ( output PADDI, input MAin2 );
SPI/LCMXO RC
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mjiobuf0080 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
MAX, MachXO, MachXO2 working
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specify
(MAin2 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin2, 0:0:0);
$width (negedge MAin2, 0:0:0);
endspecify
endmodule
module MAin_1_ ( output PADDI, input MAin1 );
SPI/LCMXO RC
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mjiobuf0080 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
MAX, MachXO, MachXO2 working
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specify
(MAin1 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin1, 0:0:0);
$width (negedge MAin1, 0:0:0);
endspecify
endmodule
module MAin_0_ ( output PADDI, input MAin0 );
SPI/LCMXO RC
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mjiobuf0080 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
MAX, MachXO, MachXO2 working
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specify
(MAin0 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin0, 0:0:0);
$width (negedge MAin0, 0:0:0);
endspecify
endmodule
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