mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-12-02 16:49:19 +00:00
88 lines
1.4 KiB
Plaintext
88 lines
1.4 KiB
Plaintext
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[Device]
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Family=machxo2
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PartType=LCMXO2-1200HC
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PartName=LCMXO2-1200HC-4TG100C
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SpeedGrade=4
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Package=TQFP100
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OperatingCondition=COM
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Status=S
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[IP]
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VendorName=Lattice Semiconductor Corporation
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CoreType=LPM
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CoreStatus=Demo
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CoreName=PLL
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CoreRevision=5.8
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ModuleName=RPLL
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SourceFormat=Verilog HDL
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ParameterFileVersion=1.0
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Date=07/14/2024
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Time=22:23:22
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[Parameters]
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Verilog=1
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VHDL=0
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EDIF=1
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Destination=Synplicity
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Expression=None
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Order=None
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IO=0
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mode=Frequency
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CLKI=133.0
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CLKI_DIV=13
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BW=0.955
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VCO=491.077
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fb_mode=CLKOP
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CLKFB_DIV=6
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FRACN_ENABLE=0
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FRACN_DIV=0
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DynamicPhase=STATIC
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ClkEnable=0
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Standby=0
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Enable_sel=0
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PLLRst=0
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PLLMRst=0
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ClkOS2Rst=0
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ClkOS3Rst=0
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LockSig=0
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LockStk=0
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WBProt=0
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OPBypass=0
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OPUseDiv=0
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CLKOP_DIV=8
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FREQ_PIN_CLKOP=61
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OP_Tol=1.0
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CLKOP_AFREQ=61.384615
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CLKOP_PHASEADJ=0
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CLKOP_TRIM_POL=Rising
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CLKOP_TRIM_DELAY=0
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EnCLKOS=0
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OSBypass=0
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OSUseDiv=0
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CLKOS_DIV=1
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FREQ_PIN_CLKOS=100
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OS_Tol=0.0
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CLKOS_AFREQ=
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CLKOS_PHASEADJ=0
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CLKOS_TRIM_POL=Rising
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CLKOS_TRIM_DELAY=0
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EnCLKOS2=0
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OS2Bypass=0
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OS2UseDiv=0
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CLKOS2_DIV=1
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FREQ_PIN_CLKOS2=100
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OS2_Tol=0.0
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CLKOS2_AFREQ=
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CLKOS2_PHASEADJ=0
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EnCLKOS3=0
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OS3Bypass=0
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OS3UseDiv=0
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CLKOS3_DIV=1
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FREQ_PIN_CLKOS3=100
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OS3_Tol=0.0
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CLKOS3_AFREQ=
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CLKOS3_PHASEADJ=0
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[Command]
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cmd_line= -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
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