Apple-2-HW/RAM2GS
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RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_vo.vo

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MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
RC
2023-09-21 09:45:45 +00:00
// ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd
// Netlist created on Thu Sep 21 05:39:43 2023
// Netlist written on Thu Sep 21 05:40:09 2023
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
// Design is for device LCMXO2-640HC
// Design is for package TQFP100
// Design is for performance grade 4
`timescale 1 ns / 1 ps
module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA,
RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML );
input PHI2;
input [9:0] MAin;
input [1:0] CROW;
input [7:0] Din;
input nCCAS, nCRAS, nFWE, RCLK;
output [7:0] Dout;
output LED;
output [1:0] RBA;
output [11:0] RA;
output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML;
inout [7:0] RD;
wire \FS[0] , \FS_s[0] , RCLK_c, \FS_cry[0] , \FS[17] , \FS_s[17] ,
\FS_cry[16] , \FS[16] , \FS[15] , \FS_s[16] , \FS_s[15] ,
\FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] ,
\FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] ,
\FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] ,
\FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] ,
\FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] ,
\FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] ,
RC
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\MAin_c[1] , un1_CmdEnable20_0_0_o3, ADSubmitted, CmdEnable17, N_524,
CmdEnable16, ADSubmitted_r_0_0, PHI2_c, N_518, N_594, C1Submitted,
C1Submitted_RNO, nCCAS_c, nCCAS_c_i, CASr, CASr2, CO0, \S[1] ,
N_123_i, RASr2, N_345_i, N_593, CmdEnable_0_sqmuxa, un1_CmdEnable20_i,
CmdEnable, CmdEnable_s, \Din_c[1] , CmdLEDEN_4_u_i_0_a3_0_0,
CmdValid_2_i_o2_1_o3, CmdLEDEN, LEDEN, CmdLEDEN_4_u_i_0_0, N_531,
N_40_i, XOR8MEG18, CmdUFMShift, CmdUFMShift_3, CmdUFMWrite,
\Din_c[0] , N_462, CmdUFMWrite_3, N_213, \Din_c[3] , \Din_c[4] ,
\Din_c[5] , CmdValid_r, CmdValid, \MAin_c[0] , N_36_fast,
CmdValid_fast, Cmdn8MEGEN, n8MEGEN, Cmdn8MEGEN_4_u_i_0_0, N_38_i,
nFWE_c, nFWE_c_i, nCRAS_c, FWEr, RD_1_i, nRCS_9_u_i_0_o2_1_RNIL2K71,
\IS[0] , N_351_i_i, N_267, \IS[1] , \IS[2] , N_348_i_i, N_344_i,
N_360_i, \IS[3] , N_350_i_i, \IS_i[0] , N_581, InitReady3_0_a3_1,
InitReady3, InitReady, N_757_0, \wb_dato[1] , LEDEN_6_i_m2_i_m2,
CmdValid_RNIOOBE2, LEDENe_0, Ready_fast, \CROW_c[0] , PHI2r2, PHI2r,
\RBAd_0[0] , PHI2r3, CBR, nCRAS_c_i_0, RASr, LED_c, nRowColSel,
\RowA[3] , \MAin_c[3] , RASr3, \RA_c[3] , N_216, Ready,
RCKEEN_8_u_0_1_0, RCKEEN_8_u_0_0_0, RCKEEN_8, RCKEEN, RCKE_2, RCKE_c,
m3_0_a2_0, Ready_0_sqmuxa_0_a2_4_a3_2, N_347, N_758_0, Ready_0_sqmuxa,
N_759_0, \RowAd_0[1] , \RowAd_0[0] , \RowA[0] , \RowA[1] ,
\MAin_c[2] , \RowAd_0[3] , \RowAd_0[2] , \RowA[2] , \MAin_c[5] ,
\MAin_c[4] , \RowAd_0[5] , \RowAd_0[4] , \RowA[4] , \RowA[5] ,
\MAin_c[7] , \MAin_c[6] , \RowAd_0[7] , \RowAd_0[6] , \RowA[6] ,
\RowA[7] , \MAin_c[9] , \MAin_c[8] , \RowAd_0[9] , \RowAd_0[8] ,
\RowA[8] , \RowA[9] , XOR8MEG, N_441, XOR8MEG_3_u_0_0_a3_0_2,
XOR8MEG_3, N_4, g1_0, n8MEGENe_1_0, n8MEGENe_0, CASr3, N_248_i_1_1,
nRowColSel_0_0_0, nRRAS_0_sqmuxa, N_417, \wb_adr_5_i_0_0[1] , N_382,
N_416, \wb_adr_5_i_0_0[0] , N_383, N_423, \wb_adr_5_i_0_3[0] ,
N_229_i, N_230_i, un1_wb_rst14_i_0, \wb_adr[0] , \wb_adr[1] ,
\wb_adr[2] , \wb_adr_5[3] , \wb_adr_5[2] , \wb_adr[3] , \wb_adr[4] ,
N_210, N_385, N_384, \wb_adr[5] , \wb_adr[6] , \wb_adr_5[7] , N_386,
\wb_adr[7] , N_214, N_471_3, wb_cyc_stb_4_iv_0_a3_0_0, N_471_2,
un1_PHI2r3, N_471, wb_cyc_stb_4, N_178, wb_rst10, wb_cyc_stb, N_207,
\wb_dati_5_1_iv_0_1[1] , N_578, \wb_dati_5_0_iv_0_a3_1[0] , wb_we,
N_576, \wb_dati_5[1] , \wb_dati_5[0] , \wb_dati[0] , \wb_dati[1] ,
\wb_dati_5_1_iv_i_i_0[3] , \wb_dati_5_1_iv_i_i_1[3] ,
\wb_dati_5_1_iv_i_i_a3_1[3] , N_579, N_361, \wb_dati_5_1_iv_i_i[3] ,
MAX, MachXO, MachXO2 working
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\wb_dati_5[2] , \wb_dati[2] , \wb_dati[3] , \wb_dati[4] ,
RC
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\wb_dati_5_1_iv_0_0[4] , \wb_dati_5_1_iv_0_1[4] , \wb_dati_5[5] ,
\wb_dati_5[4] , \wb_dati[5] , N_484, N_486, N_488,
\wb_dati_5_1_iv_0_0[7] , \wb_dati_5_1_iv_0_1[6] , \wb_dati_5[7] ,
\wb_dati_5[6] , \wb_dati[6] , \wb_dati[7] , N_92_i, N_31_i, wb_req,
wb_reqe_0, N_515, wb_rst, wb_rste_0, CmdUFMData, wb_we_0_i_0_1,
N_231_i, N_479, N_217, N_209, CBR_fast, N_408, nRCAS_0_sqmuxa_1,
N_248_i_sx, un1_nRCAS_6_sqmuxa_i_0_0, nRCAS_r_i_0_o2_0_0, N_599,
N_407, N_427, wb_we_0_i_0_a3_0_0, wb_we_0_i_0_0, \Din_c[6] , N_539,
un1_CmdEnable20_0_0_0, \wb_adr_5_i_0_a3_0_1[0] , N_424, N_542,
\wb_adr_5_i_0_1[0] , N_208, \wb_dati_5_1_iv_0_a3_0_1[7] ,
\ufmefb/g0_0_a3_2 , N_226, \wb_dati_5_1_iv_0_a3_0_1[1] , N_477, N_236,
N_596, N_412, N_536, N_502, N_522, nRCS_9_u_i_0_o3,
\wb_dati_5_1_iv_i_i_a3_3_0[3] , un1_nRCAS_6_sqmuxa_i_0_0_o2_0, N_221,
N_246_i, un1_CmdEnable20_0_0_a3_1_1, nRWE_s_i_0_tz_0, N_590, N_595,
N_49_i, CmdUFMData_1_sqmuxa, N_248_i_1_0, N_247_i, \Bank[1] ,
\Bank[3] , \Bank[4] , \Bank[5] , un1_CmdEnable20_0_0_o3_10,
un1_CmdEnable20_0_0_o3_11, \Bank[7] , \Bank[6] , N_537, N_514, N_473,
N_472, RA10s_i, nRWE_s_i_0_a3_1_0, wb_ack, wb_cyc_stb_2_sqmuxa_i_a3_0,
\Bank[0] , \Bank[2] , un1_CmdEnable20_0_0_o3_4,
un1_CmdEnable20_0_0_o3_3, N_248_i_1, N_248_i, N_511, N_404,
wb_cyc_stb_4_iv_0_a3_0_2_0, N_505, \Din_c[2] , \Din_c[7] ,
XOR8MEG_3_u_0_0_0_a2, G_4_0_a3_0, RDQMH_c, RDQML_c, \RA_c[6] ,
\RA_c[8] , \RA_c[9] , \RA_c[0] , \RA_c[7] , \RA_c[1] , \RA_c[5] ,
\RA_c[2] , \RA_c[4] , \CROW_c[1] , RA11d_0, \RBAd_0[1] , \wb_dato[0] ,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
\RD_in[0] , \WRD[0] , nRCAS_c, nRRAS_c, nRWE_c, nRCS_c, \RD_in[7] ,
\WRD[7] , \RD_in[6] , \WRD[6] , \RD_in[5] , \WRD[5] , \RD_in[4] ,
\WRD[4] , \RD_in[3] , \WRD[3] , \RD_in[2] , \WRD[2] , \RD_in[1] ,
\WRD[1] , \RA_c[11] , \RA_c[10] , \RBA_c[1] , \RBA_c[0] , VCCI;
SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(RCLK_c), .F1(\FS_s[0] ),
.Q1(\FS[0] ), .FCO(\FS_cry[0] ));
SLICE_1 SLICE_1( .A0(\FS[17] ), .DI0(\FS_s[17] ), .CLK(RCLK_c),
.FCI(\FS_cry[16] ), .F0(\FS_s[17] ), .Q0(\FS[17] ));
SLICE_2 SLICE_2( .A1(\FS[16] ), .A0(\FS[15] ), .DI1(\FS_s[16] ),
.DI0(\FS_s[15] ), .CLK(RCLK_c), .FCI(\FS_cry[14] ), .F0(\FS_s[15] ),
.Q0(\FS[15] ), .F1(\FS_s[16] ), .Q1(\FS[16] ), .FCO(\FS_cry[16] ));
SLICE_3 SLICE_3( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ),
.DI0(\FS_s[13] ), .CLK(RCLK_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ),
.Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] ));
SLICE_4 SLICE_4( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ),
.DI0(\FS_s[11] ), .CLK(RCLK_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ),
.Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] ));
SLICE_5 SLICE_5( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ),
.DI0(\FS_s[9] ), .CLK(RCLK_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ),
.Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] ));
SLICE_6 SLICE_6( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ),
.DI0(\FS_s[7] ), .CLK(RCLK_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ),
.Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] ));
SLICE_7 SLICE_7( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ),
.DI0(\FS_s[5] ), .CLK(RCLK_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ),
.Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] ));
SLICE_8 SLICE_8( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ),
.DI0(\FS_s[3] ), .CLK(RCLK_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ),
.Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] ));
SLICE_9 SLICE_9( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ),
.DI0(\FS_s[1] ), .CLK(RCLK_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ),
.Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
RC
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SLICE_10 SLICE_10( .D1(\MAin_c[1] ), .C1(un1_CmdEnable20_0_0_o3),
.D0(ADSubmitted), .C0(CmdEnable17), .B0(N_524), .A0(CmdEnable16),
.DI0(ADSubmitted_r_0_0), .CLK(PHI2_c), .F0(ADSubmitted_r_0_0),
.Q0(ADSubmitted), .F1(N_524));
SLICE_11 SLICE_11( .D1(un1_CmdEnable20_0_0_o3), .C1(N_518), .B1(\MAin_c[1] ),
.A1(N_594), .D0(un1_CmdEnable20_0_0_o3), .C0(CmdEnable16),
.B0(\MAin_c[1] ), .A0(C1Submitted), .DI0(C1Submitted_RNO), .CLK(PHI2_c),
.F0(C1Submitted_RNO), .Q0(C1Submitted), .F1(CmdEnable16));
SLICE_12 SLICE_12( .D0(nCCAS_c), .DI0(nCCAS_c_i), .M1(CASr), .CLK(RCLK_c),
MAX, MachXO, MachXO2 working
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.F0(nCCAS_c_i), .Q0(CASr), .Q1(CASr2));
RC
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SLICE_16 SLICE_16( .C1(CO0), .A1(\S[1] ), .C0(CO0), .A0(\S[1] ),
.DI0(N_123_i), .LSR(RASr2), .CLK(RCLK_c), .F0(N_123_i), .Q0(CO0),
.F1(N_345_i));
SLICE_17 SLICE_17( .D1(N_518), .C1(N_593), .B1(\MAin_c[1] ),
.A1(un1_CmdEnable20_0_0_o3), .D0(CmdEnable_0_sqmuxa), .C0(CmdEnable17),
.B0(un1_CmdEnable20_i), .A0(CmdEnable), .DI0(CmdEnable_s), .CLK(PHI2_c),
.F0(CmdEnable_s), .Q0(CmdEnable), .F1(CmdEnable17));
SLICE_18 SLICE_18( .D1(\Din_c[1] ), .C1(CmdLEDEN_4_u_i_0_a3_0_0),
.B1(CmdValid_2_i_o2_1_o3), .A1(CmdLEDEN), .C0(LEDEN),
.B0(CmdLEDEN_4_u_i_0_0), .A0(N_531), .DI0(N_40_i), .CE(XOR8MEG18),
.CLK(PHI2_c), .F0(N_40_i), .Q0(CmdLEDEN), .F1(CmdLEDEN_4_u_i_0_0));
SLICE_20 SLICE_20( .D0(\Din_c[1] ), .C0(N_531), .B0(CmdValid_2_i_o2_1_o3),
MAX, MachXO, MachXO2 working
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.A0(CmdUFMShift), .DI0(CmdUFMShift_3), .CE(XOR8MEG18), .CLK(PHI2_c),
.F0(CmdUFMShift_3), .Q0(CmdUFMShift));
RC
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SLICE_21 SLICE_21( .D1(CmdValid_2_i_o2_1_o3), .A1(CmdUFMWrite),
.D0(\Din_c[0] ), .C0(N_462), .B0(\Din_c[1] ), .A0(N_531),
.DI0(CmdUFMWrite_3), .CE(XOR8MEG18), .CLK(PHI2_c), .F0(CmdUFMWrite_3),
.Q0(CmdUFMWrite), .F1(N_462));
SLICE_22 SLICE_22( .D1(N_213), .C1(\Din_c[3] ), .B1(\Din_c[4] ),
.A1(\Din_c[5] ), .C0(CmdValid_2_i_o2_1_o3), .A0(XOR8MEG18),
MAX, MachXO, MachXO2 working
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.DI0(CmdValid_r), .CLK(PHI2_c), .F0(CmdValid_r), .Q0(CmdValid),
RC
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.F1(CmdValid_2_i_o2_1_o3));
SLICE_23 SLICE_23( .D1(CmdEnable), .C1(\MAin_c[1] ), .B1(\MAin_c[0] ),
.A1(un1_CmdEnable20_0_0_o3), .C0(XOR8MEG18), .B0(CmdValid_2_i_o2_1_o3),
.DI0(N_36_fast), .CLK(PHI2_c), .F0(N_36_fast), .Q0(CmdValid_fast),
.F1(XOR8MEG18));
SLICE_24 SLICE_24( .D1(CmdValid_2_i_o2_1_o3), .C1(\Din_c[0] ),
.B1(Cmdn8MEGEN), .A1(CmdLEDEN_4_u_i_0_a3_0_0), .D0(n8MEGEN),
.C0(Cmdn8MEGEN_4_u_i_0_0), .B0(N_531), .DI0(N_38_i), .CE(XOR8MEG18),
.CLK(PHI2_c), .F0(N_38_i), .Q0(Cmdn8MEGEN), .F1(Cmdn8MEGEN_4_u_i_0_0));
SLICE_25 SLICE_25( .B1(nFWE_c), .A1(nCCAS_c), .A0(nFWE_c), .DI0(nFWE_c_i),
MAX, MachXO, MachXO2 working
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.CLK(nCRAS_c), .F0(nFWE_c_i), .Q0(FWEr), .F1(RD_1_i));
RC
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SLICE_26 SLICE_26( .B1(CASr2), .A1(CO0), .B0(nRCS_9_u_i_0_o2_1_RNIL2K71),
.A0(\IS[0] ), .DI0(N_351_i_i), .CLK(RCLK_c), .F0(N_351_i_i), .Q0(\IS[0] ),
.F1(N_267));
SLICE_27 SLICE_27( .C1(\IS[0] ), .B1(\IS[1] ), .A1(\IS[2] ), .C0(\IS[0] ),
.A0(\IS[1] ), .DI1(N_348_i_i), .DI0(N_344_i), .CE(N_360_i), .CLK(RCLK_c),
.F0(N_344_i), .Q0(\IS[1] ), .F1(N_348_i_i), .Q1(\IS[2] ));
SLICE_28 SLICE_28( .B1(\IS[0] ), .D0(\IS[2] ), .C0(\IS[1] ), .B0(\IS[0] ),
.A0(\IS[3] ), .DI0(N_350_i_i), .CE(N_360_i), .CLK(RCLK_c), .F0(N_350_i_i),
.Q0(\IS[3] ), .F1(\IS_i[0] ));
SLICE_29 SLICE_29( .D1(\FS[10] ), .C1(N_581), .B1(InitReady3_0_a3_1),
.A1(\FS[11] ), .C0(InitReady3), .A0(InitReady), .DI0(N_757_0),
.CLK(RCLK_c), .F0(N_757_0), .Q0(InitReady), .F1(InitReady3));
SLICE_30 SLICE_30( .C1(\wb_dato[1] ), .B1(InitReady), .A1(CmdLEDEN),
.D0(LEDEN), .B0(LEDEN_6_i_m2_i_m2), .A0(CmdValid_RNIOOBE2), .DI0(LEDENe_0),
.CLK(RCLK_c), .F0(LEDENe_0), .Q0(LEDEN), .F1(LEDEN_6_i_m2_i_m2));
SLICE_31 SLICE_31( .B0(Ready_fast), .A0(\CROW_c[0] ), .M1(PHI2r2),
.M0(PHI2r), .CLK(RCLK_c), .F0(\RBAd_0[0] ), .Q0(PHI2r2), .Q1(PHI2r3));
SLICE_32 SLICE_32( .D1(CBR), .C1(nCRAS_c), .B1(LEDEN), .C0(nCRAS_c),
MAX, MachXO, MachXO2 working
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.DI0(nCRAS_c_i_0), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c_i_0), .Q0(RASr),
.F1(LED_c), .Q1(RASr2));
RC
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SLICE_33 SLICE_33( .D1(nRowColSel), .C1(\RowA[3] ), .B1(\MAin_c[3] ),
.C0(CmdEnable16), .A0(ADSubmitted), .M0(RASr2), .CLK(RCLK_c),
.F0(CmdEnable_0_sqmuxa), .Q0(RASr3), .F1(\RA_c[3] ));
SLICE_34 SLICE_34( .D1(N_216), .C1(RASr2), .B1(InitReady), .A1(Ready),
.D0(RCKEEN_8_u_0_1_0), .C0(RCKEEN_8_u_0_0_0), .B0(CBR), .A0(Ready),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.DI0(RCKEEN_8), .CLK(RCLK_c), .F0(RCKEEN_8), .Q0(RCKEEN),
RC
2023-09-21 09:45:45 +00:00
.F1(RCKEEN_8_u_0_0_0));
SLICE_35 SLICE_35( .C1(RASr2), .A1(\S[1] ), .D0(RASr2), .C0(RASr3),
.B0(RCKEEN), .A0(RASr), .DI0(RCKE_2), .CLK(RCLK_c), .F0(RCKE_2),
.Q0(RCKE_c), .F1(m3_0_a2_0));
SLICE_36 SLICE_36( .D1(\IS[1] ), .C1(\IS[0] ), .B1(\IS[2] ),
.D0(Ready_0_sqmuxa_0_a2_4_a3_2), .C0(N_347), .B0(InitReady), .A0(Ready),
.DI0(N_758_0), .CLK(RCLK_c), .F0(N_758_0), .Q0(Ready), .F1(N_347));
SLICE_37 SLICE_37( .D1(Ready_0_sqmuxa_0_a2_4_a3_2), .C1(N_347),
.B1(InitReady), .A1(Ready), .C0(Ready_0_sqmuxa), .A0(Ready_fast),
.DI0(N_759_0), .CLK(RCLK_c), .F0(N_759_0), .Q0(Ready_fast),
.F1(Ready_0_sqmuxa));
SLICE_38 SLICE_38( .B1(Ready_fast), .A1(\MAin_c[1] ), .B0(Ready_fast),
.A0(\MAin_c[0] ), .DI1(\RowAd_0[1] ), .DI0(\RowAd_0[0] ), .CLK(nCRAS_c),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.F0(\RowAd_0[0] ), .Q0(\RowA[0] ), .F1(\RowAd_0[1] ), .Q1(\RowA[1] ));
RC
2023-09-21 09:45:45 +00:00
SLICE_39 SLICE_39( .B1(Ready_fast), .A1(\MAin_c[3] ), .C0(\MAin_c[2] ),
.B0(Ready_fast), .DI1(\RowAd_0[3] ), .DI0(\RowAd_0[2] ), .CLK(nCRAS_c),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.F0(\RowAd_0[2] ), .Q0(\RowA[2] ), .F1(\RowAd_0[3] ), .Q1(\RowA[3] ));
RC
2023-09-21 09:45:45 +00:00
SLICE_40 SLICE_40( .C1(Ready_fast), .B1(\MAin_c[5] ), .C0(Ready_fast),
.B0(\MAin_c[4] ), .DI1(\RowAd_0[5] ), .DI0(\RowAd_0[4] ), .CLK(nCRAS_c),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.F0(\RowAd_0[4] ), .Q0(\RowA[4] ), .F1(\RowAd_0[5] ), .Q1(\RowA[5] ));
RC
2023-09-21 09:45:45 +00:00
SLICE_41 SLICE_41( .C1(Ready_fast), .B1(\MAin_c[7] ), .C0(Ready_fast),
.B0(\MAin_c[6] ), .DI1(\RowAd_0[7] ), .DI0(\RowAd_0[6] ), .CLK(nCRAS_c),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.F0(\RowAd_0[6] ), .Q0(\RowA[6] ), .F1(\RowAd_0[7] ), .Q1(\RowA[7] ));
RC
2023-09-21 09:45:45 +00:00
SLICE_42 SLICE_42( .D1(Ready_fast), .A1(\MAin_c[9] ), .D0(Ready_fast),
.C0(\MAin_c[8] ), .DI1(\RowAd_0[9] ), .DI0(\RowAd_0[8] ), .CLK(nCRAS_c),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.F0(\RowAd_0[8] ), .Q0(\RowA[8] ), .F1(\RowAd_0[9] ), .Q1(\RowA[9] ));
RC
2023-09-21 09:45:45 +00:00
SLICE_43 SLICE_43( .D1(RASr2), .C1(CO0), .B1(\IS[3] ), .A1(\S[1] ), .B0(CO0),
.A0(\S[1] ), .DI0(N_216), .LSR(RASr2), .CLK(RCLK_c), .F0(N_216),
.Q0(\S[1] ), .F1(Ready_0_sqmuxa_0_a2_4_a3_2));
SLICE_44 SLICE_44( .D1(\Din_c[5] ), .C1(\Din_c[4] ), .B1(N_213),
.A1(XOR8MEG), .D0(\Din_c[1] ), .C0(LEDEN), .B0(N_441),
.A0(XOR8MEG_3_u_0_0_a3_0_2), .DI0(XOR8MEG_3), .CE(XOR8MEG18), .CLK(PHI2_c),
.F0(XOR8MEG_3), .Q0(XOR8MEG), .F1(N_441));
SLICE_45 SLICE_45( .D1(CmdValid), .C1(N_4), .B1(InitReady), .A1(g1_0),
.D0(n8MEGENe_1_0), .C0(CmdValid_RNIOOBE2), .A0(n8MEGEN), .DI0(n8MEGENe_0),
.CLK(RCLK_c), .F0(n8MEGENe_0), .Q0(n8MEGEN), .F1(CmdValid_RNIOOBE2));
SLICE_46 SLICE_46( .C1(CASr3), .A1(FWEr), .D0(CBR), .C0(N_248_i_1_1),
.B0(N_345_i), .A0(Ready), .DI0(nRowColSel_0_0_0), .LSR(nRRAS_0_sqmuxa),
.CLK(RCLK_c), .F0(nRowColSel_0_0_0), .Q0(nRowColSel), .F1(N_248_i_1_1));
SLICE_47 SLICE_47( .D1(N_417), .C1(\wb_adr_5_i_0_0[1] ), .B1(N_382),
.A1(N_416), .D0(\wb_adr_5_i_0_0[0] ), .C0(N_383), .B0(N_423),
.A0(\wb_adr_5_i_0_3[0] ), .DI1(N_229_i), .DI0(N_230_i),
.CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_230_i), .Q0(\wb_adr[0] ),
.F1(N_229_i), .Q1(\wb_adr[1] ));
SLICE_48 SLICE_48( .D1(\wb_adr[2] ), .A1(InitReady), .C0(\wb_adr[1] ),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.A0(InitReady), .DI1(\wb_adr_5[3] ), .DI0(\wb_adr_5[2] ),
RC
2023-09-21 09:45:45 +00:00
.CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_adr_5[2] ), .Q0(\wb_adr[2] ),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.F1(\wb_adr_5[3] ), .Q1(\wb_adr[3] ));
RC
2023-09-21 09:45:45 +00:00
SLICE_49 SLICE_49( .D1(InitReady), .C1(\wb_adr[4] ), .B1(N_210),
.A1(\FS[15] ), .D0(InitReady), .C0(\wb_adr[3] ), .B0(N_210), .A0(\FS[15] ),
.DI1(N_385), .DI0(N_384), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_384),
.Q0(\wb_adr[4] ), .F1(N_385), .Q1(\wb_adr[5] ));
SLICE_50 SLICE_50( .B1(\wb_adr[6] ), .A1(InitReady), .D0(\FS[15] ),
.C0(\wb_adr[5] ), .B0(N_210), .A0(InitReady), .DI1(\wb_adr_5[7] ),
.DI0(N_386), .CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(N_386),
.Q0(\wb_adr[6] ), .F1(\wb_adr_5[7] ), .Q1(\wb_adr[7] ));
SLICE_51 SLICE_51( .D1(N_214), .C1(N_471_3), .B1(wb_cyc_stb_4_iv_0_a3_0_0),
.A1(N_471_2), .D0(un1_PHI2r3), .C0(N_471), .B0(CmdUFMWrite),
.A0(InitReady), .DI0(wb_cyc_stb_4), .CE(N_178), .LSR(wb_rst10),
.CLK(RCLK_c), .F0(wb_cyc_stb_4), .Q0(wb_cyc_stb), .F1(N_471));
SLICE_52 SLICE_52( .D1(N_207), .C1(\wb_dati_5_1_iv_0_1[1] ), .B1(\FS[11] ),
.A1(N_578), .D0(InitReady), .C0(\wb_dati_5_0_iv_0_a3_1[0] ), .B0(wb_we),
.A0(N_576), .DI1(\wb_dati_5[1] ), .DI0(\wb_dati_5[0] ),
.CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[0] ),
.Q0(\wb_dati[0] ), .F1(\wb_dati_5[1] ), .Q1(\wb_dati[1] ));
SLICE_53 SLICE_53( .D1(\wb_dati_5_1_iv_i_i_0[3] ),
.C1(\wb_dati_5_1_iv_i_i_1[3] ), .B1(\wb_dati_5_1_iv_i_i_a3_1[3] ),
.A1(N_579), .D0(N_361), .C0(\wb_dati[1] ), .A0(InitReady),
.DI1(\wb_dati_5_1_iv_i_i[3] ), .DI0(\wb_dati_5[2] ), .CE(un1_wb_rst14_i_0),
.CLK(RCLK_c), .F0(\wb_dati_5[2] ), .Q0(\wb_dati[2] ),
.F1(\wb_dati_5_1_iv_i_i[3] ), .Q1(\wb_dati[3] ));
SLICE_54 SLICE_54( .D1(InitReady), .C1(N_361), .A1(\wb_dati[4] ),
.D0(\wb_dati_5_1_iv_0_0[4] ), .C0(\FS[9] ), .B0(\wb_dati_5_1_iv_0_1[4] ),
.A0(N_578), .DI1(\wb_dati_5[5] ), .DI0(\wb_dati_5[4] ),
.CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[4] ),
.Q0(\wb_dati[4] ), .F1(\wb_dati_5[5] ), .Q1(\wb_dati[5] ));
SLICE_55 SLICE_55( .D1(N_484), .C1(N_486), .B1(N_488),
.A1(\wb_dati_5_1_iv_0_0[7] ), .D0(N_207), .C0(N_578), .B0(\FS[11] ),
.A0(\wb_dati_5_1_iv_0_1[6] ), .DI1(\wb_dati_5[7] ), .DI0(\wb_dati_5[6] ),
.CE(un1_wb_rst14_i_0), .CLK(RCLK_c), .F0(\wb_dati_5[6] ),
.Q0(\wb_dati[6] ), .F1(\wb_dati_5[7] ), .Q1(\wb_dati[7] ));
SLICE_56 SLICE_56( .D1(\FS[17] ), .C1(\FS[16] ), .B1(N_581), .A1(InitReady),
.C0(N_92_i), .B0(N_31_i), .A0(wb_req), .DI0(wb_reqe_0), .LSR(wb_rst10),
.CLK(RCLK_c), .F0(wb_reqe_0), .Q0(wb_req), .F1(N_31_i));
SLICE_57 SLICE_57( .D1(InitReady), .C1(\FS[16] ), .B1(\FS[17] ),
.A1(\FS[15] ), .D0(wb_rst10), .C0(N_515), .B0(N_92_i), .A0(wb_rst),
.DI0(wb_rste_0), .CLK(RCLK_c), .F0(wb_rste_0), .Q0(wb_rst), .F1(wb_rst10));
SLICE_58 SLICE_58( .D1(InitReady), .C1(\wb_adr[0] ), .B1(N_210),
.A1(\FS[15] ), .D0(InitReady), .C0(CmdUFMData), .B0(N_210),
.A0(wb_we_0_i_0_1), .DI0(N_231_i), .CE(un1_wb_rst14_i_0), .LSR(wb_rst10),
.CLK(RCLK_c), .F0(N_231_i), .Q0(wb_we), .F1(N_382));
wb_dati_5_1_iv_0_o3_5__SLICE_59 \wb_dati_5_1_iv_0_o3[5]/SLICE_59 (
.D1(N_214), .C1(\FS[12] ), .B1(N_479), .A1(N_217), .D0(N_214), .C0(N_209),
.B0(N_479), .A0(\FS[13] ), .M0(\FS[9] ), .OFX0(N_361));
SLICE_60 SLICE_60( .D1(Ready), .C1(CO0), .B1(m3_0_a2_0), .A1(CBR_fast),
.D0(CO0), .C0(N_408), .B0(nRCAS_0_sqmuxa_1), .A0(\S[1] ), .F0(N_248_i_sx),
.F1(nRCAS_0_sqmuxa_1));
SLICE_61 SLICE_61( .D1(\S[1] ), .C1(N_408), .B1(Ready), .A1(CO0),
.D0(un1_nRCAS_6_sqmuxa_i_0_0), .C0(CO0), .B0(CASr2),
.F0(nRCAS_r_i_0_o2_0_0), .F1(un1_nRCAS_6_sqmuxa_i_0_0));
SLICE_62 SLICE_62( .D1(\FS[10] ), .C1(InitReady), .B1(\FS[11] ),
.A1(\FS[9] ), .D0(\FS[14] ), .C0(InitReady), .B0(N_599), .F0(N_407),
.F1(N_599));
SLICE_63 SLICE_63( .D1(N_427), .C1(N_207), .B1(\FS[12] ),
.A1(wb_we_0_i_0_a3_0_0), .D0(N_407), .C0(wb_we_0_i_0_0), .B0(\FS[12] ),
.A0(\FS[13] ), .F0(wb_we_0_i_0_1), .F1(wb_we_0_i_0_0));
SLICE_64 SLICE_64( .D1(\Din_c[6] ), .C1(N_539), .B1(\MAin_c[0] ),
.A1(\Din_c[3] ), .D0(N_594), .C0(N_518), .B0(\MAin_c[0] ),
.A0(\MAin_c[1] ), .F0(un1_CmdEnable20_0_0_0), .F1(N_594));
SLICE_65 SLICE_65( .D1(\FS[10] ), .C1(\FS[9] ),
.B1(\wb_adr_5_i_0_a3_0_1[0] ), .A1(N_424), .D0(N_542), .C0(\FS[9] ),
.B0(\wb_adr_5_i_0_1[0] ), .A0(N_208), .F0(\wb_adr_5_i_0_3[0] ),
.F1(\wb_adr_5_i_0_1[0] ));
SLICE_66 SLICE_66( .D1(InitReady), .C1(\FS[15] ), .B1(\FS[17] ),
.A1(\FS[16] ), .D0(InitReady), .C0(N_214), .B0(\wb_dati[6] ),
.A0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .F0(\wb_dati_5_1_iv_0_0[7] ),
.F1(N_214));
SLICE_67 SLICE_67( .D1(N_579), .C1(\FS[9] ), .B1(N_208), .A1(\FS[10] ),
.D0(\FS[10] ), .B0(\FS[13] ), .A0(\FS[11] ), .F0(N_208),
.F1(\wb_dati_5_1_iv_0_0[4] ));
SLICE_68 SLICE_68( .D1(\FS[9] ), .C1(\FS[10] ), .A1(\FS[11] ),
.D0(\ufmefb/g0_0_a3_2 ), .C0(N_214), .A0(N_226), .F0(N_4), .F1(N_226));
SLICE_69 SLICE_69( .D1(N_214), .C1(\FS[14] ),
.B1(\wb_dati_5_1_iv_0_a3_0_1[1] ), .A1(\FS[12] ), .D0(\FS[11] ),
.C0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[13] ),
.F0(\wb_dati_5_1_iv_0_a3_0_1[1] ), .F1(N_477));
SLICE_70 SLICE_70( .D1(\FS[13] ), .C1(N_236), .B1(N_542), .A1(\FS[11] ),
.D0(\FS[14] ), .C0(\FS[12] ), .B0(InitReady), .F0(N_542), .F1(N_424));
SLICE_71 SLICE_71( .D1(N_596), .C1(N_412), .B1(N_536), .A1(N_502),
.D0(\FS[10] ), .C0(\FS[9] ), .A0(\FS[11] ), .F0(N_596),
.F1(\wb_dati_5_1_iv_i_i_1[3] ));
SLICE_72 SLICE_72( .D1(RCKE_c), .C1(RASr2), .B1(N_522), .A1(nRRAS_0_sqmuxa),
.C0(CO0), .B0(\S[1] ), .A0(Ready), .F0(nRRAS_0_sqmuxa),
.F1(nRCS_9_u_i_0_o3));
SLICE_73 SLICE_73( .D1(\wb_dati[2] ), .C1(\wb_dati_5_1_iv_i_i_a3_3_0[3] ),
.B1(InitReady), .A1(N_502), .D0(\FS[12] ), .C0(\FS[9] ), .B0(\FS[10] ),
.A0(\FS[11] ), .F0(\wb_dati_5_1_iv_i_i_a3_3_0[3] ),
.F1(\wb_dati_5_1_iv_i_i_0[3] ));
SLICE_74 SLICE_74( .D1(\IS[2] ), .C1(\IS[3] ), .A1(\IS[1] ), .D0(InitReady),
.C0(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .B0(RASr2), .A0(Ready), .F0(N_408),
.F1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0));
SLICE_75 SLICE_75( .D1(\FS[14] ), .B1(InitReady), .D0(\FS[12] ), .C0(N_207),
.B0(N_515), .A0(\FS[11] ), .F0(\wb_adr_5_i_0_0[1] ), .F1(N_515));
SLICE_76 SLICE_76( .D1(\FS[10] ), .C1(\FS[11] ), .B1(\FS[14] ),
.A1(\FS[13] ), .D0(N_214), .C0(N_217), .B0(\FS[9] ), .A0(\FS[12] ),
.F0(N_486), .F1(N_217));
SLICE_77 SLICE_77( .D1(\FS[13] ), .C1(\FS[12] ), .B1(\FS[14] ), .A1(N_214),
.D0(\FS[9] ), .C0(N_578), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_484),
.F1(N_578));
SLICE_78 SLICE_78( .D1(N_221), .C1(\IS[0] ), .B1(N_216),
.A1(un1_nRCAS_6_sqmuxa_i_0_0_o2_0), .D0(nRRAS_0_sqmuxa), .C0(N_522),
.B0(RASr2), .A0(RCKE_c), .F0(N_246_i), .F1(N_522));
SLICE_79 SLICE_79( .D1(InitReady), .A1(RASr2), .D0(CO0), .C0(N_221),
.B0(\S[1] ), .A0(Ready), .F0(N_360_i), .F1(N_221));
SLICE_80 SLICE_80( .D1(\MAin_c[1] ), .C1(N_518), .B1(N_593),
.D0(un1_CmdEnable20_0_0_0), .C0(un1_CmdEnable20_0_0_a3_1_1),
.B0(un1_CmdEnable20_0_0_o3), .A0(C1Submitted), .M1(nCCAS_c_i),
.M0(nCCAS_c_i), .CLK(nCRAS_c), .F0(un1_CmdEnable20_i), .Q0(CBR),
.F1(un1_CmdEnable20_0_0_a3_1_1), .Q1(CBR_fast));
SLICE_81 SLICE_81( .D1(\S[1] ), .C1(Ready), .A1(CBR), .D0(nRWE_s_i_0_tz_0),
.C0(N_590), .B0(N_595), .A0(nRCAS_0_sqmuxa_1), .F0(N_49_i), .F1(N_590));
SLICE_82 SLICE_82( .D1(\Din_c[5] ), .C1(\Din_c[4] ), .B1(N_213),
.A1(\Din_c[3] ), .C0(N_531), .B0(XOR8MEG18), .M0(\Din_c[0] ),
.CE(CmdUFMData_1_sqmuxa), .CLK(PHI2_c), .F0(CmdUFMData_1_sqmuxa),
.Q0(CmdUFMData), .F1(N_531));
SLICE_83 SLICE_83( .D1(CO0), .B1(FWEr), .D0(N_595), .C0(nRCS_9_u_i_0_o3),
.B0(N_590), .A0(N_248_i_1_0), .F0(N_247_i), .F1(N_248_i_1_0));
SLICE_84 SLICE_84( .D1(\Bank[1] ), .C1(\Bank[3] ), .B1(\Bank[4] ),
.A1(\Bank[5] ), .D0(un1_CmdEnable20_0_0_o3_10),
.C0(un1_CmdEnable20_0_0_o3_11), .B0(\Bank[7] ), .A0(\Bank[6] ),
.F0(un1_CmdEnable20_0_0_o3), .F1(un1_CmdEnable20_0_0_o3_11));
SLICE_85 SLICE_85( .D1(N_576), .C1(N_537), .B1(\FS[10] ), .A1(N_514),
.D0(InitReady), .C0(\wb_dati[5] ), .B0(N_473), .A0(N_472),
.F0(\wb_dati_5_1_iv_0_1[6] ), .F1(N_473));
SLICE_86 SLICE_86( .D1(\FS[11] ), .C1(N_536), .B1(N_207), .A1(N_502),
.D0(N_479), .C0(\wb_dati[3] ), .B0(InitReady), .A0(N_473),
.F0(\wb_dati_5_1_iv_0_1[4] ), .F1(N_479));
SLICE_87 SLICE_87( .D1(N_214), .C1(\FS[14] ), .A1(\FS[12] ), .D0(\FS[10] ),
.C0(N_579), .B0(\FS[11] ), .A0(\FS[13] ), .F0(N_488), .F1(N_579));
SLICE_88 SLICE_88( .D1(CO0), .C1(\S[1] ), .B1(Ready), .A1(N_221),
.D0(\IS[3] ), .C0(\IS[1] ), .B0(\IS[2] ), .A0(nRCS_9_u_i_0_o2_1_RNIL2K71),
.F0(RA10s_i), .F1(nRCS_9_u_i_0_o2_1_RNIL2K71));
SLICE_89 SLICE_89( .C1(\FS[9] ), .B1(\FS[10] ), .D0(\FS[13] ), .C0(N_236),
.B0(N_579), .A0(\FS[11] ), .F0(N_472), .F1(N_236));
SLICE_90 SLICE_90( .D1(\IS[1] ), .C1(nRCS_9_u_i_0_o2_1_RNIL2K71),
.B1(\IS[0] ), .A1(\IS[2] ), .D0(nRRAS_0_sqmuxa), .C0(nRWE_s_i_0_a3_1_0),
.B0(RCKE_c), .A0(RASr2), .F0(nRWE_s_i_0_tz_0), .F1(nRWE_s_i_0_a3_1_0));
SLICE_91 SLICE_91( .D1(N_214), .C1(\FS[13] ), .B1(\FS[9] ), .A1(N_209),
.D0(InitReady), .C0(\wb_dati[0] ), .B0(N_412), .A0(N_477),
.F0(\wb_dati_5_1_iv_0_1[1] ), .F1(N_412));
SLICE_92 SLICE_92( .D1(wb_req), .C1(\FS[0] ), .B1(N_471_3), .D0(N_471_2),
.C0(wb_ack), .B0(wb_cyc_stb_2_sqmuxa_i_a3_0), .A0(N_214), .F0(N_178),
.F1(wb_cyc_stb_2_sqmuxa_i_a3_0));
SLICE_93 SLICE_93( .D1(\MAin_c[7] ), .C1(\MAin_c[2] ), .B1(\MAin_c[3] ),
.A1(\MAin_c[5] ), .D0(\Bank[0] ), .C0(\Bank[2] ),
.B0(un1_CmdEnable20_0_0_o3_4), .A0(un1_CmdEnable20_0_0_o3_3),
.F0(un1_CmdEnable20_0_0_o3_10), .F1(un1_CmdEnable20_0_0_o3_4));
SLICE_94 SLICE_94( .D1(N_248_i_1), .C1(N_248_i_1_0), .B1(N_248_i_sx),
.A1(N_248_i_1_1), .D0(nRCAS_r_i_0_o2_0_0), .C0(FWEr), .B0(N_267), .A0(CBR),
.F0(N_248_i_1), .F1(N_248_i));
SLICE_95 SLICE_95( .D1(\FS[12] ), .A1(\FS[13] ), .D0(N_536), .C0(InitReady),
.B0(N_207), .A0(\FS[11] ), .F0(N_427), .F1(N_536));
SLICE_96 SLICE_96( .D1(\FS[14] ), .C1(InitReady), .D0(N_511), .C0(N_404),
.B0(\FS[12] ), .A0(\FS[13] ), .F0(\wb_adr_5_i_0_0[0] ), .F1(N_511));
SLICE_97 SLICE_97( .C1(\FS[16] ), .B1(\FS[17] ), .D0(N_210),
.C0(\wb_dati[7] ), .B0(InitReady), .A0(\FS[15] ), .F0(N_383), .F1(N_210));
SLICE_98 SLICE_98( .B1(\FS[4] ), .A1(\FS[3] ), .D0(\FS[2] ), .C0(\FS[7] ),
.B0(wb_cyc_stb_4_iv_0_a3_0_2_0), .A0(\FS[6] ), .F0(N_471_2),
.F1(wb_cyc_stb_4_iv_0_a3_0_2_0));
SLICE_99 SLICE_99( .C1(\Din_c[3] ), .B1(\Din_c[5] ), .D0(\MAin_c[0] ),
.C0(\Din_c[6] ), .B0(N_505), .A0(\Din_c[2] ), .F0(N_593), .F1(N_505));
SLICE_100 SLICE_100( .C1(\Din_c[7] ), .A1(\Din_c[6] ),
.D0(XOR8MEG_3_u_0_0_0_a2), .C0(N_213), .B0(N_539), .A0(\Din_c[3] ),
.F0(XOR8MEG_3_u_0_0_a3_0_2), .F1(N_213));
SLICE_101 SLICE_101( .D1(\FS[14] ), .C1(\FS[12] ), .D0(N_537), .C0(\FS[10] ),
.B0(\FS[9] ), .A0(N_514), .F0(\wb_dati_5_1_iv_0_a3_0_1[7] ), .F1(N_537));
SLICE_102 SLICE_102( .D1(\FS[11] ), .A1(\FS[13] ), .D0(\FS[10] ),
.C0(\FS[12] ), .B0(\FS[14] ), .A0(N_514), .F0(\wb_dati_5_0_iv_0_a3_1[0] ),
.F1(N_514));
SLICE_103 SLICE_103( .C1(PHI2r3), .B1(PHI2r2), .D0(CmdValid_fast),
.C0(CmdUFMShift), .B0(G_4_0_a3_0), .A0(InitReady), .F0(un1_wb_rst14_i_0),
.F1(G_4_0_a3_0));
SLICE_104 SLICE_104( .C1(\FS[14] ), .B1(\FS[13] ), .A1(\FS[12] ),
.D0(wb_ack), .C0(\FS[14] ), .B0(\FS[13] ), .A0(\FS[12] ),
.F0(\ufmefb/g0_0_a3_2 ), .F1(N_581));
SLICE_105 SLICE_105( .D1(\FS[14] ), .C1(InitReady), .B1(N_226),
.A1(\FS[13] ), .D0(\FS[14] ), .C0(InitReady), .B0(\FS[13] ),
.F0(wb_we_0_i_0_a3_0_0), .F1(N_417));
SLICE_106 SLICE_106( .D1(\FS[12] ), .C1(\FS[13] ), .B1(N_599), .A1(\FS[14] ),
.D0(\FS[12] ), .C0(\FS[13] ), .B0(N_599), .F0(N_423), .F1(N_416));
SLICE_107 SLICE_107( .C1(CmdValid), .B1(PHI2r3), .A1(PHI2r2), .D0(InitReady),
.C0(CmdValid), .B0(PHI2r3), .A0(PHI2r2), .M0(CASr2), .CLK(RCLK_c),
.F0(N_92_i), .Q0(CASr3), .F1(un1_PHI2r3));
SLICE_108 SLICE_108( .D1(FWEr), .C1(\S[1] ), .B1(CASr2), .A1(CO0), .D0(FWEr),
.C0(CASr3), .B0(CASr2), .A0(CO0), .F0(N_595), .F1(RCKEEN_8_u_0_1_0));
SLICE_109 SLICE_109( .D1(\FS[10] ), .C1(\FS[9] ), .B1(\FS[13] ),
.A1(\FS[11] ), .D0(\FS[10] ), .C0(\FS[9] ), .A0(\FS[11] ), .F0(N_404),
.F1(\wb_dati_5_1_iv_i_i_a3_1[3] ));
SLICE_110 SLICE_110( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[12] ),
.A1(InitReady), .D0(\FS[10] ), .C0(\FS[14] ), .B0(\FS[11] ), .A0(\FS[12] ),
.F0(N_209), .F1(\wb_adr_5_i_0_a3_0_1[0] ));
SLICE_111 SLICE_111( .D1(nRowColSel), .A1(\MAin_c[9] ), .D0(nRowColSel),
.A0(\MAin_c[9] ), .F0(RDQMH_c), .F1(RDQML_c));
SLICE_112 SLICE_112( .D1(\Din_c[1] ), .C1(\Din_c[4] ), .B1(\Din_c[7] ),
.A1(\Din_c[0] ), .C0(\Din_c[4] ), .A0(\Din_c[0] ),
.F0(XOR8MEG_3_u_0_0_0_a2), .F1(N_518));
SLICE_113 SLICE_113( .D1(\FS[14] ), .C1(N_214), .C0(N_214), .B0(\FS[9] ),
.F0(N_576), .F1(N_502));
SLICE_114 SLICE_114( .D1(nRowColSel), .C1(\RowA[6] ), .A1(\MAin_c[6] ),
.C0(nFWE_c), .B0(\MAin_c[4] ), .A0(\MAin_c[6] ),
.F0(un1_CmdEnable20_0_0_o3_3), .F1(\RA_c[6] ));
SLICE_115 SLICE_115( .D1(\RowA[9] ), .C1(nRowColSel), .A1(\MAin_c[9] ),
.D0(\MAin_c[8] ), .C0(nRowColSel), .B0(\RowA[8] ), .F0(\RA_c[8] ),
.F1(\RA_c[9] ));
SLICE_116 SLICE_116( .D1(\RowA[7] ), .C1(nRowColSel), .B1(\MAin_c[7] ),
.D0(nRowColSel), .B0(\MAin_c[0] ), .A0(\RowA[0] ), .F0(\RA_c[0] ),
.F1(\RA_c[7] ));
SLICE_117 SLICE_117( .D1(\MAin_c[5] ), .C1(\RowA[5] ), .A1(nRowColSel),
.C0(nRowColSel), .B0(\RowA[1] ), .A0(\MAin_c[1] ), .F0(\RA_c[1] ),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.F1(\RA_c[5] ));
RC
2023-09-21 09:45:45 +00:00
SLICE_118 SLICE_118( .D1(nRowColSel), .C1(\MAin_c[4] ), .A1(\RowA[4] ),
.C0(\MAin_c[2] ), .B0(\RowA[2] ), .A0(nRowColSel), .F0(\RA_c[2] ),
.F1(\RA_c[4] ));
SLICE_119 SLICE_119( .D1(\Din_c[5] ), .C1(\Din_c[4] ), .B1(\Din_c[6] ),
.A1(\Din_c[7] ), .D0(\Din_c[5] ), .B0(\Din_c[2] ), .F0(N_539),
.F1(CmdLEDEN_4_u_i_0_a3_0_0));
SLICE_120 SLICE_120( .C1(\CROW_c[1] ), .B1(Ready_fast), .D0(\Din_c[6] ),
.C0(XOR8MEG), .B0(Ready_fast), .A0(n8MEGEN), .F0(RA11d_0),
.F1(\RBAd_0[1] ));
SLICE_121 SLICE_121( .B1(wb_req), .A1(\FS[0] ), .C0(\FS[8] ), .B0(\FS[5] ),
.A0(\FS[1] ), .F0(N_471_3), .F1(wb_cyc_stb_4_iv_0_a3_0_0));
SLICE_122 SLICE_122( .D1(InitReady), .C1(\wb_dato[0] ), .A1(Cmdn8MEGEN),
.B0(PHI2r3), .A0(PHI2r2), .F0(g1_0), .F1(n8MEGENe_1_0));
SLICE_123 SLICE_123( .D1(\FS[10] ), .B1(\FS[9] ), .C0(\FS[16] ),
.B0(\FS[17] ), .A0(\FS[15] ), .F0(InitReady3_0_a3_1), .F1(N_207));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .IOLDO(\WRD[0] ), .PADDT(RD_1_i),
.RD0(RD[0]));
RD_0__MGIOL \RD[0]_MGIOL ( .IOLDO(\WRD[0] ), .OPOS(\Din_c[0] ),
.CLK(nCCAS_c));
Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2));
PHI2_MGIOL PHI2_MGIOL( .DI(PHI2_c), .CLK(RCLK_c), .IN(PHI2r));
RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML));
RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH));
nRCAS nRCAS_I( .IOLDO(nRCAS_c), .nRCAS(nRCAS));
RC
2023-09-21 09:45:45 +00:00
nRCAS_MGIOL nRCAS_MGIOL( .IOLDO(nRCAS_c), .OPOS(N_248_i), .CLK(RCLK_c));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
nRRAS nRRAS_I( .IOLDO(nRRAS_c), .nRRAS(nRRAS));
RC
2023-09-21 09:45:45 +00:00
nRRAS_MGIOL nRRAS_MGIOL( .IOLDO(nRRAS_c), .OPOS(N_246_i), .CLK(RCLK_c));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE));
RC
2023-09-21 09:45:45 +00:00
nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(N_49_i), .CLK(RCLK_c));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE));
RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK));
nRCS nRCS_I( .IOLDO(nRCS_c), .nRCS(nRCS));
RC
2023-09-21 09:45:45 +00:00
nRCS_MGIOL nRCS_MGIOL( .IOLDO(nRCS_c), .OPOS(N_247_i), .CLK(RCLK_c));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .IOLDO(\WRD[7] ), .PADDT(RD_1_i),
.RD7(RD[7]));
RD_7__MGIOL \RD[7]_MGIOL ( .IOLDO(\WRD[7] ), .OPOS(\Din_c[7] ),
.CLK(nCCAS_c));
RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .IOLDO(\WRD[6] ), .PADDT(RD_1_i),
.RD6(RD[6]));
RD_6__MGIOL \RD[6]_MGIOL ( .IOLDO(\WRD[6] ), .OPOS(\Din_c[6] ),
.CLK(nCCAS_c));
RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .IOLDO(\WRD[5] ), .PADDT(RD_1_i),
.RD5(RD[5]));
RD_5__MGIOL \RD[5]_MGIOL ( .IOLDO(\WRD[5] ), .OPOS(\Din_c[5] ),
.CLK(nCCAS_c));
RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .IOLDO(\WRD[4] ), .PADDT(RD_1_i),
.RD4(RD[4]));
RD_4__MGIOL \RD[4]_MGIOL ( .IOLDO(\WRD[4] ), .OPOS(\Din_c[4] ),
.CLK(nCCAS_c));
RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .IOLDO(\WRD[3] ), .PADDT(RD_1_i),
.RD3(RD[3]));
RD_3__MGIOL \RD[3]_MGIOL ( .IOLDO(\WRD[3] ), .OPOS(\Din_c[3] ),
.CLK(nCCAS_c));
RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .IOLDO(\WRD[2] ), .PADDT(RD_1_i),
.RD2(RD[2]));
RD_2__MGIOL \RD[2]_MGIOL ( .IOLDO(\WRD[2] ), .OPOS(\Din_c[2] ),
.CLK(nCCAS_c));
RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .IOLDO(\WRD[1] ), .PADDT(RD_1_i),
.RD1(RD[1]));
RD_1__MGIOL \RD[1]_MGIOL ( .IOLDO(\WRD[1] ), .OPOS(\Din_c[1] ),
.CLK(nCCAS_c));
RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11]));
RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(RA11d_0),
.CLK(PHI2_c));
RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10]));
RC
2023-09-21 09:45:45 +00:00
RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\IS_i[0] ),
.LSR(RA10s_i), .CLK(RCLK_c));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RA_9_ \RA[9]_I ( .PADDO(\RA_c[9] ), .RA9(RA[9]));
RA_8_ \RA[8]_I ( .PADDO(\RA_c[8] ), .RA8(RA[8]));
RA_7_ \RA[7]_I ( .PADDO(\RA_c[7] ), .RA7(RA[7]));
RA_6_ \RA[6]_I ( .PADDO(\RA_c[6] ), .RA6(RA[6]));
RA_5_ \RA[5]_I ( .PADDO(\RA_c[5] ), .RA5(RA[5]));
RA_4_ \RA[4]_I ( .PADDO(\RA_c[4] ), .RA4(RA[4]));
RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3]));
RA_2_ \RA[2]_I ( .PADDO(\RA_c[2] ), .RA2(RA[2]));
RA_1_ \RA[1]_I ( .PADDO(\RA_c[1] ), .RA1(RA[1]));
RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0]));
RBA_1_ \RBA[1]_I ( .IOLDO(\RBA_c[1] ), .RBA1(RBA[1]));
RBA_1__MGIOL \RBA[1]_MGIOL ( .IOLDO(\RBA_c[1] ), .OPOS(\RBAd_0[1] ),
.CLK(nCRAS_c));
RBA_0_ \RBA[0]_I ( .IOLDO(\RBA_c[0] ), .RBA0(RBA[0]));
RBA_0__MGIOL \RBA[0]_MGIOL ( .IOLDO(\RBA_c[0] ), .OPOS(\RBAd_0[0] ),
.CLK(nCRAS_c));
LED LED_I( .PADDO(LED_c), .LED(LED));
nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE));
nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS));
nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS));
Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
Din_7__MGIOL \Din[7]_MGIOL ( .DI(\Din_c[7] ), .CLK(PHI2_c), .IN(\Bank[7] ));
Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
Din_6__MGIOL \Din[6]_MGIOL ( .DI(\Din_c[6] ), .CLK(PHI2_c), .IN(\Bank[6] ));
Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
Din_5__MGIOL \Din[5]_MGIOL ( .DI(\Din_c[5] ), .CLK(PHI2_c), .IN(\Bank[5] ));
Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
Din_4__MGIOL \Din[4]_MGIOL ( .DI(\Din_c[4] ), .CLK(PHI2_c), .IN(\Bank[4] ));
Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
Din_3__MGIOL \Din[3]_MGIOL ( .DI(\Din_c[3] ), .CLK(PHI2_c), .IN(\Bank[3] ));
Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
Din_2__MGIOL \Din[2]_MGIOL ( .DI(\Din_c[2] ), .CLK(PHI2_c), .IN(\Bank[2] ));
Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
Din_1__MGIOL \Din[1]_MGIOL ( .DI(\Din_c[1] ), .CLK(PHI2_c), .IN(\Bank[1] ));
Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
Din_0__MGIOL \Din[0]_MGIOL ( .DI(\Din_c[0] ), .CLK(PHI2_c), .IN(\Bank[0] ));
CROW_1_ \CROW[1]_I ( .PADDI(\CROW_c[1] ), .CROW1(CROW[1]));
CROW_0_ \CROW[0]_I ( .PADDI(\CROW_c[0] ), .CROW0(CROW[0]));
MAin_9_ \MAin[9]_I ( .PADDI(\MAin_c[9] ), .MAin9(MAin[9]));
MAin_8_ \MAin[8]_I ( .PADDI(\MAin_c[8] ), .MAin8(MAin[8]));
MAin_7_ \MAin[7]_I ( .PADDI(\MAin_c[7] ), .MAin7(MAin[7]));
MAin_6_ \MAin[6]_I ( .PADDI(\MAin_c[6] ), .MAin6(MAin[6]));
MAin_5_ \MAin[5]_I ( .PADDI(\MAin_c[5] ), .MAin5(MAin[5]));
MAin_4_ \MAin[4]_I ( .PADDI(\MAin_c[4] ), .MAin4(MAin[4]));
MAin_3_ \MAin[3]_I ( .PADDI(\MAin_c[3] ), .MAin3(MAin[3]));
MAin_2_ \MAin[2]_I ( .PADDI(\MAin_c[2] ), .MAin2(MAin[2]));
MAin_1_ \MAin[1]_I ( .PADDI(\MAin_c[1] ), .MAin1(MAin[1]));
MAin_0_ \MAin[0]_I ( .PADDI(\MAin_c[0] ), .MAin0(MAin[0]));
ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(RCLK_c), .WBRSTI(wb_rst),
.WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we),
.WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ),
.WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ),
.WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ),
.WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ),
.WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ),
.WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ),
.WBACKO(wb_ack));
VHI VHI_INST( .Z(VCCI));
PUR PUR_INST( .PUR(VCCI));
GSR GSR_INST( .GSR(VCCI));
endmodule
module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly;
vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module vcc ( output PWR1 );
VHI INST1( .Z(PWR1));
endmodule
module gnd ( output PWR0 );
VLO INST1( .Z(PWR0));
endmodule
module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
defparam inst1.INIT0 = 16'h000A;
defparam inst1.INIT1 = 16'h300A;
defparam inst1.INJECT1_0 = "NO";
defparam inst1.INJECT1_1 = "NO";
endmodule
module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
vmuxregsre \FS[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
ccu20001 \FS_s_0[17] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1());
specify
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
defparam inst1.INIT0 = 16'h5002;
defparam inst1.INIT1 = 16'h300A;
defparam inst1.INJECT1_0 = "NO";
defparam inst1.INJECT1_1 = "NO";
endmodule
module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre \FS[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20002 \FS_cry_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
defparam inst1.INIT0 = 16'h300A;
defparam inst1.INIT1 = 16'h300A;
defparam inst1.INJECT1_0 = "NO";
defparam inst1.INJECT1_1 = "NO";
endmodule
module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
specify
(A1 => F1) = (0:0:0,0:0:0);
(A1 => FCO) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(A0 => F1) = (0:0:0,0:0:0);
(A0 => FCO) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
(FCI => F0) = (0:0:0,0:0:0);
(FCI => F1) = (0:0:0,0:0:0);
(FCI => FCO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
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module SLICE_10 ( input D1, C1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
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RC
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lut4 un1_ADWR_i_i_a2( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40003 ADSubmitted_r_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
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vmuxregsre ADSubmitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
module lut4 ( input A, B, C, D, output Z );
RC
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ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40003 ( input A, B, C, D, output Z );
RC
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ROM16X1A #(16'h5150) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
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endmodule
module inverter ( input I, output Z );
INV INST1( .A(I), .Z(Z));
endmodule
RC
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module SLICE_11 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
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RC
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lut40004 CmdEnable16_0_a2_1_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40005 C1Submitted_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
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vmuxregsre C1Submitted( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
RC
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gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
module lut40004 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40005 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFAF2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_12 ( input D0, DI0, M1, CLK, output F0, Q0, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
RC
2023-09-21 09:45:45 +00:00
lut40006 nCCAS_pad_RNISUR8( .A(GNDI), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre CASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
specify
RC
2023-09-21 09:45:45 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40006 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h00FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_16 ( input C1, A1, C0, A0, DI0, LSR, CLK, output F0, Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
RC
2023-09-21 09:45:45 +00:00
lut40007 nRowColSel_0_0_0_x2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40008 \S_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre0009 \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40007 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h5A5A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40008 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module vmuxregsre0009 ( input D0, D1, SD, SP, CK, LSR, output Q );
FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_17 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40010 un1_CmdEnable20_0_0_a2_0_RNI00E51( .A(A1), .B(B1), .C(C1), .D(D1),
.Z(F1));
lut40011 CmdEnable_s( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre CmdEnable( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
RC
2023-09-21 09:45:45 +00:00
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
module lut40010 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40011 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFE2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0,
Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40012 CmdLEDEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40013 CmdLEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdLEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
module lut40012 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h44F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40013 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h3131) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module SLICE_20 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40014 CmdUFMShift_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre CmdUFMShift( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
module lut40014 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_21 ( input D1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
F1 );
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40015 CmdUFMWrite_3_u_0_0_0_a3( .A(A1), .B(GNDI), .C(GNDI), .D(D1),
.Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40016 CmdUFMWrite_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre CmdUFMWrite( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40015 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40016 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_22 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40017 CmdValid_2_i_o2_1_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40018 CmdValid_r( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdValid( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40017 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFF3B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40018 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_23 ( input D1, C1, B1, A1, C0, B0, DI0, CLK, output F0, Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40019 CmdUFMData_1_sqmuxa_0_a3_3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40020 CmdValid_r_fast( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre CmdValid_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40019 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40020 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_24 ( input D1, C1, B1, A1, D0, C0, B0, DI0, CE, CLK, output F0,
Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40021 Cmdn8MEGEN_4_u_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40022 Cmdn8MEGEN_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Cmdn8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40021 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hB3A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40022 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_25 ( input B1, A1, A0, DI0, CLK, output F0, Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40023 nCCAS_pad_RNI01SJ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40024 FWEr_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre FWEr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
specify
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40023 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40024 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_26 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40025 RCKEEN_8_u_0_0_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40026 \IS_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \IS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40025 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40026 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h9999) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_27 ( input C1, B1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
F1, Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40027 \IS_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40007 IS_n1_0_x2_0_x2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \IS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre \IS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40027 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_28 ( input B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40028 RA10_0io_RNO( .A(GNDI), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40029 \IS_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \IS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40028 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h3333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40029 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h6AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_29 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40030 InitReady3_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40031 InitReady_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre InitReady( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40030 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40031 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_30 ( input C1, B1, A1, D0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40032 LEDEN_6_i_m2_i_m2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40033 LEDENe( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
RC
2023-09-21 09:45:45 +00:00
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40032 ( input A, B, C, D, output Z );
ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40033 ( input A, B, C, D, output Z );
ROM16X1A #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_31 ( input B0, A0, M1, M0, CLK, output F0, Q0, Q1 );
wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly;
lut40034 \RBAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre PHI2r3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre PHI2r2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40034 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_32 ( input D1, C1, B1, C0, DI0, M1, CLK, output F0, Q0, F1, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly;
RC
2023-09-21 09:45:45 +00:00
lut40035 LED_pad_RNO( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40036 RASr_RNO( .A(GNDI), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre RASr2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre RASr( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40035 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFF3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40036 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_33 ( input D1, C1, B1, C0, A0, M0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, M0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40037 \un9_RA_i_m2_i_m2[3] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40038 CmdEnable_0_sqmuxa_0_a3_0_a3( .A(A0), .B(GNDI), .C(C0), .D(GNDI),
.Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre RASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
RC
2023-09-21 09:45:45 +00:00
vcc DRIVEVCC( .PWR1(VCCI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40037 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCCF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40038 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40039 RCKEEN_8_u_0_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40040 RCKEEN_8_u_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre RCKEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40039 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h444E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40040 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_35 ( input C1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40041 RASr2_RNI6PUF( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40042 RCKE_2_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre RCKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40041 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40042 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_36 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40043 Ready_0_sqmuxa_0_a2_4_o2( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
lut40044 Ready_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40043 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40044 ( input A, B, C, D, output Z );
ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_37 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40045 Ready_0_sqmuxa_0_a2_4_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40031 Ready_fast_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre Ready_fast( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module lut40045 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_38 ( input B1, A1, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
RC
2023-09-21 09:45:45 +00:00
lut40034 \RowAd[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40034 \RowAd[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \RowA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre \RowA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_39 ( input B1, A1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
RC
2023-09-21 09:45:45 +00:00
lut40034 \RowAd[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40046 \RowAd[2] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \RowA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre \RowA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(B1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40046 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_40 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40047 \RowAd[5] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40048 \RowAd[4] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \RowA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre \RowA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40047 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCFCF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40048 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_41 ( input C1, B1, C0, B0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
RC
2023-09-21 09:45:45 +00:00
lut40048 \RowAd[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40048 \RowAd[6] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \RowA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre \RowA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_42 ( input D1, A1, D0, C0, DI1, DI0, CLK, output F0, Q0, F1, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly;
RC
2023-09-21 09:45:45 +00:00
lut40049 \RowAd[9] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40050 \RowAd[8] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \RowA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre \RowA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(D0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40049 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40050 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_43 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
F1 );
wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly;
RC
2023-09-21 09:45:45 +00:00
lut40051 Ready_0_sqmuxa_0_a2_4_a3_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40052 \S_0_i_o2_i_o2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0009 \S[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40051 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40052 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
F0, Q0, F1 );
wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly;
lut40053 XOR8MEG_3_u_0_0_0_a3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40054 XOR8MEG_3_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre XOR8MEG( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
RC
2023-09-21 09:45:45 +00:00
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40053 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAAA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40054 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_45 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40055 CmdValid_RNIOOBE2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40056 n8MEGEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
vmuxregsre n8MEGEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40055 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40056 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_46 ( input C1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40057 nRowColSel_0_0_0_a2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40058 nRowColSel_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre0009 nRowColSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40057 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40058 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h88A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40059 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40060 \wb_adr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
RC
2023-09-21 09:45:45 +00:00
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40059 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40060 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_48 ( input D1, A1, C0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40015 \wb_adr_5[3] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40038 \wb_adr_5[2] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40061 \wb_adr_5_i_m2_i_m2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40061 \wb_adr_5_i_m2_i_m2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
RC
2023-09-21 09:45:45 +00:00
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40061 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_50 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
Q0, F1, Q1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40034 \wb_adr_5[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40062 \wb_adr_5_i_m2_i_m2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40062 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
output F0, Q0, F1 );
wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
RC
2023-09-21 09:45:45 +00:00
lut40063 wb_cyc_stb_4_iv_0_a3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40064 wb_cyc_stb_4_iv_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre0009 wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40063 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40064 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
RC
2023-09-21 09:45:45 +00:00
lut40065 \wb_dati_5_1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40066 \wb_dati_5_0_iv_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40065 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF0F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40066 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_53 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output
F0, Q0, F1, Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40067 \wb_dati_5_1_iv_i_i[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40068 \wb_dati_5_1_iv_0[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40067 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40068 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_54 ( input D1, C1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output
F0, Q0, F1, Q1 );
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40069 \wb_dati_5_1_iv_0[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40070 \wb_dati_5_1_iv_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40069 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40070 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
output F0, Q0, F1, Q1 );
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40071 \wb_dati_5_1_iv_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40072 \wb_dati_5_1_iv_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
RC
2023-09-21 09:45:45 +00:00
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40071 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40072 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_56 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
Q0, F1 );
wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
RC
2023-09-21 09:45:45 +00:00
lut40073 wb_reqe_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40074 wb_reqe( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
vmuxregsre0009 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40073 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40074 ( input A, B, C, D, output Z );
ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
Q0, F1 );
wire VCCI, GNDI, DI0_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
lut40075 \FS_RNIHVJI_0[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40076 wb_rste( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40075 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40076 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hE222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK,
output F0, Q0, F1 );
wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40061 \wb_adr_5_i_0_m2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40077 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
vmuxregsre0009 wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge LSR, 0:0:0);
$width (negedge LSR, 0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40077 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h5011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module wb_dati_5_1_iv_0_o3_5__SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0,
M0, output OFX0 );
wire
\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ,
\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40078 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1),
.D(D1),
.Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ));
lut40079 \wb_dati_5_1_iv_0_o3[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0),
.Z(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ));
selmux2 \wb_dati_5_1_iv_0_o3[5]/SLICE_59_K0K1MUX (
.D0(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/GATE_H0 ),
.D1(\wb_dati_5_1_iv_0_o3[5]/SLICE_59/wb_dati_5_1_iv_0_o3[5]/SLICE_59_K1_H1 ),
.SD(M0), .Z(OFX0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => OFX0) = (0:0:0,0:0:0);
(C1 => OFX0) = (0:0:0,0:0:0);
(B1 => OFX0) = (0:0:0,0:0:0);
(A1 => OFX0) = (0:0:0,0:0:0);
(D0 => OFX0) = (0:0:0,0:0:0);
(C0 => OFX0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => OFX0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A0 => OFX0) = (0:0:0,0:0:0);
(M0 => OFX0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40078 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCCCE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40079 ( input A, B, C, D, output Z );
ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
module selmux2 ( input D0, D1, SD, output Z );
MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40080 CBR_fast_RNIQ31K1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40081 nRCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40080 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40081 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCCCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_61 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40082 un1_nRCAS_6_sqmuxa_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40083 nRCAS_r_i_0_o2_0_2_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40082 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h33FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40083 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h00CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40084 \wb_adr_5_i_0_a2_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40085 wb_we_0_i_0_1_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40084 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40085 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40086 wb_we_0_i_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40087 wb_we_0_i_0_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40086 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFA2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40087 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40088 un1_CmdEnable20_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40089 un1_CmdEnable20_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40088 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40089 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40090 \wb_adr_5_i_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40091 \wb_adr_5_i_0_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40090 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAEEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40091 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40092 \FS_RNIHVJI[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40093 \wb_dati_5_1_iv_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40092 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40093 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_67 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40094 \wb_dati_5_1_iv_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40095 \wb_adr_5_i_0_o2[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40094 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h35F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40095 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h2255) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_68 ( input D1, C1, A1, D0, C0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40096 \FS_RNIF2MA[9] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40097 \ufmefb/EFBInst_0_RNISI191 ( .A(A0), .B(GNDI), .C(C0), .D(D0),
.Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40096 ( input A, B, C, D, output Z );
ROM16X1A #(16'h5FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40097 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40098 \wb_dati_5_1_iv_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40099 \wb_dati_5_1_iv_0_a3_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
.Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40098 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40099 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40099 \wb_adr_5_i_0_a3_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40100 \FS_RNIJO0F[14] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40100 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_71 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40101 \wb_dati_5_1_iv_i_i_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40102 \wb_dati_5_1_iv_i_i_1_RNO[3] ( .A(A0), .B(GNDI), .C(C0), .D(D0),
.Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40101 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40102 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40103 nRCS_9_u_i_0_o3( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40104 Ready_RNICVV51( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40103 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hEEEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40104 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40105 \wb_dati_5_1_iv_i_i_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40106 \wb_dati_5_1_iv_i_i_0_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0),
.Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40105 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40106 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_74 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40107 un1_nRCAS_6_sqmuxa_i_0_0_o2_0( .A(A1), .B(GNDI), .C(C1), .D(D1),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40108 un1_nRCAS_6_sqmuxa_i_0_0_o2_0_RNIQVER( .A(A0), .B(B0), .C(C0),
.D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40107 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40108 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_75 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40109 \wb_adr_5_i_0_a2_0[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40110 \wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40109 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
module lut40110 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h40CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40111 \wb_dati_5_1_iv_0_o2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40112 \wb_dati_5_1_iv_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40111 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h100B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40112 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40113 \FS_RNIGOCT[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40114 \wb_dati_5_1_iv_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
module lut40113 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40114 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h4050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_78 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40115 nRCS_9_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40116 nRRAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40115 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40116 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h010F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_79 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40117 nRCS_9_u_i_0_o2_1( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40118 nRCS_9_u_i_0_o2_1_RNIL2K71_0( .A(A0), .B(B0), .C(C0), .D(D0),
.Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40117 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40118 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_80 ( input D1, C1, B1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0,
F1, Q1 );
wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40119 un1_CmdEnable20_0_0_a3_1_1( .A(GNDI), .B(B1), .C(C1), .D(D1),
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40120 CmdEnable_s_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CBR_fast( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
vmuxregsre CBR( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN),
.LSR(GNDI), .Q(Q0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
(CLK => Q1) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
module lut40119 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40120 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_81 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40121 RCKEEN_8_u_0_0_a2_2( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40122 nRWE_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40121 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h5000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40122 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_82 ( input D1, C1, B1, A1, C0, B0, M0, CE, CLK, output F0, Q0, F1 );
wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40123 CmdLEDEN_4_u_i_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40046 CmdUFMData_1_sqmuxa_0_a3( .A(GNDI), .B(B0), .C(C0), .D(GNDI),
.Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
vmuxregsre CmdUFMData( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly),
.CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
module lut40123 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_83 ( input D1, B1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40109 nRCAS_r_i_0_a2( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40124 nRCS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40124 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0307) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40125 un1_CmdEnable20_0_0_o3_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40126 un1_CmdEnable20_0_0_o3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module lut40125 ( input A, B, C, D, output Z );
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40126 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40127 \wb_dati_5_1_iv_0_a3_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40128 \wb_dati_5_1_iv_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40127 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40128 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40129 \wb_dati_5_1_iv_0_a3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40130 \wb_dati_5_1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40129 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h8020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40130 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_87 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40131 \wb_dati_5_1_iv_i_i_a2_4[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1),
.Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40132 \wb_dati_5_1_iv_0_a3_3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40131 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40132 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
RC
2023-09-21 09:45:45 +00:00
lut40133 nRCS_9_u_i_0_o2_1_RNIL2K71( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40134 RA10_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40133 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40134 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_89 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40047 \wb_dati_5_1_iv_0_o2_0[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40135 \wb_dati_5_1_iv_0_a3[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40135 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0804) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40136 nRWE_s_i_0_a3_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40137 nRWE_s_i_0_tz_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40136 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40137 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40138 \wb_dati_5_1_iv_i_i_a3_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1),
.Z(F1));
lut40139 \wb_dati_5_1_iv_0_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40138 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40139 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_92 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40140 wb_cyc_stb_2_sqmuxa_i_a3_0( .A(GNDI), .B(B1), .C(C1), .D(D1),
.Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40141 wb_cyc_stb_2_sqmuxa_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40140 ( input A, B, C, D, output Z );
ROM16X1A #(16'hCC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40141 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40142 un1_CmdEnable20_0_0_o3_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40143 un1_CmdEnable20_0_0_o3_10( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40142 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40143 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
lut40144 nRCAS_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40145 nRCAS_r_i_0_o2_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40144 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0133) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40145 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_95 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40146 \wb_dati_5_1_iv_i_i_a2_2[3] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1),
.Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40147 wb_we_0_i_0_a3_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40146 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h5500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40147 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0900) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_96 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut4 \wb_adr_5_i_0_a2_1[0] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40148 \wb_adr_5_i_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40148 ( input A, B, C, D, output Z );
ROM16X1A #(16'hA800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_97 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40149 \FS_RNIH267[16] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40150 \wb_adr_5_i_0_m2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40149 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40150 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hC0E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40151 wb_cyc_stb_4_iv_0_a3_0_2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
.Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40152 wb_cyc_stb_4_iv_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40151 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40152 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_99 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40046 CmdLEDEN_4_u_i_0_a2_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40080 un1_CmdEnable20_0_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module SLICE_100 ( input C1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40153 XOR8MEG_3_u_0_0_o2_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40080 XOR8MEG_3_u_0_0_a3_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40153 ( input A, B, C, D, output Z );
ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_101 ( input D1, C1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40154 \wb_dati_5_1_iv_0_a2[6] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40155 \wb_dati_5_1_iv_0_a3_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
module lut40154 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40155 ( input A, B, C, D, output Z );
ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_102 ( input D1, A1, D0, C0, B0, A0, output F0, F1 );
wire GNDI;
lut40156 \wb_dati_5_0_iv_0_a2[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1),
.Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40157 \wb_dati_5_0_iv_0_a3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
specify
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40156 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40157 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_103 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40158 PHI2r3_RNIFT0I_0( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40159 CmdValid_fast_RNI3K0H1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40158 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40159 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hD555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_104 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40160 \FS_RNIVOOA[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40161 \ufmefb/EFBInst_0_RNISGNB ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40160 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40161 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40162 \wb_adr_5_i_0_a3_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40163 wb_we_0_i_0_0_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40162 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40163 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40164 \wb_adr_5_i_0_a3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40165 \wb_adr_RNO_0[0] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
gnd DRIVEGND( .PWR0(GNDI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40164 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h8C04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40165 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_107 ( input C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0,
F1 );
wire GNDI, VCCI, M0_dly, CLK_dly;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40166 wb_cyc_stb_4_iv_0_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
gnd DRIVEGND( .PWR0(GNDI));
lut40167 CmdValid_RNIS5A51( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
vmuxregsre CASr3( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly),
.LSR(GNDI), .Q(Q0));
vcc DRIVEVCC( .PWR1(VCCI));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(CLK => Q0) = (0:0:0,0:0:0);
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40166 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40167 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h40FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40168 RCKEEN_8_u_0_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40169 nRWE_s_i_0_a2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40168 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h7A0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40169 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_109 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40170 \wb_dati_5_1_iv_i_i_a3_1_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Z(F1));
RC
2023-09-21 09:45:45 +00:00
lut40171 \wb_adr_5_i_0_o2_0[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40170 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h2100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40171 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hA0AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40172 \wb_adr_5_i_0_a3_0_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40173 \wb_dati_5_1_iv_i_i_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40172 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40173 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h4002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_111 ( input D1, A1, D0, A0, output F0, F1 );
wire GNDI;
lut40174 RDQML_0_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40049 RDQMH_pad_RNO( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40174 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h55FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_112 ( input D1, C1, B1, A1, C0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40175 un1_CmdEnable20_0_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40018 XOR8MEG_3_u_0_0_0_a2( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(B1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40175 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_113 ( input D1, C1, C0, B0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40176 \FS_RNI7U6M[14] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40177 \wb_dati_5_1_iv_i_i_a2_3[3] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI),
.Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40176 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40177 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_114 ( input D1, C1, A1, C0, B0, A0, output F0, F1 );
wire GNDI;
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
lut40178 \un9_RA_i_m2_i_m2[6] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40179 un1_CmdEnable20_0_0_o3_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40178 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40179 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_115 ( input D1, C1, A1, D0, C0, B0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40180 \un9_RA_i_m2_i_m2[9] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40181 \un9_RA[8] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(C1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40180 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hAFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40181 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFC0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_116 ( input D1, C1, B1, D0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40182 \un9_RA_i_m2_i_m2[7] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40183 \un9_RA_i_m2_i_m2[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40182 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCFC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40183 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hCCAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_117 ( input D1, C1, A1, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40184 \un9_RA_i_m2_i_m2[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40185 \un9_RA_i_m2_i_m2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40184 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hFA50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40185 ( input A, B, C, D, output Z );
ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_118 ( input D1, C1, A1, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40186 \un9_RA_i_m2_i_m2[4] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40187 \un9_RA_i_m2_i_m2[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
RC
2023-09-21 09:45:45 +00:00
(D1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(A0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40186 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40187 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_119 ( input D1, C1, B1, A1, D0, B0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40188 CmdLEDEN_4_u_i_0_a3_0_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
lut40189 XOR8MEG_3_u_0_0_a2_0( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(A1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40188 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module lut40189 ( input A, B, C, D, output Z );
ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
module SLICE_120 ( input C1, B1, D0, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40046 \RBAd[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40190 RA11d( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(C1 => F1) = (0:0:0,0:0:0);
RC
2023-09-21 09:45:45 +00:00
(B1 => F1) = (0:0:0,0:0:0);
(D0 => F0) = (0:0:0,0:0:0);
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40190 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h84C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_121 ( input B1, A1, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40034 wb_cyc_stb_4_iv_0_a3_0_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
.Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40191 wb_cyc_stb_4_iv_0_a3_0_3( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(B1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40191 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_122 ( input D1, C1, A1, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40192 n8MEGEN_RNO_0( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40193 PHI2r3_RNIFT0I( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(C1 => F1) = (0:0:0,0:0:0);
(A1 => F1) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40192 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h550F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40193 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
endmodule
RC
2023-09-21 09:45:45 +00:00
module SLICE_123 ( input D1, B1, C0, B0, A0, output F0, F1 );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
wire GNDI;
RC
2023-09-21 09:45:45 +00:00
lut40194 \wb_adr_5_i_0_o2[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
gnd DRIVEGND( .PWR0(GNDI));
RC
2023-09-21 09:45:45 +00:00
lut40195 InitReady3_0_a3_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(D1 => F1) = (0:0:0,0:0:0);
(B1 => F1) = (0:0:0,0:0:0);
(C0 => F0) = (0:0:0,0:0:0);
(B0 => F0) = (0:0:0,0:0:0);
(A0 => F0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40194 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h33FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
RC
2023-09-21 09:45:45 +00:00
module lut40195 ( input A, B, C, D, output Z );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module RD_0_ ( output PADDI, input IOLDO, PADDT, inout RD0 );
xo2iobuf \RD_pad[0] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
specify
(IOLDO => RD0) = (0:0:0,0:0:0);
(PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(RD0 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD0, 0:0:0);
$width (negedge RD0, 0:0:0);
endspecify
endmodule
module xo2iobuf ( input I, T, output Z, PAD, input PADI );
IB INST1( .I(PADI), .O(Z));
OBW INST2( .I(I), .T(T), .O(PAD));
endmodule
module RD_0__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \WRD_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module mfflsre ( input D0, SP, CK, LSR, output Q );
FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module Dout_0_ ( input PADDO, output Dout0 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0196 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout0) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module xo2iobuf0196 ( input I, output PAD );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
OB INST5( .I(I), .O(PAD));
endmodule
module PHI2 ( output PADDI, input PHI2 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 PHI2_pad( .Z(PADDI), .PAD(PHI2));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PHI2 => PADDI) = (0:0:0,0:0:0);
$width (posedge PHI2, 0:0:0);
$width (negedge PHI2, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module xo2iobuf0197 ( output Z, input PAD );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
RC
2023-09-21 09:45:45 +00:00
IB INST1( .I(PAD), .O(Z));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
endmodule
module PHI2_MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre PHI2r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module smuxlregsre ( input D0, SP, CK, LSR, output Q );
IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module RDQML ( input PADDO, output RDQML );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 RDQML_pad( .I(PADDO), .PAD(RDQML));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RDQML) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module xo2iobuf0198 ( input I, output PAD );
OB INST5( .I(I), .O(PAD));
endmodule
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
module RDQMH ( input PADDO, output RDQMH );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 RDQMH_pad( .I(PADDO), .PAD(RDQMH));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RDQMH) = (0:0:0,0:0:0);
endspecify
endmodule
module nRCAS ( input IOLDO, output nRCAS );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 nRCAS_pad( .I(IOLDO), .PAD(nRCAS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(IOLDO => nRCAS) = (0:0:0,0:0:0);
endspecify
endmodule
module nRCAS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
mfflsre0199 nRCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module mfflsre0199 ( input D0, SP, CK, LSR, output Q );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module nRRAS ( input IOLDO, output nRRAS );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 nRRAS_pad( .I(IOLDO), .PAD(nRRAS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(IOLDO => nRRAS) = (0:0:0,0:0:0);
endspecify
endmodule
module nRRAS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
mfflsre0199 nRRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module nRWE ( input IOLDO, output nRWE );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 nRWE_pad( .I(IOLDO), .PAD(nRWE));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(IOLDO => nRWE) = (0:0:0,0:0:0);
endspecify
endmodule
module nRWE_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
mfflsre0199 nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module RCKE ( input PADDO, output RCKE );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 RCKE_pad( .I(PADDO), .PAD(RCKE));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RCKE) = (0:0:0,0:0:0);
endspecify
endmodule
module RCLK ( output PADDI, input RCLK );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 RCLK_pad( .Z(PADDI), .PAD(RCLK));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(RCLK => PADDI) = (0:0:0,0:0:0);
$width (posedge RCLK, 0:0:0);
$width (negedge RCLK, 0:0:0);
endspecify
endmodule
module nRCS ( input IOLDO, output nRCS );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 nRCS_pad( .I(IOLDO), .PAD(nRCS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(IOLDO => nRCS) = (0:0:0,0:0:0);
endspecify
endmodule
module nRCS_MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
RC
2023-09-21 09:45:45 +00:00
mfflsre0199 nRCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module RD_7_ ( output PADDI, input IOLDO, PADDT, inout RD7 );
xo2iobuf \RD_pad[7] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
specify
(IOLDO => RD7) = (0:0:0,0:0:0);
(PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(RD7 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD7, 0:0:0);
$width (negedge RD7, 0:0:0);
endspecify
endmodule
module RD_7__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \WRD_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module RD_6_ ( output PADDI, input IOLDO, PADDT, inout RD6 );
xo2iobuf \RD_pad[6] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
specify
(IOLDO => RD6) = (0:0:0,0:0:0);
(PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(RD6 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD6, 0:0:0);
$width (negedge RD6, 0:0:0);
endspecify
endmodule
module RD_6__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \WRD_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module RD_5_ ( output PADDI, input IOLDO, PADDT, inout RD5 );
xo2iobuf \RD_pad[5] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
specify
(IOLDO => RD5) = (0:0:0,0:0:0);
(PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(RD5 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD5, 0:0:0);
$width (negedge RD5, 0:0:0);
endspecify
endmodule
module RD_5__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \WRD_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module RD_4_ ( output PADDI, input IOLDO, PADDT, inout RD4 );
xo2iobuf \RD_pad[4] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
specify
(IOLDO => RD4) = (0:0:0,0:0:0);
(PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(RD4 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD4, 0:0:0);
$width (negedge RD4, 0:0:0);
endspecify
endmodule
module RD_4__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \WRD_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module RD_3_ ( output PADDI, input IOLDO, PADDT, inout RD3 );
xo2iobuf \RD_pad[3] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
specify
(IOLDO => RD3) = (0:0:0,0:0:0);
(PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(RD3 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD3, 0:0:0);
$width (negedge RD3, 0:0:0);
endspecify
endmodule
module RD_3__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \WRD_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module RD_2_ ( output PADDI, input IOLDO, PADDT, inout RD2 );
xo2iobuf \RD_pad[2] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
specify
(IOLDO => RD2) = (0:0:0,0:0:0);
(PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(RD2 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD2, 0:0:0);
$width (negedge RD2, 0:0:0);
endspecify
endmodule
module RD_2__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \WRD_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module RD_1_ ( output PADDI, input IOLDO, PADDT, inout RD1 );
xo2iobuf \RD_pad[1] ( .I(IOLDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
specify
(IOLDO => RD1) = (0:0:0,0:0:0);
(PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
(RD1 => PADDI) = (0:0:0,0:0:0);
$width (posedge RD1, 0:0:0);
$width (negedge RD1, 0:0:0);
endspecify
endmodule
module RD_1__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \WRD_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module RA_11_ ( input IOLDO, output RA11 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[11] ( .I(IOLDO), .PAD(RA11));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(IOLDO => RA11) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_11__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, GNDI, OPOS_dly, CLK_dly;
mfflsre RA11_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module RA_10_ ( input IOLDO, output RA10 );
RC
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xo2iobuf0198 \RA_pad[10] ( .I(IOLDO), .PAD(RA10));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(IOLDO => RA10) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_10__MGIOL ( output IOLDO, input OPOS, LSR, CLK );
wire VCCI, OPOS_dly, CLK_dly, LSR_dly;
RC
2023-09-21 09:45:45 +00:00
mfflsre0200 RA10_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly),
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module mfflsre0200 ( input D0, SP, CK, LSR, output Q );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
defparam INST01.GSR = "DISABLED";
endmodule
module RA_9_ ( input PADDO, output RA9 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[9] ( .I(PADDO), .PAD(RA9));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA9) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_8_ ( input PADDO, output RA8 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[8] ( .I(PADDO), .PAD(RA8));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA8) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_7_ ( input PADDO, output RA7 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[7] ( .I(PADDO), .PAD(RA7));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA7) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_6_ ( input PADDO, output RA6 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[6] ( .I(PADDO), .PAD(RA6));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA6) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_5_ ( input PADDO, output RA5 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[5] ( .I(PADDO), .PAD(RA5));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA5) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_4_ ( input PADDO, output RA4 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[4] ( .I(PADDO), .PAD(RA4));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA4) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_3_ ( input PADDO, output RA3 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[3] ( .I(PADDO), .PAD(RA3));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA3) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_2_ ( input PADDO, output RA2 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[2] ( .I(PADDO), .PAD(RA2));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA2) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_1_ ( input PADDO, output RA1 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[1] ( .I(PADDO), .PAD(RA1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA1) = (0:0:0,0:0:0);
endspecify
endmodule
module RA_0_ ( input PADDO, output RA0 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RA_pad[0] ( .I(PADDO), .PAD(RA0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => RA0) = (0:0:0,0:0:0);
endspecify
endmodule
module RBA_1_ ( input IOLDO, output RBA1 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RBA_pad[1] ( .I(IOLDO), .PAD(RBA1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(IOLDO => RBA1) = (0:0:0,0:0:0);
endspecify
endmodule
module RBA_1__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \RBA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module RBA_0_ ( input IOLDO, output RBA0 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0198 \RBA_pad[0] ( .I(IOLDO), .PAD(RBA0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(IOLDO => RBA0) = (0:0:0,0:0:0);
endspecify
endmodule
module RBA_0__MGIOL ( output IOLDO, input OPOS, CLK );
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
mfflsre \RBA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
.Q(IOLDO));
vcc DRIVEVCC( .PWR1(VCCI));
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IOLDO) = (0:0:0,0:0:0);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
endspecify
endmodule
module LED ( input PADDO, output LED );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0201 LED_pad( .I(PADDO), .PAD(LED));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => LED) = (0:0:0,0:0:0);
endspecify
endmodule
RC
2023-09-21 09:45:45 +00:00
module xo2iobuf0201 ( input I, output PAD );
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
OB INST5( .I(I), .O(PAD));
endmodule
module nFWE ( output PADDI, input nFWE );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 nFWE_pad( .Z(PADDI), .PAD(nFWE));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(nFWE => PADDI) = (0:0:0,0:0:0);
$width (posedge nFWE, 0:0:0);
$width (negedge nFWE, 0:0:0);
endspecify
endmodule
module nCRAS ( output PADDI, input nCRAS );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 nCRAS_pad( .Z(PADDI), .PAD(nCRAS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(nCRAS => PADDI) = (0:0:0,0:0:0);
$width (posedge nCRAS, 0:0:0);
$width (negedge nCRAS, 0:0:0);
endspecify
endmodule
module nCCAS ( output PADDI, input nCCAS );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 nCCAS_pad( .Z(PADDI), .PAD(nCCAS));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(nCCAS => PADDI) = (0:0:0,0:0:0);
$width (posedge nCCAS, 0:0:0);
$width (negedge nCCAS, 0:0:0);
endspecify
endmodule
module Dout_7_ ( input PADDO, output Dout7 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0196 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout7) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_6_ ( input PADDO, output Dout6 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0196 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout6) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_5_ ( input PADDO, output Dout5 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0196 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout5) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_4_ ( input PADDO, output Dout4 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0196 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout4) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_3_ ( input PADDO, output Dout3 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0196 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout3) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_2_ ( input PADDO, output Dout2 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0196 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout2) = (0:0:0,0:0:0);
endspecify
endmodule
module Dout_1_ ( input PADDO, output Dout1 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0196 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(PADDO => Dout1) = (0:0:0,0:0:0);
endspecify
endmodule
module Din_7_ ( output PADDI, input Din7 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(Din7 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din7, 0:0:0);
$width (negedge Din7, 0:0:0);
endspecify
endmodule
module Din_7__MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre \Bank_0io[7] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module Din_6_ ( output PADDI, input Din6 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(Din6 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din6, 0:0:0);
$width (negedge Din6, 0:0:0);
endspecify
endmodule
module Din_6__MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre \Bank_0io[6] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module Din_5_ ( output PADDI, input Din5 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(Din5 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din5, 0:0:0);
$width (negedge Din5, 0:0:0);
endspecify
endmodule
module Din_5__MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre \Bank_0io[5] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module Din_4_ ( output PADDI, input Din4 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(Din4 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din4, 0:0:0);
$width (negedge Din4, 0:0:0);
endspecify
endmodule
module Din_4__MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre \Bank_0io[4] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module Din_3_ ( output PADDI, input Din3 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(Din3 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din3, 0:0:0);
$width (negedge Din3, 0:0:0);
endspecify
endmodule
module Din_3__MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre \Bank_0io[3] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module Din_2_ ( output PADDI, input Din2 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(Din2 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din2, 0:0:0);
$width (negedge Din2, 0:0:0);
endspecify
endmodule
module Din_2__MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre \Bank_0io[2] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module Din_1_ ( output PADDI, input Din1 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(Din1 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din1, 0:0:0);
$width (negedge Din1, 0:0:0);
endspecify
endmodule
module Din_1__MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre \Bank_0io[1] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module Din_0_ ( output PADDI, input Din0 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(Din0 => PADDI) = (0:0:0,0:0:0);
$width (posedge Din0, 0:0:0);
$width (negedge Din0, 0:0:0);
endspecify
endmodule
module Din_0__MGIOL ( input DI, CLK, output IN );
wire VCCI, GNDI, DI_dly, CLK_dly;
smuxlregsre \Bank_0io[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
.Q(IN));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
specify
(CLK => IN) = (0:0:0,0:0:0);
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
$width (posedge CLK, 0:0:0);
$width (negedge CLK, 0:0:0);
endspecify
endmodule
module CROW_1_ ( output PADDI, input CROW1 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \CROW_pad[1] ( .Z(PADDI), .PAD(CROW1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(CROW1 => PADDI) = (0:0:0,0:0:0);
$width (posedge CROW1, 0:0:0);
$width (negedge CROW1, 0:0:0);
endspecify
endmodule
module CROW_0_ ( output PADDI, input CROW0 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \CROW_pad[0] ( .Z(PADDI), .PAD(CROW0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(CROW0 => PADDI) = (0:0:0,0:0:0);
$width (posedge CROW0, 0:0:0);
$width (negedge CROW0, 0:0:0);
endspecify
endmodule
module MAin_9_ ( output PADDI, input MAin9 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[9] ( .Z(PADDI), .PAD(MAin9));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin9 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin9, 0:0:0);
$width (negedge MAin9, 0:0:0);
endspecify
endmodule
module MAin_8_ ( output PADDI, input MAin8 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[8] ( .Z(PADDI), .PAD(MAin8));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin8 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin8, 0:0:0);
$width (negedge MAin8, 0:0:0);
endspecify
endmodule
module MAin_7_ ( output PADDI, input MAin7 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[7] ( .Z(PADDI), .PAD(MAin7));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin7 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin7, 0:0:0);
$width (negedge MAin7, 0:0:0);
endspecify
endmodule
module MAin_6_ ( output PADDI, input MAin6 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[6] ( .Z(PADDI), .PAD(MAin6));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin6 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin6, 0:0:0);
$width (negedge MAin6, 0:0:0);
endspecify
endmodule
module MAin_5_ ( output PADDI, input MAin5 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[5] ( .Z(PADDI), .PAD(MAin5));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin5 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin5, 0:0:0);
$width (negedge MAin5, 0:0:0);
endspecify
endmodule
module MAin_4_ ( output PADDI, input MAin4 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[4] ( .Z(PADDI), .PAD(MAin4));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin4 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin4, 0:0:0);
$width (negedge MAin4, 0:0:0);
endspecify
endmodule
module MAin_3_ ( output PADDI, input MAin3 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[3] ( .Z(PADDI), .PAD(MAin3));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin3 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin3, 0:0:0);
$width (negedge MAin3, 0:0:0);
endspecify
endmodule
module MAin_2_ ( output PADDI, input MAin2 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[2] ( .Z(PADDI), .PAD(MAin2));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin2 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin2, 0:0:0);
$width (negedge MAin2, 0:0:0);
endspecify
endmodule
module MAin_1_ ( output PADDI, input MAin1 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[1] ( .Z(PADDI), .PAD(MAin1));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin1 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin1, 0:0:0);
$width (negedge MAin1, 0:0:0);
endspecify
endmodule
module MAin_0_ ( output PADDI, input MAin0 );
RC
2023-09-21 09:45:45 +00:00
xo2iobuf0197 \MAin_pad[0] ( .Z(PADDI), .PAD(MAin0));
MAX, MachXO, MachXO2 working
2023-08-20 11:10:11 +00:00
specify
(MAin0 => PADDI) = (0:0:0,0:0:0);
$width (posedge MAin0, 0:0:0);
$width (negedge MAin0, 0:0:0);
endspecify
endmodule
module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0,
WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0,
WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output
WBDATO0, WBDATO1, WBACKO );
wire VCCI, GNDI;
EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI),
.WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0),
.WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4),
.WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0),
.WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4),
.WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0),
.WBDATO1(WBDATO1), .WBDATO2(), .WBDATO3(), .WBDATO4(), .WBDATO5(),
.WBDATO6(), .WBDATO7(), .WBACKO(WBACKO), .WBCUFMIRQ(), .UFMSN(VCCI),
.CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), .I2C1SCLO(), .I2C1SCLOEN(),
.I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLI(GNDI), .I2C2SCLO(),
.I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), .I2C2SDAOEN(), .I2C1IRQO(),
.I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), .SPISCKEN(), .SPIMISOI(GNDI),
.SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), .SPIMOSIO(), .SPIMOSIEN(),
.SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), .SPIMCSN3(), .SPIMCSN4(),
.SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), .SPICSNEN(), .SPISCSN(GNDI),
.SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), .TCIC(GNDI), .TCINT(), .TCOC(),
.PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), .PLLWEO(), .PLLADRO0(),
.PLLADRO1(), .PLLADRO2(), .PLLADRO3(), .PLLADRO4(), .PLLDATO0(),
.PLLDATO1(), .PLLDATO2(), .PLLDATO3(), .PLLDATO4(), .PLLDATO5(),
.PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), .PLL0DATI1(GNDI),
.PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), .PLL0DATI5(GNDI),
.PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), .PLL1DATI0(GNDI),
.PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), .PLL1DATI4(GNDI),
.PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), .PLL1ACKI(GNDI));
vcc DRIVEVCC( .PWR1(VCCI));
gnd DRIVEGND( .PWR0(GNDI));
endmodule
module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1,
WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1,
WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0,
WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO,
WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output
I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input
I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO,
I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN,
input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output
SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4,
SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO,
input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO,
PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4,
PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6,
PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4,
PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2,
PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI );
wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf,
WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf,
WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf,
WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf,
WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf,
PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf,
PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf,
PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf,
PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf,
I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf,
SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf,
UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf,
WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf,
PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf,
PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf,
PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf,
PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf,
I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf,
I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf,
I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf,
SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf,
SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf,
SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf,
CFGWAKE_buf, CFGSTDBY_buf;
EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf),
.WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf),
.WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf),
.WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf),
.WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf),
.WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf),
.WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf),
.PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf),
.PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf),
.PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf),
.PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf),
.PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf),
.PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf),
.PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf),
.PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf),
.PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf),
.I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf),
.I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf),
.SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf),
.TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf),
.WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf),
.WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf),
.WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf),
.PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf),
.PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf),
.PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf),
.PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf),
.PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf),
.PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf),
.I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf),
.I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf),
.I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf),
.I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf),
.I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf),
.SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf),
.SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf),
.SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf),
.SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf),
.SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf),
.SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf),
.TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf),
.CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf));
defparam INST10.DEV_DENSITY = "640L";
defparam INST10.EFB_I2C1 = "DISABLED";
defparam INST10.EFB_I2C2 = "DISABLED";
defparam INST10.EFB_SPI = "DISABLED";
defparam INST10.EFB_TC = "DISABLED";
defparam INST10.EFB_TC_PORTMODE = "WB";
defparam INST10.EFB_UFM = "ENABLED";
defparam INST10.EFB_WB_CLK_FREQ = "66.7";
defparam INST10.GSR = "ENABLED";
defparam INST10.I2C1_ADDRESSING = "7BIT";
defparam INST10.I2C1_BUS_PERF = "100kHz";
defparam INST10.I2C1_CLK_DIVIDER = 1;
defparam INST10.I2C1_GEN_CALL = "DISABLED";
defparam INST10.I2C1_SLAVE_ADDR = "0b1000001";
defparam INST10.I2C1_WAKEUP = "DISABLED";
defparam INST10.I2C2_ADDRESSING = "7BIT";
defparam INST10.I2C2_BUS_PERF = "100kHz";
defparam INST10.I2C2_CLK_DIVIDER = 1;
defparam INST10.I2C2_GEN_CALL = "DISABLED";
defparam INST10.I2C2_SLAVE_ADDR = "0b1000010";
defparam INST10.I2C2_WAKEUP = "DISABLED";
defparam INST10.SPI_CLK_DIVIDER = 1;
defparam INST10.SPI_CLK_INV = "DISABLED";
defparam INST10.SPI_INTR_RXOVR = "DISABLED";
defparam INST10.SPI_INTR_RXRDY = "DISABLED";
defparam INST10.SPI_INTR_TXOVR = "DISABLED";
defparam INST10.SPI_INTR_TXRDY = "DISABLED";
defparam INST10.SPI_LSB_FIRST = "DISABLED";
defparam INST10.SPI_MODE = "MASTER";
defparam INST10.SPI_PHASE_ADJ = "DISABLED";
defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED";
defparam INST10.SPI_WAKEUP = "DISABLED";
defparam INST10.TC_CCLK_SEL = 1;
defparam INST10.TC_ICAPTURE = "DISABLED";
defparam INST10.TC_ICR_INT = "OFF";
defparam INST10.TC_MODE = "CTCM";
defparam INST10.TC_OCR_INT = "OFF";
defparam INST10.TC_OCR_SET = 32767;
defparam INST10.TC_OC_MODE = "TOGGLE";
defparam INST10.TC_OVERFLOW = "DISABLED";
defparam INST10.TC_OV_INT = "OFF";
defparam INST10.TC_RESETN = "ENABLED";
defparam INST10.TC_SCLK_SEL = "PCLOCK";
defparam INST10.TC_TOP_SEL = "OFF";
defparam INST10.TC_TOP_SET = 65535;
defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED";
defparam INST10.UFM_INIT_FILE_FORMAT = "HEX";
defparam INST10.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem";
defparam INST10.UFM_INIT_PAGES = 1;
defparam INST10.UFM_INIT_START_PAGE = 190;
EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf),
.WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI),
.WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf),
.WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7),
.WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf),
.WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4),
.WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf),
.WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1),
.WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf),
.WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6),
.WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf),
.WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3),
.WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf),
.WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0),
.WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7),
.PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6),
.PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5),
.PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4),
.PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3),
.PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2),
.PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1),
.PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0),
.PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI),
.PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7),
.PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6),
.PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5),
.PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4),
.PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3),
.PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2),
.PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1),
.PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0),
.PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI),
.PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI),
.I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI),
.I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI),
.I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI),
.I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf),
.SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII),
.SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf),
.TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN),
.TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN),
.UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf),
.WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5),
.WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf),
.WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2),
.WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf),
.WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO),
.WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf),
.PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO),
.PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO),
.PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf),
.PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3),
.PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2),
.PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1),
.PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0),
.PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7),
.PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6),
.PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5),
.PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4),
.PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3),
.PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2),
.PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1),
.PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0),
.PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO),
.I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN),
.I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO),
.I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN),
.I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO),
.I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN),
.I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO),
.I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN),
.I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO),
.I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO),
.I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf),
.SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO),
.SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN),
.SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO),
.SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN),
.SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0),
.SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1),
.SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2),
.SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3),
.SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4),
.SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5),
.SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6),
.SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7),
.SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN),
.SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf),
.TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf),
.WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf),
.CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY),
.CFGSTDBYin(CFGSTDBY_buf));
endmodule
module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin,
output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin,
output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output
WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output
WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output
WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output
WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output
WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output
WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output
WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output
WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output
PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in,
output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input
PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out,
input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output
PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in,
output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input
PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out,
input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output
PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in,
output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input
I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout,
input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout,
input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout,
input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout,
input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input
TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input
WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input
WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input
WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input
WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input
WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input
PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout,
input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out,
input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out,
input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out,
input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out,
input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out,
input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out,
input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out,
input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output
I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin,
output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input
I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout,
input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output
I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin,
output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin,
output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input
SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout,
input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output
SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in,
output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in,
output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in,
output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin,
output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin,
output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin,
output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin );
wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly,
WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly,
WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly,
WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly,
WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly;
BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout));
BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout));
BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout));
BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout));
BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout));
BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out));
BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out));
BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out));
BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out));
BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out));
BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out));
BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out));
BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out));
BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out));
BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out));
BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out));
BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out));
BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out));
BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out));
BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out));
BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out));
BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out));
BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out));
BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out));
BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out));
BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out));
BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out));
BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out));
BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out));
BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout));
BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out));
BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out));
BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out));
BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out));
BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out));
BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out));
BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out));
BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out));
BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout));
BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout));
BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout));
BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout));
BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout));
BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout));
BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout));
BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout));
BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout));
BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout));
BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout));
BUFBA TCIC_buf( .A(TCICin), .Z(TCICout));
BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout));
BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out));
BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out));
BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out));
BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out));
BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out));
BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out));
BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out));
BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out));
BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout));
BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout));
BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout));
BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout));
BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout));
BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout));
BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out));
BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out));
BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out));
BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out));
BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out));
BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out));
BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out));
BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out));
BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out));
BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out));
BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out));
BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out));
BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out));
BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout));
BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout));
BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout));
BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout));
BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout));
BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout));
BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout));
BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout));
BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout));
BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout));
BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout));
BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout));
BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout));
BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout));
BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout));
BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout));
BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out));
BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out));
BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out));
BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out));
BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out));
BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out));
BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out));
BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out));
BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout));
BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout));
BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout));
BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout));
BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout));
BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout));
BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout));
specify
(WBCLKIin => WBDATO0out) = (0:0:0,0:0:0);
(WBCLKIin => WBDATO1out) = (0:0:0,0:0:0);
(WBCLKIin => WBACKOout) = (0:0:0,0:0:0);
$setuphold
(posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly);
$setuphold
(posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly);
$setuphold
(posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly);
$setuphold
(posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly);
$setuphold
(posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly);
$setuphold
(posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly);
$setuphold
(posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly);
$setuphold
(posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly);
$setuphold
(posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly);
$setuphold
(posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly);
$setuphold
(posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly);
$setuphold
(posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly);
$setuphold
(posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly);
$setuphold
(posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly);
$setuphold
(posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly);
$setuphold
(posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly);
$setuphold
(posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly);
$setuphold
(posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly);
$setuphold
(posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly);
$setuphold
(posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly);
$width (posedge WBCLKIin, 0:0:0);
$width (negedge WBCLKIin, 0:0:0);
endspecify
endmodule
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