2021-10-09 01:29:42 +00:00
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Starting process: Module
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Starting process:
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2023-08-17 01:04:05 +00:00
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SCUBA, Version Diamond (64-bit) 3.12.1.454
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Wed Aug 16 20:52:02 2023
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2021-10-09 01:29:42 +00:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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BEGIN SCUBA Module Synthesis
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2023-08-17 01:04:05 +00:00
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Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
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Circuit name : REFB
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2021-10-09 01:29:42 +00:00
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Module type : efb
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Module Version : 1.2
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Ports :
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Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
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Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
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I/O buffer : not inserted
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2023-08-17 01:04:05 +00:00
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EDIF output : REFB.edn
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Verilog output : REFB.v
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Verilog template : REFB_tmpl.v
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2021-10-09 01:29:42 +00:00
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Verilog purpose : for synthesis and simulation
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Bus notation : big endian
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2023-08-17 01:04:05 +00:00
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Report output : REFB.srp
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2021-10-09 01:29:42 +00:00
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Estimated Resource Usage:
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END SCUBA Module Synthesis
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2023-08-17 01:04:05 +00:00
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File: REFB.lpc created.
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2021-10-09 01:29:42 +00:00
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End process: completed successfully.
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Total Warnings: 0
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Total Errors: 0
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