MachXO2 stuff
This commit is contained in:
Zane Kaminski
parent
8cbf2f47ad
commit
8e3c43b7fc
|
|
@ -1,9 +0,0 @@
|
|||
[Runmanager]
|
||||
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
|
||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
|
||||
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
|
||||
|
||||
[impl1%3CStrategy1%3E]
|
||||
isChecked=false
|
||||
isHidden=false
|
||||
isExpanded=false
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
[General]
|
||||
Map.auto_tasks=MapTrace
|
||||
Export.auto_tasks=IBIS, Bitgen, Jedecgen
|
||||
PAR.auto_tasks=PARTrace, IOTiming
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="EFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2021 08 17 05:49:18.220" version="1.2" type="Module" synthesis="lse" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="EFB.lpc" type="lpc" modified="2021 08 17 05:48:29.634"/>
|
||||
<File name="EFB.v" type="top_level_verilog" modified="2021 08 17 05:48:29.674"/>
|
||||
<File name="EFB_tmpl.v" type="template_verilog" modified="2021 08 17 05:48:29.674"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
|
|
@ -1 +0,0 @@
|
|||
EFB.v
|
||||
Binary file not shown.
|
|
@ -1,14 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="RAM2GS_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2GS"/>
|
||||
<Source name="../RAM2GS-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2GS"/>
|
||||
</Source>
|
||||
<Source name="RAM2GS_LCMXO2_640HC.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="RAM2GS_LCMXO2_640HC1.sty"/>
|
||||
</BaliProject>
|
||||
|
|
@ -1,215 +0,0 @@
|
|||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[9]" SITE "62" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RCLK" SITE "63" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
|
||||
IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
|
||||
IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
|
||||
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "LED" LOAD 25.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
|
||||
USE PRIMARY NET "PHI2_c" ;
|
||||
USE PRIMARY NET "RCLK_c" ;
|
||||
VOLTAGE 3.300 V;
|
||||
VCCIO_DERATE BANK 0 PERCENT -5;
|
||||
VCCIO_DERATE PERCENT -5;
|
||||
VCCIO_DERATE BANK 1 PERCENT -5;
|
||||
PERIOD NET "PHI2_c" 350.000000 ns ;
|
||||
PERIOD NET "nCCAS_c" 350.000000 ns ;
|
||||
PERIOD NET "nCRAS_c" 350.000000 ns ;
|
||||
PERIOD NET "RCLK_c" 16.000000 ns ;
|
||||
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
USE PRIMARY NET "nCCAS_c" ;
|
||||
USE PRIMARY NET "nCRAS_c" ;
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn210817003052"></A><B><U><big>pn210817003052</big></U></B>
|
||||
#Start recording tcl command: 8/16/2021 23:26:11
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse"
|
||||
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
|
||||
prj_project save
|
||||
#Stop recording: 8/17/2021 00:30:52
|
||||
|
||||
|
||||
|
||||
<A name="pn210817054927"></A><B><U><big>pn210817054927</big></U></B>
|
||||
#Start recording tcl command: 8/17/2021 00:30:55
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 8/17/2021 05:49:27
|
||||
|
||||
|
||||
|
||||
<A name="pn210817062320"></A><B><U><big>pn210817062320</big></U></B>
|
||||
#Start recording tcl command: 8/17/2021 05:49:30
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Synthesis -impl impl1
|
||||
prj_run Synthesis -impl impl1 -forceOne
|
||||
prj_run Map -impl impl1 -forceOne
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
#Stop recording: 8/17/2021 06:23:20
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
#Start recording tcl command: 8/16/2021 23:26:11
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project new -name "RAM2GS_LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "lse"
|
||||
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
|
||||
prj_project save
|
||||
#Stop recording: 8/17/2021 00:30:52
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
#Start recording tcl command: 8/17/2021 00:30:55
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 8/17/2021 05:49:27
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
#Start recording tcl command: 8/17/2021 05:49:30
|
||||
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Synthesis -impl impl1
|
||||
prj_run Synthesis -impl impl1 -forceOne
|
||||
prj_run Map -impl impl1 -forceOne
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
#Stop recording: 8/17/2021 06:23:20
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
#Start recording tcl command: 10/9/2021 01:18:46
|
||||
#Project Location: C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_run Map -impl impl1 -forceAll
|
||||
prj_run PAR -impl impl1 -forceAll
|
||||
#Stop recording: 10/10/2021 06:41:44
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BuildStatus>
|
||||
<Strategy name="Strategy1">
|
||||
<Milestone name="Export" build_result="0" build_time="0">
|
||||
<Task name="IBIS" build_result="0" update_result="2" update_time="1633756763"/>
|
||||
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Bitgen" build_result="0" update_result="2" update_time="1633756763"/>
|
||||
<Task name="Jedecgen" build_result="0" update_result="2" update_time="1633756763"/>
|
||||
</Milestone>
|
||||
<Milestone name="Map" build_result="2" build_time="1633756755">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1633756755"/>
|
||||
<Task name="MapTrace" build_result="2" update_result="0" update_time="1633756755"/>
|
||||
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="PAR" build_result="2" build_time="1633756763">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1633756763"/>
|
||||
<Task name="PARTrace" build_result="2" update_result="0" update_time="1633756764"/>
|
||||
<Task name="IOTiming" build_result="2" update_result="0" update_time="1633756765"/>
|
||||
</Milestone>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1633756754">
|
||||
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1633756754"/>
|
||||
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1633756753"/>
|
||||
</Milestone>
|
||||
<Milestone name="TOOL_Report" build_result="0" build_time="0">
|
||||
<Task name="HDLE" build_result="2" update_result="0" update_time="1629194861"/>
|
||||
<Task name="BKM" build_result="0" update_result="2" update_time="1629194861"/>
|
||||
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Report name=".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" last_build_time="1633756755" last_build_size="91027"/>
|
||||
<Report name="IBIS/RAM2GS_LCMXO2_640HC_impl1.ibs" last_build_time="0" last_build_size="0"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.bgn" last_build_time="1629195669" last_build_size="4441"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.bit" last_build_time="1629195667" last_build_size="6667"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ior" last_build_time="1633756765" last_build_size="6451"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.jed" last_build_time="1629195669" last_build_size="177066"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.lsedata" last_build_time="1633756753" last_build_size="407682"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ncd" last_build_time="1633756763" last_build_size="302666"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ngd" last_build_time="1633756754" last_build_size="234541"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.tw1" last_build_time="1633756755" last_build_size="113287"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.twr" last_build_time="1633756764" last_build_size="194360"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_map.ncd" last_build_time="1633756755" last_build_size="212106"/>
|
||||
</Strategy>
|
||||
</BuildStatus>
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1 +0,0 @@
|
|||
RAM2GS_rtl.vdb
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,22 +0,0 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.TECH
|
||||
Register bits: 119 of 877 (13.569%)
|
||||
I/O cells: 63
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 10 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 30 100.0
|
||||
FD1P3AY 4 100.0
|
||||
FD1P3IX 3 100.0
|
||||
FD1S3AX 64 100.0
|
||||
FD1S3IX 14 100.0
|
||||
FD1S3JX 4 100.0
|
||||
GSR 1 100.0
|
||||
IB 25 100.0
|
||||
INV 3 100.0
|
||||
LUT4 236 100.0
|
||||
OB 30 100.0
|
||||
PFUMX 16 100.0
|
||||
TOTAL 449
|
||||
|
|
@ -1,86 +0,0 @@
|
|||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 17 06:21:07 2021
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 0 Page.
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 245 MB
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -1,273 +0,0 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Sat Oct 09 01:19:20 2021
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVTTL33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVTTL33_IN | PL6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVTTL33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVTTL33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVTTL33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVTTL33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVTTL33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVTTL33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVTTL33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVTTL33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVTTL33_OUT | PT11D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVTTL33_OUT | PT9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVTTL33_OUT | PT9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVTTL33_OUT | PT9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVTTL33_OUT | PT10B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVTTL33_OUT | PT10A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVTTL33_OUT | PT11A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVTTL33_OUT | PT10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 34/2 | LVTTL33_OUT | PB6C | | | DRIVE:16mA SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVTTL33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVTTL33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVTTL33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVTTL33_IN | PL7B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVTTL33_IN | PL7A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVTTL33_IN | PL6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVTTL33_IN | PL7C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVTTL33_IN | PL6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVTTL33_IN | PL7D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVTTL33_IN | PB6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVTTL33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVTTL33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVTTL33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVTTL33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVTTL33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVTTL33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVTTL33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVTTL33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVTTL33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVTTL33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVTTL33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVTTL33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVTTL33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVTTL33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVTTL33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVTTL33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVTTL33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVTTL33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVTTL33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVTTL33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVTTL33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVTTL33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVTTL33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVTTL33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVTTL33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVTTL33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVTTL33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVTTL33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVTTL33_IN | PL6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVTTL33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVTTL33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVTTL33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVTTL33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVTTL33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVTTL33_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVTTL33_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVTTL33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVTTL33_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVTTL33_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVTTL33_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVTTL33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVTTL33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVTTL33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVTTL33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVTTL33_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVTTL33_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVTTL33_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVTTL33_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVTTL33_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVTTL33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVTTL33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVTTL33_IN | PL7D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVTTL33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVTTL33_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVTTL33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVTTL33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVTTL33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVTTL33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVTTL33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVTTL33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVTTL33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVTTL33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVTTL33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVTTL33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVTTL33_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVTTL33_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVTTL33_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVTTL33_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVTTL33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVTTL33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVTTL33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVTTL33_OUT | PR6A | | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVTTL33_OUT | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVTTL33_IN | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVTTL33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVTTL33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVTTL33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVTTL33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVTTL33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVTTL33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVTTL33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVTTL33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVTTL33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVTTL33_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVTTL33_OUT | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVTTL33_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVTTL33_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVTTL33_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVTTL33_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVTTL33_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVTTL33_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVTTL33_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVTTL33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVTTL33_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVTTL33_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVTTL33_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVTTL33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Oct 09 01:19:22 2021
|
||||
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 4;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 52;
|
||||
; Global primary clock #1
|
||||
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
|
||||
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 13;
|
||||
; Global primary clock #2
|
||||
GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_2_LOADNUM = 7;
|
||||
; Global primary clock #3
|
||||
GLOBAL_PRIMARY_3_SIGNALNAME = nCCAS_c;
|
||||
GLOBAL_PRIMARY_3_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_3_LOADNUM = 4;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 0;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 13;
|
||||
BANK_0_AVAIL = 19;
|
||||
BANK_0_VCCIO = 3.3V;
|
||||
BANK_0_VREF1 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 20;
|
||||
BANK_1_AVAIL = 20;
|
||||
BANK_1_VCCIO = 3.3V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 12;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 3.3V;
|
||||
BANK_2_VREF1 = NA;
|
||||
; I/O Bank 3 Usage
|
||||
BANK_3_USED = 18;
|
||||
BANK_3_AVAIL = 20;
|
||||
BANK_3_VCCIO = 3.3V;
|
||||
BANK_3_VREF1 = NA;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +0,0 @@
|
|||
#BLOCK ASYNCPATHS;
|
||||
#BLOCK RESETPATHS;
|
||||
|
||||
#FREQUENCY 200.000000 MHz;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,402 +0,0 @@
|
|||
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
|
||||
rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX
|
||||
O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/
|
||||
LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.0.240.2
|
||||
Mapped on: 10/09/21 01:19:14
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 119 out of 877 (14%)
|
||||
PFU registers: 119 out of 640 (19%)
|
||||
PIO registers: 0 out of 237 (0%)
|
||||
Number of SLICEs: 131 out of 320 (41%)
|
||||
SLICEs as Logic/ROM: 131 out of 320 (41%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 255 out of 640 (40%)
|
||||
Number used as logic LUTs: 235
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 5
|
||||
Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
|
||||
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
|
||||
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 14
|
||||
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
|
||||
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
|
||||
Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
|
||||
Net InitReady: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
|
||||
Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
|
||||
Net Ready_N_280: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net nRWE_N_210: 1 loads, 1 LSLICEs
|
||||
Net C1Submitted_N_232: 2 loads, 2 LSLICEs
|
||||
Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
|
||||
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
|
||||
Net Ready: 7 loads, 7 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 36 loads
|
||||
Net FS_10: 32 loads
|
||||
Net FS_11: 32 loads
|
||||
Net FS_9: 26 loads
|
||||
Net FS_7: 25 loads
|
||||
Net FS_8: 23 loads
|
||||
Net FS_5: 21 loads
|
||||
Net FS_6: 21 loads
|
||||
Net FS_12: 20 loads
|
||||
Net Ready: 18 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
No errors or warnings present.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVTTL33 | |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVTTL33 | |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVTTL33 | |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block i2 undriven or does not drive anything - clipped.
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal PHI2_N_151 was merged into signal PHI2_c
|
||||
Signal nRWE_N_209 was merged into signal nRWE_N_210
|
||||
Signal RCLK_c_enable_22 was merged into signal InitReady
|
||||
Signal n2557 was merged into signal nRowColSel_N_34
|
||||
Signal n4935 was merged into signal Ready
|
||||
Signal n4933 was merged into signal nRowColSel_N_35
|
||||
Signal GND_net undriven or does not drive anything - clipped.
|
||||
Signal VCC_net undriven or does not drive anything - clipped.
|
||||
Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped.
|
||||
Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped.
|
||||
Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped.
|
||||
Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped.
|
||||
Block i4008 was optimized away.
|
||||
Block nRWE_I_53_1_lut was optimized away.
|
||||
Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
|
||||
Block i1683_1_lut was optimized away.
|
||||
Block i1044_1_lut_rep_86 was optimized away.
|
||||
Block i1684_1_lut_rep_84 was optimized away.
|
||||
Block i1 was optimized away.
|
||||
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
|
||||
Desired WISHBONE clock frequency: 50.0 MHz
|
||||
Clock source: wb_clk
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: NO_WB
|
||||
UFM Connection: DISABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb
|
||||
Type: EFB
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 37 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
-v
|
||||
1
|
||||
|
||||
|
||||
-gt
|
||||
|
||||
|
||||
-mapchkpnt 0
|
||||
-sethld
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -1,5 +0,0 @@
|
|||
-rem
|
||||
-distrce
|
||||
-log "RAM2GS_LCMXO2_640HC_impl1.log"
|
||||
-o "RAM2GS_LCMXO2_640HC_impl1.csv"
|
||||
-pr "RAM2GS_LCMXO2_640HC_impl1.prf"
|
||||
|
|
@ -1,273 +0,0 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Sat Oct 09 01:19:20 2021
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVTTL33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVTTL33_IN | PL6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVTTL33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVTTL33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVTTL33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVTTL33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVTTL33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVTTL33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVTTL33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVTTL33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVTTL33_OUT | PT11D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVTTL33_OUT | PT9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVTTL33_OUT | PT9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVTTL33_OUT | PT9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVTTL33_OUT | PT10B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVTTL33_OUT | PT10A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVTTL33_OUT | PT11A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVTTL33_OUT | PT10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 34/2 | LVTTL33_OUT | PB6C | | | DRIVE:16mA SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVTTL33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVTTL33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVTTL33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVTTL33_IN | PL7B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVTTL33_IN | PL7A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVTTL33_IN | PL6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVTTL33_IN | PL7C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVTTL33_IN | PL6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVTTL33_IN | PL7D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVTTL33_IN | PB6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVTTL33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVTTL33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVTTL33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVTTL33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVTTL33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVTTL33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVTTL33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVTTL33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVTTL33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVTTL33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVTTL33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVTTL33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVTTL33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVTTL33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVTTL33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVTTL33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVTTL33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVTTL33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVTTL33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVTTL33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVTTL33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVTTL33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVTTL33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVTTL33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVTTL33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVTTL33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVTTL33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVTTL33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVTTL33_IN | PL6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVTTL33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVTTL33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVTTL33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVTTL33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVTTL33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVTTL33_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVTTL33_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVTTL33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVTTL33_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVTTL33_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVTTL33_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVTTL33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVTTL33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVTTL33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVTTL33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVTTL33_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVTTL33_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVTTL33_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVTTL33_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVTTL33_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVTTL33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVTTL33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVTTL33_IN | PL7D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVTTL33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVTTL33_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVTTL33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVTTL33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVTTL33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVTTL33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVTTL33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVTTL33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVTTL33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVTTL33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVTTL33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVTTL33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVTTL33_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVTTL33_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVTTL33_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVTTL33_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVTTL33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVTTL33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVTTL33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVTTL33_OUT | PR6A | | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVTTL33_OUT | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVTTL33_IN | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVTTL33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVTTL33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVTTL33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVTTL33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVTTL33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVTTL33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVTTL33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVTTL33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVTTL33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVTTL33_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVTTL33_OUT | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVTTL33_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVTTL33_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVTTL33_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVTTL33_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVTTL33_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVTTL33_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVTTL33_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVTTL33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVTTL33_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVTTL33_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVTTL33_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVTTL33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Oct 09 01:19:22 2021
|
||||
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RCLK" SITE "63" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[9]" SITE "62" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
PERIOD NET "PHI2_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "RCLK_c" ;
|
||||
PERIOD NET "nCCAS_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "PHI2_c" ;
|
||||
PERIOD NET "nCRAS_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "nCRAS_c" ;
|
||||
PERIOD NET "RCLK_c" 16.000000 ns ;
|
||||
USE PRIMARY NET "nCCAS_c" ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "LED" LOAD 25.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
|
||||
VOLTAGE 3.300 V;
|
||||
VCCIO_DERATE BANK 0 PERCENT -5;
|
||||
VCCIO_DERATE PERCENT -5;
|
||||
VCCIO_DERATE BANK 1 PERCENT -5;
|
||||
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
|
||||
COMMERCIAL ;
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
|
||||
|
||||
-g RamCfg:Reset
|
||||
|
||||
-path "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,152 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 17 06:21:07 2021
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC -w -jedec -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 0 Page.
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 245 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>I/O Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.0.240.2
|
||||
// Written on Sat Oct 09 01:19:25 2021
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F -0.195 M 1.729 4
|
||||
CROW[1] nCRAS F -0.218 M 1.801 4
|
||||
Din[0] PHI2 F 6.339 4 1.186 4
|
||||
Din[0] nCCAS F 1.641 4 0.107 M
|
||||
Din[1] PHI2 F 6.084 4 1.570 4
|
||||
Din[1] nCCAS F 0.198 4 1.314 4
|
||||
Din[2] PHI2 F 3.778 4 1.771 4
|
||||
Din[2] nCCAS F 0.075 4 1.431 4
|
||||
Din[3] PHI2 F 4.331 4 1.705 4
|
||||
Din[3] nCCAS F -0.116 M 1.722 4
|
||||
Din[4] PHI2 F 6.176 4 1.711 4
|
||||
Din[4] nCCAS F 1.065 4 0.575 4
|
||||
Din[5] PHI2 F 4.684 4 1.261 4
|
||||
Din[5] nCCAS F -0.081 M 1.625 4
|
||||
Din[6] PHI2 F 5.243 4 0.356 4
|
||||
Din[6] nCCAS F 1.414 4 0.309 4
|
||||
Din[7] PHI2 F 6.602 4 1.175 4
|
||||
Din[7] nCCAS F -0.286 M 2.137 4
|
||||
MAin[0] PHI2 F 5.034 4 0.629 4
|
||||
MAin[0] nCRAS F 1.094 4 0.380 4
|
||||
MAin[1] PHI2 F 6.081 4 1.157 4
|
||||
MAin[1] nCRAS F 0.544 4 0.877 4
|
||||
MAin[2] PHI2 F 9.979 4 -0.319 M
|
||||
MAin[2] nCRAS F -0.050 M 1.401 4
|
||||
MAin[3] PHI2 F 9.162 4 -0.219 M
|
||||
MAin[3] nCRAS F 1.032 4 0.440 4
|
||||
MAin[4] PHI2 F 11.678 4 -0.770 M
|
||||
MAin[4] nCRAS F -0.150 M 1.620 4
|
||||
MAin[5] PHI2 F 8.668 4 -0.081 M
|
||||
MAin[5] nCRAS F -0.050 M 1.401 4
|
||||
MAin[6] PHI2 F 8.516 4 -0.025 M
|
||||
MAin[6] nCRAS F 1.003 4 0.478 4
|
||||
MAin[7] PHI2 F 9.320 4 -0.061 M
|
||||
MAin[7] nCRAS F 1.001 4 0.478 4
|
||||
MAin[8] nCRAS F -0.146 M 1.657 4
|
||||
MAin[9] nCRAS F -0.360 M 2.140 4
|
||||
PHI2 RCLK R 3.079 4 -0.602 M
|
||||
nCCAS RCLK R 3.574 4 -0.705 M
|
||||
nCCAS nCRAS F 3.232 4 -0.351 M
|
||||
nCRAS RCLK R 2.757 4 -0.470 M
|
||||
nFWE PHI2 F 5.913 4 0.723 4
|
||||
nFWE nCRAS F 0.547 4 0.890 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 10.062 4 3.164 M
|
||||
RA[0] RCLK R 10.645 4 3.471 M
|
||||
RA[0] nCRAS F 11.744 4 3.770 M
|
||||
RA[10] RCLK R 9.485 4 3.236 M
|
||||
RA[11] PHI2 R 11.513 4 3.824 M
|
||||
RA[1] RCLK R 10.921 4 3.549 M
|
||||
RA[1] nCRAS F 12.664 4 4.036 M
|
||||
RA[2] RCLK R 10.923 4 3.527 M
|
||||
RA[2] nCRAS F 12.463 4 3.984 M
|
||||
RA[3] RCLK R 11.178 4 3.615 M
|
||||
RA[3] nCRAS F 12.304 4 3.917 M
|
||||
RA[4] RCLK R 11.365 4 3.630 M
|
||||
RA[4] nCRAS F 13.243 4 4.179 M
|
||||
RA[5] RCLK R 11.365 4 3.630 M
|
||||
RA[5] nCRAS F 12.940 4 4.098 M
|
||||
RA[6] RCLK R 11.099 4 3.573 M
|
||||
RA[6] nCRAS F 12.162 4 3.870 M
|
||||
RA[7] RCLK R 10.948 4 3.552 M
|
||||
RA[7] nCRAS F 12.282 4 3.936 M
|
||||
RA[8] RCLK R 11.114 4 3.608 M
|
||||
RA[8] nCRAS F 12.909 4 4.116 M
|
||||
RA[9] RCLK R 11.005 4 3.561 M
|
||||
RA[9] nCRAS F 12.959 4 4.081 M
|
||||
RBA[0] nCRAS F 11.842 4 3.911 M
|
||||
RBA[1] nCRAS F 11.343 4 3.771 M
|
||||
RCKE RCLK R 9.884 4 3.362 M
|
||||
RDQMH RCLK R 10.941 4 3.559 M
|
||||
RDQML RCLK R 10.641 4 3.470 M
|
||||
RD[0] nCCAS F 12.628 4 4.413 M
|
||||
RD[1] nCCAS F 12.231 4 4.302 M
|
||||
RD[2] nCCAS F 12.231 4 4.302 M
|
||||
RD[3] nCCAS F 11.928 4 4.221 M
|
||||
RD[4] nCCAS F 12.427 4 4.361 M
|
||||
RD[5] nCCAS F 12.697 4 4.400 M
|
||||
RD[6] nCCAS F 12.427 4 4.361 M
|
||||
RD[7] nCCAS F 12.427 4 4.361 M
|
||||
nRCAS RCLK R 9.674 4 3.300 M
|
||||
nRCS RCLK R 9.674 4 3.300 M
|
||||
nRRAS RCLK R 9.797 4 3.322 M
|
||||
nRWE RCLK R 9.275 4 3.194 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
-a "MachXO2"
|
||||
-d LCMXO2-640HC
|
||||
-t TQFP100
|
||||
-s 4
|
||||
-frequency 200
|
||||
-optimization_goal Balanced
|
||||
-bram_utilization 100
|
||||
-ramstyle Auto
|
||||
-romstyle auto
|
||||
-dsp_utilization 100
|
||||
-use_dsp 1
|
||||
-use_carry_chain 1
|
||||
-carry_chain_length 0
|
||||
-force_gsr Auto
|
||||
-resource_sharing 1
|
||||
-propagate_constants 1
|
||||
-remove_duplicate_regs 1
|
||||
-mux_style Auto
|
||||
-max_fanout 1000
|
||||
-fsm_encoding_style Auto
|
||||
-twr_paths 3
|
||||
-fix_gated_clocks 1
|
||||
-loop_limit 1950
|
||||
|
||||
|
||||
|
||||
-use_io_insertion 1
|
||||
-resolve_mixed_drivers 0
|
||||
-use_io_reg auto
|
||||
|
||||
|
||||
-lpf 1
|
||||
-p "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
|
||||
-ver "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
|
||||
-top RAM2GS
|
||||
|
||||
|
||||
-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
|
||||
|
||||
-ngd "RAM2GS_LCMXO2_640HC_impl1.ngd"
|
||||
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
[ START MERGED ]
|
||||
n4935 Ready
|
||||
n4933 nRowColSel_N_35
|
||||
n2557 nRowColSel_N_34
|
||||
nRWE_N_209 nRWE_N_210
|
||||
PHI2_N_151 PHI2_c
|
||||
RCLK_c_enable_22 InitReady
|
||||
[ END MERGED ]
|
||||
[ START CLIPPED ]
|
||||
GND_net
|
||||
VCC_net
|
||||
FS_972_add_4_1/S0
|
||||
FS_972_add_4_1/CI
|
||||
FS_972_add_4_19/S1
|
||||
FS_972_add_4_19/CO
|
||||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RCLK" SITE "63" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[9]" SITE "62" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
PERIOD NET "PHI2_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "RCLK_c" ;
|
||||
PERIOD NET "nCCAS_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "PHI2_c" ;
|
||||
PERIOD NET "nCRAS_c" 350.000000 ns ;
|
||||
USE PRIMARY NET "nCRAS_c" ;
|
||||
PERIOD NET "RCLK_c" 16.000000 ns ;
|
||||
USE PRIMARY NET "nCCAS_c" ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
---------------------------------------------------
|
||||
Report for cell RAM2GS
|
||||
Instance path: RAM2GS
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 131.00 100.0
|
||||
LUT4 235.00 100.0
|
||||
IOBUF 63 100.0
|
||||
PFUREG 119 100.0
|
||||
RIPPLE 10 100.0
|
||||
Binary file not shown.
|
|
@ -1,428 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Mrp"></A>
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
|
||||
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
|
||||
rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX
|
||||
O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/
|
||||
LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.0.240.2
|
||||
Mapped on: 10/09/21 01:19:14
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 119 out of 877 (14%)
|
||||
PFU registers: 119 out of 640 (19%)
|
||||
PIO registers: 0 out of 237 (0%)
|
||||
Number of SLICEs: 131 out of 320 (41%)
|
||||
SLICEs as Logic/ROM: 131 out of 320 (41%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 255 out of 640 (40%)
|
||||
Number used as logic LUTs: 235
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 5
|
||||
Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
|
||||
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
|
||||
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 14
|
||||
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
|
||||
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
|
||||
|
||||
Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
|
||||
Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
|
||||
Net InitReady: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
|
||||
Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
|
||||
Net Ready_N_280: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net nRWE_N_210: 1 loads, 1 LSLICEs
|
||||
Net C1Submitted_N_232: 2 loads, 2 LSLICEs
|
||||
Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
|
||||
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
|
||||
Net Ready: 7 loads, 7 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 36 loads
|
||||
Net FS_10: 32 loads
|
||||
Net FS_11: 32 loads
|
||||
Net FS_9: 26 loads
|
||||
Net FS_7: 25 loads
|
||||
Net FS_8: 23 loads
|
||||
Net FS_5: 21 loads
|
||||
Net FS_6: 21 loads
|
||||
Net FS_12: 20 loads
|
||||
Net Ready: 18 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
No errors or warnings present.
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVTTL33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVTTL33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVTTL33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
|
||||
|
||||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block i2 undriven or does not drive anything - clipped.
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal PHI2_N_151 was merged into signal PHI2_c
|
||||
Signal nRWE_N_209 was merged into signal nRWE_N_210
|
||||
Signal RCLK_c_enable_22 was merged into signal InitReady
|
||||
Signal n2557 was merged into signal nRowColSel_N_34
|
||||
Signal n4935 was merged into signal Ready
|
||||
Signal n4933 was merged into signal nRowColSel_N_35
|
||||
Signal GND_net undriven or does not drive anything - clipped.
|
||||
Signal VCC_net undriven or does not drive anything - clipped.
|
||||
Signal FS_972_add_4_1/S0 undriven or does not drive anything - clipped.
|
||||
Signal FS_972_add_4_1/CI undriven or does not drive anything - clipped.
|
||||
Signal FS_972_add_4_19/S1 undriven or does not drive anything - clipped.
|
||||
Signal FS_972_add_4_19/CO undriven or does not drive anything - clipped.
|
||||
Block i4008 was optimized away.
|
||||
Block nRWE_I_53_1_lut was optimized away.
|
||||
Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
|
||||
Block i1683_1_lut was optimized away.
|
||||
Block i1044_1_lut_rep_86 was optimized away.
|
||||
Block i1684_1_lut_rep_84 was optimized away.
|
||||
Block i1 was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 50.0 MHz
|
||||
Clock source: wb_clk
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: NO_WB
|
||||
UFM Connection: DISABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb
|
||||
Type: EFB
|
||||
|
||||
|
||||
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 37 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,338 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>PAD Specification File</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Pad"></A>PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Sat Oct 09 01:19:20 2021
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVTTL33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVTTL33_IN | PL6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVTTL33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVTTL33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVTTL33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVTTL33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVTTL33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVTTL33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVTTL33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVTTL33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVTTL33_OUT | PT11D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVTTL33_OUT | PT9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVTTL33_OUT | PT9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVTTL33_OUT | PT9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVTTL33_OUT | PT10B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVTTL33_OUT | PT10A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVTTL33_OUT | PT11A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVTTL33_OUT | PT10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| LED | 34/2 | LVTTL33_OUT | PB6C | | | DRIVE:16mA SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVTTL33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVTTL33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVTTL33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVTTL33_IN | PL7B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVTTL33_IN | PL7A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVTTL33_IN | PL6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVTTL33_IN | PL7C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVTTL33_IN | PL6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVTTL33_IN | PL7D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVTTL33_IN | PB6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVTTL33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVTTL33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVTTL33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVTTL33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVTTL33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVTTL33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVTTL33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVTTL33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVTTL33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVTTL33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVTTL33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVTTL33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVTTL33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVTTL33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVTTL33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVTTL33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVTTL33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVTTL33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVTTL33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVTTL33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVTTL33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVTTL33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVTTL33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVTTL33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVTTL33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVTTL33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVTTL33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVTTL33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVTTL33_IN | PL6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVTTL33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVTTL33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVTTL33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVTTL33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVTTL33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
|
||||
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVTTL33_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVTTL33_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVTTL33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVTTL33_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVTTL33_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVTTL33_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVTTL33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVTTL33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVTTL33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVTTL33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVTTL33_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVTTL33_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVTTL33_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVTTL33_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVTTL33_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVTTL33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVTTL33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVTTL33_IN | PL7D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVTTL33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVTTL33_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVTTL33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVTTL33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVTTL33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVTTL33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVTTL33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVTTL33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVTTL33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVTTL33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVTTL33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVTTL33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVTTL33_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVTTL33_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVTTL33_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVTTL33_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVTTL33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVTTL33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVTTL33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVTTL33_OUT | PR6A | | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVTTL33_OUT | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVTTL33_IN | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVTTL33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVTTL33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVTTL33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVTTL33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVTTL33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVTTL33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVTTL33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVTTL33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVTTL33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVTTL33_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVTTL33_OUT | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVTTL33_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVTTL33_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVTTL33_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVTTL33_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVTTL33_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVTTL33_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVTTL33_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVTTL33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVTTL33_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVTTL33_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVTTL33_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVTTL33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+--------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Oct 09 01:19:22 2021
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
|
||||
<TR>
|
||||
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2GS_LCMXO2_640HC project summary</B></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2GS_LCMXO2_640HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Lattice LSE</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">I/O Timing Analysis </SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-640HC-4TG100C</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-640HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2GS_LCMXO2_640HC.lpf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2GS_LCMXO2_640HC_impl1.prf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.12.0.240.2</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2021/10/09 01:19:25</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,15 +0,0 @@
|
|||
Results of NGD DRC are available in RAM2GS_drc.log.
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
|
||||
|
||||
Running DRC...
|
||||
|
||||
DRC complete with no errors or warnings
|
||||
|
||||
Design Results:
|
||||
452 blocks expanded
|
||||
completed the first expansion
|
||||
All blocks are expanded and NGD expansion is successful.
|
||||
Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
|
||||
|
|
@ -1,335 +0,0 @@
|
|||
--------------------------------------------------------------------------------
|
||||
Lattice Synthesis Timing Report, Version
|
||||
Sat Oct 09 01:19:14 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Design: RAM2GS
|
||||
Constraint file:
|
||||
Report level: verbose report, limited to 3 items per constraint
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c]
|
||||
130 items scored, 125 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i4 to CmdLEDEN_545 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i4 to CmdLEDEN_545
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[4]
|
||||
LUT4 --- 0.493 C to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP Cmdn8MEGEN_546 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i4 to Cmdn8MEGEN_546
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[4]
|
||||
LUT4 --- 0.493 C to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i5 to CmdLEDEN_545 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i5 to CmdLEDEN_545
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i5 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[5]
|
||||
LUT4 --- 0.493 B to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Warning: 13.106 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
|
||||
1392 items scored, 1147 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.222ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
|
||||
|
||||
Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
15.062ns data_path FS_972__i8 to wb_adr_i4 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
|
||||
|
||||
Path Details: FS_972__i8 to wb_adr_i4
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
|
||||
Route 23 e 1.894 FS[8]
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i28_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[4]
|
||||
--------
|
||||
15.062 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.222ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i6 (to RCLK_c +)
|
||||
|
||||
Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
15.062ns data_path FS_972__i8 to wb_adr_i6 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
|
||||
|
||||
Path Details: FS_972__i8 to wb_adr_i6
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
|
||||
Route 23 e 1.894 FS[8]
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i29_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[6]
|
||||
--------
|
||||
15.062 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.216ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_972__i6 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
|
||||
|
||||
Delay: 15.056ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
15.056ns data_path FS_972__i6 to wb_adr_i4 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.216ns
|
||||
|
||||
Path Details: FS_972__i6 to wb_adr_i4
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_972__i6 (from RCLK_c)
|
||||
Route 21 e 1.888 FS[6]
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i28_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[4]
|
||||
--------
|
||||
15.056 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Warning: 15.222 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
Timing Report Summary
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets PHI2_c] | 5.000 ns| 26.212 ns| 8 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 5.000 ns| 15.222 ns| 10 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Critical Nets | Loads| Errors| % of total
|
||||
--------------------------------------------------------------------------------
|
||||
n14 | 16| 200| 15.72%
|
||||
| | |
|
||||
n12_adj_8 | 2| 198| 15.57%
|
||||
| | |
|
||||
n14_adj_3 | 1| 183| 14.39%
|
||||
| | |
|
||||
n14_adj_7 | 2| 176| 13.84%
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Timing summary:
|
||||
---------------
|
||||
|
||||
Timing errors: 1272 Score: 5951146
|
||||
|
||||
Constraints cover 1577 paths, 335 nets, and 954 connections (77.9% coverage)
|
||||
|
||||
|
||||
Peak memory: 60768256 bytes, TRCE: 3186688 bytes, DLYMAN: 0 bytes
|
||||
CPU_TIME_REPORT: 0 secs
|
||||
|
|
@ -1,400 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice Synthesis Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice Synthesis Timing Report, Version
|
||||
Sat Oct 09 01:19:14 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Design: RAM2GS
|
||||
Constraint file:
|
||||
Report level: verbose report, limited to 3 items per constraint
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c]
|
||||
130 items scored, 125 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i4 to CmdLEDEN_545 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i4 to CmdLEDEN_545
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[4]
|
||||
LUT4 --- 0.493 C to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP Cmdn8MEGEN_546 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i4 to Cmdn8MEGEN_546
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[4]
|
||||
LUT4 --- 0.493 C to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i5 to CmdLEDEN_545 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i5 to CmdLEDEN_545
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i5 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[5]
|
||||
LUT4 --- 0.493 B to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Warning: 13.106 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
|
||||
1392 items scored, 1147 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.222ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
|
||||
|
||||
Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
15.062ns data_path FS_972__i8 to wb_adr_i4 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
|
||||
|
||||
Path Details: FS_972__i8 to wb_adr_i4
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
|
||||
Route 23 e 1.894 FS[8]
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i28_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[4]
|
||||
--------
|
||||
15.062 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.222ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i6 (to RCLK_c +)
|
||||
|
||||
Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
15.062ns data_path FS_972__i8 to wb_adr_i6 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
|
||||
|
||||
Path Details: FS_972__i8 to wb_adr_i6
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
|
||||
Route 23 e 1.894 FS[8]
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i29_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[6]
|
||||
--------
|
||||
15.062 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.216ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_972__i6 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
|
||||
|
||||
Delay: 15.056ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
15.056ns data_path FS_972__i6 to wb_adr_i4 violates
|
||||
5.000ns delay constraint less
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.216ns
|
||||
|
||||
Path Details: FS_972__i6 to wb_adr_i4
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_972__i6 (from RCLK_c)
|
||||
Route 21 e 1.888 FS[6]
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i28_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[4]
|
||||
--------
|
||||
15.056 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Warning: 15.222 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets PHI2_c] | 5.000 ns| 26.212 ns| 8 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 5.000 ns| 15.222 ns| 10 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Critical Nets | Loads| Errors| % of total
|
||||
--------------------------------------------------------------------------------
|
||||
n14 | 16| 200| 15.72%
|
||||
| | |
|
||||
n12_adj_8 | 2| 198| 15.57%
|
||||
| | |
|
||||
n14_adj_3 | 1| 183| 14.39%
|
||||
| | |
|
||||
n14_adj_7 | 2| 176| 13.84%
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 1272 Score: 5951146
|
||||
|
||||
Constraints cover 1577 paths, 335 nets, and 954 connections (77.9% coverage)
|
||||
|
||||
|
||||
Peak memory: 60768256 bytes, TRCE: 3186688 bytes, DLYMAN: 0 bytes
|
||||
CPU_TIME_REPORT: 0 secs
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,982 +0,0 @@
|
|||
|
||||
synthesis -f "RAM2GS_LCMXO2_640HC_impl1_lattice.synproj"
|
||||
synthesis: version Diamond (64-bit) 3.12.0.240.2
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Oct 09 01:19:13 2021
|
||||
|
||||
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
|
||||
|
||||
<postMsg mid="35002000" type="Info" dynamic="0" navigation="0" />
|
||||
Synthesis options:
|
||||
The -a option is MachXO2.
|
||||
The -s option is 4.
|
||||
The -t option is TQFP100.
|
||||
The -d option is LCMXO2-640HC.
|
||||
Using package TQFP100.
|
||||
Using performance grade 4.
|
||||
|
||||
|
||||
##########################################################
|
||||
|
||||
### Lattice Family : MachXO2
|
||||
|
||||
### Device : LCMXO2-640HC
|
||||
|
||||
### Package : TQFP100
|
||||
|
||||
### Speed : 4
|
||||
|
||||
##########################################################
|
||||
|
||||
|
||||
|
||||
<postMsg mid="35001781" type="Info" dynamic="0" navigation="0" />
|
||||
Optimization goal = Balanced
|
||||
Top-level module name = RAM2GS.
|
||||
Target frequency = 200.000000 MHz.
|
||||
Maximum fanout = 1000.
|
||||
Timing path count = 3
|
||||
BRAM utilization = 100.000000 %
|
||||
DSP usage = true
|
||||
DSP utilization = 100.000000 %
|
||||
fsm_encoding_style = auto
|
||||
resolve_mixed_drivers = 0
|
||||
fix_gated_clocks = 1
|
||||
|
||||
Mux style = Auto
|
||||
Use Carry Chain = true
|
||||
carry_chain_length = 0
|
||||
Loop Limit = 1950.
|
||||
Use IO Insertion = TRUE
|
||||
Use IO Reg = AUTO
|
||||
|
||||
Resource Sharing = TRUE
|
||||
Propagate Constants = TRUE
|
||||
Remove Duplicate Registers = TRUE
|
||||
force_gsr = auto
|
||||
ROM style = auto
|
||||
RAM style = auto
|
||||
The -comp option is FALSE.
|
||||
The -syn option is FALSE.
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
|
||||
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
|
||||
-sdc option: SDC file input not used.
|
||||
-lpf option: Output file option is ON.
|
||||
Hardtimer checking is enabled (default). The -dt option is not used.
|
||||
The -r option is OFF. [ Remove LOC Properties is OFF. ]
|
||||
Technology check ok...
|
||||
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Compile design.
|
||||
Compile Design Begin
|
||||
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Top module name (Verilog): RAM2GS
|
||||
<postMsg mid="35901018" type="Info" dynamic="2" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): " arg1="RAM2GS" arg2="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg3="1" />
|
||||
<postMsg mid="35901209" type="Warning" dynamic="3" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): " arg1="32" arg2="2" arg3="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg4="123" />
|
||||
<postMsg mid="35901209" type="Warning" dynamic="3" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): " arg1="32" arg2="18" arg3="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg4="128" />
|
||||
<postMsg mid="35901209" type="Warning" dynamic="3" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): " arg1="32" arg2="4" arg3="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg4="255" />
|
||||
<postMsg mid="35901018" type="Info" dynamic="2" navigation="2" arg0="C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): " arg1="EFB" arg2="C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v" arg3="1800" />
|
||||
<postMsg mid="35931013" type="Warning" dynamic="2" navigation="2" arg0="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): " arg1="PLL0DATI7" arg2="c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v" arg3="348" />
|
||||
Last elaborated design is RAM2GS()
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Top-level module name = RAM2GS.
|
||||
######## Missing driver on net n1128. Patching with GND.
|
||||
######## Missing driver on net n1132. Patching with GND.
|
||||
######## Missing driver on net n1133. Patching with GND.
|
||||
######## Missing driver on net n1134. Patching with GND.
|
||||
######## Missing driver on net n1135. Patching with GND.
|
||||
######## Missing driver on net n1131. Patching with GND.
|
||||
######## Missing driver on net n1130. Patching with GND.
|
||||
######## Missing driver on net n1136. Patching with GND.
|
||||
######## Missing driver on net n1137. Patching with GND.
|
||||
######## Missing driver on net n1138. Patching with GND.
|
||||
######## Missing driver on net n1139. Patching with GND.
|
||||
######## Missing driver on net n1140. Patching with GND.
|
||||
######## Missing driver on net n1141. Patching with GND.
|
||||
######## Missing driver on net n1142. Patching with GND.
|
||||
######## Missing driver on net n1143. Patching with GND.
|
||||
######## Missing driver on net n1144. Patching with GND.
|
||||
######## Missing driver on net n1145. Patching with GND.
|
||||
######## Missing driver on net n1146. Patching with GND.
|
||||
######## Missing driver on net n1147. Patching with GND.
|
||||
######## Missing driver on net n1148. Patching with GND.
|
||||
######## Missing driver on net n1129. Patching with GND.
|
||||
######## Missing driver on net n1149. Patching with GND.
|
||||
######## Missing driver on net n1150. Patching with GND.
|
||||
######## Missing driver on net n1151. Patching with GND.
|
||||
######## Missing driver on net n1152. Patching with GND.
|
||||
######## Missing driver on net n1153. Patching with GND.
|
||||
######## Missing driver on net n1154. Patching with GND.
|
||||
######## Missing driver on net n1155. Patching with GND.
|
||||
######## Missing driver on net n1156. Patching with GND.
|
||||
######## Missing driver on net n1157. Patching with GND.
|
||||
<postMsg mid="35001774" type="Info" dynamic="2" navigation="0" arg0="IS" arg1="one-hot" />
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
0000 -> 0000000000000001
|
||||
|
||||
0001 -> 0000000000000010
|
||||
|
||||
0010 -> 0000000000000100
|
||||
|
||||
0011 -> 0000000000001000
|
||||
|
||||
0100 -> 0000000000010000
|
||||
|
||||
0101 -> 0000000000100000
|
||||
|
||||
0110 -> 0000000001000000
|
||||
|
||||
0111 -> 0000000010000000
|
||||
|
||||
1000 -> 0000000100000000
|
||||
|
||||
1001 -> 0000001000000000
|
||||
|
||||
1010 -> 0000010000000000
|
||||
|
||||
1011 -> 0000100000000000
|
||||
|
||||
1100 -> 0001000000000000
|
||||
|
||||
1101 -> 0010000000000000
|
||||
|
||||
1110 -> 0100000000000000
|
||||
|
||||
1111 -> 1000000000000000
|
||||
|
||||
<postMsg mid="35001774" type="Info" dynamic="2" navigation="0" arg0="S" arg1="one-hot" />
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
00 -> 0001
|
||||
|
||||
01 -> 0010
|
||||
|
||||
10 -> 0100
|
||||
|
||||
11 -> 1000
|
||||
|
||||
|
||||
|
||||
|
||||
GSR will not be inferred because no asynchronous signal was found in the netlist.
|
||||
<postMsg mid="35001779" type="Warning" dynamic="1" navigation="0" arg0="C1Submitted_542" />
|
||||
Applying 200.000000 MHz constraint to all clocks
|
||||
|
||||
<postMsg mid="35001611" type="Warning" dynamic="0" navigation="0" />
|
||||
Results of NGD DRC are available in RAM2GS_drc.log.
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
|
||||
|
||||
Running DRC...
|
||||
|
||||
DRC complete with no errors or warnings
|
||||
|
||||
Design Results:
|
||||
452 blocks expanded
|
||||
completed the first expansion
|
||||
All blocks are expanded and NGD expansion is successful.
|
||||
Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
|
||||
|
||||
################### Begin Area Report (RAM2GS)######################
|
||||
Number of register bits => 119 of 877 (13 % )
|
||||
BB => 8
|
||||
CCU2D => 10
|
||||
EFB => 1
|
||||
FD1P3AX => 30
|
||||
FD1P3AY => 4
|
||||
FD1P3IX => 3
|
||||
FD1S3AX => 64
|
||||
FD1S3IX => 14
|
||||
FD1S3JX => 4
|
||||
GSR => 1
|
||||
IB => 25
|
||||
INV => 3
|
||||
LUT4 => 236
|
||||
OB => 30
|
||||
PFUMX => 16
|
||||
################### End Area Report ##################
|
||||
|
||||
################### Begin BlackBox Report ######################
|
||||
TSALL => 1
|
||||
################### End BlackBox Report ##################
|
||||
|
||||
################### Begin Clock Report ######################
|
||||
Clock Nets
|
||||
Number of Clocks: 5
|
||||
Net : RCLK_c, loads : 79
|
||||
Net : PHI2_c, loads : 11
|
||||
Net : nCRAS_c, loads : 2
|
||||
Net : nCCAS_c, loads : 2
|
||||
Net : wb_clk, loads : 1
|
||||
Clock Enable Nets
|
||||
Number of Clock Enables: 14
|
||||
Top 10 highest fanout Clock Enables:
|
||||
Net : RCLK_c_enable_27, loads : 16
|
||||
Net : RCLK_c_enable_20, loads : 4
|
||||
Net : RCLK_c_enable_25, loads : 2
|
||||
Net : RCLK_c_enable_24, loads : 2
|
||||
Net : RCLK_c_enable_29, loads : 2
|
||||
Net : PHI2_N_151_enable_5, loads : 2
|
||||
Net : PHI2_N_151_enable_3, loads : 2
|
||||
Net : PHI2_N_151_enable_1, loads : 1
|
||||
Net : Ready_N_280, loads : 1
|
||||
Net : PHI2_N_151_enable_6, loads : 1
|
||||
Highest fanout non-clock nets
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net : InitReady, loads : 36
|
||||
Net : FS_11, loads : 32
|
||||
Net : FS_10, loads : 32
|
||||
Net : FS_9, loads : 26
|
||||
Net : FS_7, loads : 25
|
||||
Net : FS_8, loads : 23
|
||||
Net : FS_6, loads : 21
|
||||
Net : FS_5, loads : 21
|
||||
Net : FS_12, loads : 20
|
||||
Net : CmdUFMShift, loads : 16
|
||||
################### End Clock Report ##################
|
||||
|
||||
Timing Report Summary
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets PHI2_c] | 200.000 MHz| 38.150 MHz| 8 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
|
||||
Peak Memory Usage: 58.262 MB
|
||||
|
||||
--------------------------------------------------------------
|
||||
Elapsed CPU time for LSE flow : 0.813 secs
|
||||
--------------------------------------------------------------
|
||||
|
||||
map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf" -lpf "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf" -c 0
|
||||
map: version Diamond (64-bit) 3.12.0.240.2
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd
|
||||
Picdevice="LCMXO2-640HC"
|
||||
|
||||
Pictype="TQFP100"
|
||||
|
||||
Picspeed=4
|
||||
|
||||
Remove unused logic
|
||||
|
||||
Do not produce over sized NCDs.
|
||||
|
||||
Part used: LCMXO2-640HCTQFP100, Performance used: 4.
|
||||
|
||||
Loading device for application baspr from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
|
||||
Running general design DRC...
|
||||
|
||||
Removing unused logic...
|
||||
|
||||
Optimizing...
|
||||
|
||||
|
||||
|
||||
|
||||
Design Summary:
|
||||
Number of registers: 119 out of 877 (14%)
|
||||
PFU registers: 119 out of 640 (19%)
|
||||
PIO registers: 0 out of 237 (0%)
|
||||
Number of SLICEs: 131 out of 320 (41%)
|
||||
SLICEs as Logic/ROM: 131 out of 320 (41%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 255 out of 640 (40%)
|
||||
Number used as logic LUTs: 235
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
|
||||
Number of clocks: 5
|
||||
Net RCLK_c: 52 loads, 52 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk_550 )
|
||||
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
|
||||
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 14
|
||||
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
|
||||
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
|
||||
Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
|
||||
Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
|
||||
Net InitReady: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
|
||||
Net PHI2_N_151_enable_1: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_26: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_3: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_5: 2 loads, 2 LSLICEs
|
||||
Net Ready_N_280: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_6: 1 loads, 1 LSLICEs
|
||||
Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
|
||||
Net PHI2_N_151_enable_7: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net nRWE_N_210: 1 loads, 1 LSLICEs
|
||||
Net C1Submitted_N_232: 2 loads, 2 LSLICEs
|
||||
Net wb_adr_7__N_92: 2 loads, 2 LSLICEs
|
||||
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
|
||||
Net Ready: 7 loads, 7 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 36 loads
|
||||
Net FS_10: 32 loads
|
||||
Net FS_11: 32 loads
|
||||
Net FS_9: 26 loads
|
||||
Net FS_7: 25 loads
|
||||
Net FS_8: 23 loads
|
||||
Net FS_5: 21 loads
|
||||
Net FS_6: 21 loads
|
||||
Net FS_12: 20 loads
|
||||
Net Ready: 18 loads
|
||||
|
||||
|
||||
Number of warnings: 0
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 37 MB
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
|
||||
|
||||
ncd2vdb "RAM2GS_LCMXO2_640HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb"
|
||||
|
||||
Loading device for application ncd2vdb from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
|
||||
trce -f "RAM2GS_LCMXO2_640HC_impl1.mt" -o "RAM2GS_LCMXO2_640HC_impl1.tw1" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
|
||||
trce: version Diamond (64-bit) 3.12.0.240.2
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Sat Oct 09 01:19:15 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derating parameters
|
||||
-------------------
|
||||
Voltage: 3.300 V
|
||||
|
||||
VCCIO Voltage:
|
||||
3.135 V (Bank 0)
|
||||
3.135 V (Bank 1)
|
||||
3.135 V (Bank 2)
|
||||
3.135 V (Bank 3)
|
||||
2.375 V (Bank 4)
|
||||
2.375 V (Bank 5)
|
||||
2.375 V (Bank 6)
|
||||
2.375 V (Bank 7)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Sat Oct 09 01:19:15 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derating parameters
|
||||
-------------------
|
||||
Voltage: 3.300 V
|
||||
|
||||
VCCIO Voltage:
|
||||
3.135 V (Bank 0)
|
||||
3.135 V (Bank 1)
|
||||
3.135 V (Bank 2)
|
||||
3.135 V (Bank 3)
|
||||
2.375 V (Bank 4)
|
||||
2.375 V (Bank 5)
|
||||
2.375 V (Bank 6)
|
||||
2.375 V (Bank 7)
|
||||
|
||||
|
||||
|
||||
Timing summary (Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup and Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 42 MB
|
||||
|
||||
|
||||
mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd"
|
||||
|
||||
---- MParTrce Tool ----
|
||||
Removing old design directory at request of -rem command line option to this program.
|
||||
Running par. Please wait . . .
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
|
||||
Sat Oct 09 01:19:16 2021
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
|
||||
SLICE 131/320 40% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 401
|
||||
Number of Connections: 1131
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 4 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 52)
|
||||
PHI2_c (driver: PHI2, clk load #: 13)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 7)
|
||||
nCCAS_c (driver: nCCAS, clk load #: 4)
|
||||
|
||||
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="PHI2_c" arg1="Primary" arg2="PHI2" arg3="8" arg4="Primary" />
|
||||
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="nCRAS_c" arg1="Primary" arg2="nCRAS" arg3="17" arg4="Primary" />
|
||||
<postMsg mid="61061008" type="Warning" dynamic="5" navigation="0" arg0="nCCAS_c" arg1="Primary" arg2="nCCAS" arg3="9" arg4="Primary" />
|
||||
|
||||
No signal is selected as secondary clock.
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 65362.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 65089
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 1 out of 8 (12%)
|
||||
General PIO: 3 out of 80 (3%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
|
||||
PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
|
||||
|
||||
PRIMARY : 4 out of 8 (50%)
|
||||
SECONDARY: 0 out of 8 (0%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
|
||||
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 4 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1131 unrouted.
|
||||
Starting router resource preassignment
|
||||
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="PHI2_c" />
|
||||
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="nCRAS_c" />
|
||||
<postMsg mid="62061008" type="Warning" dynamic="1" navigation="0" arg0="nCCAS_c" />
|
||||
|
||||
<postMsg mid="66011008" type="Warning" dynamic="1" navigation="0" arg0="
 Signal=wb_clk loads=1 clock_loads=1" />
|
||||
|
||||
Completed router resource preassignment. Real time: 6 secs
|
||||
|
||||
Start NBR router at 01:19:22 10/09/21
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 01:19:22 10/09/21
|
||||
|
||||
Start NBR section for initial routing at 01:19:22 10/09/21
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 01:19:22 10/09/21
|
||||
Level 1, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 1
|
||||
12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 2
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
|
||||
|
||||
Start NBR section for re-routing at 01:19:23 10/09/21
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for post-routing at 01:19:23 10/09/21
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 1.135ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
<postMsg mid="66011008" type="Warning" dynamic="1" navigation="0" arg0="
 Signal=wb_clk loads=1 clock_loads=1" />
|
||||
|
||||
Total CPU time 7 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 1131 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 1.135
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 7 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Exiting par with exit code 0
|
||||
Exiting mpartrce with exit code 0
|
||||
|
||||
trce -f "RAM2GS_LCMXO2_640HC_impl1.pt" -o "RAM2GS_LCMXO2_640HC_impl1.twr" "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
|
||||
trce: version Diamond (64-bit) 3.12.0.240.2
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Sat Oct 09 01:19:23 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
Report level: verbose report, limited to 10 items per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derating parameters
|
||||
-------------------
|
||||
Voltage: 3.300 V
|
||||
|
||||
VCCIO Voltage:
|
||||
3.135 V (Bank 0)
|
||||
3.135 V (Bank 1)
|
||||
3.135 V (Bank 2)
|
||||
3.135 V (Bank 3)
|
||||
2.375 V (Bank 4)
|
||||
2.375 V (Bank 5)
|
||||
2.375 V (Bank 6)
|
||||
2.375 V (Bank 7)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Sat Oct 09 01:19:24 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,m
|
||||
Report level: verbose report, limited to 10 items per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Derating parameters
|
||||
-------------------
|
||||
Voltage: 3.300 V
|
||||
|
||||
VCCIO Voltage:
|
||||
3.135 V (Bank 0)
|
||||
3.135 V (Bank 1)
|
||||
3.135 V (Bank 2)
|
||||
3.135 V (Bank 3)
|
||||
2.375 V (Bank 4)
|
||||
2.375 V (Bank 5)
|
||||
2.375 V (Bank 6)
|
||||
2.375 V (Bank 7)
|
||||
|
||||
|
||||
|
||||
Timing summary (Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup and Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 42 MB
|
||||
|
||||
|
||||
iotiming "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf"
|
||||
I/O Timing Report:
|
||||
: version Diamond (64-bit) 3.12.0.240.2
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Running Performance Grade: 4
|
||||
Computing Setup Time ...
|
||||
Computing Max Clock to Output Delay ...
|
||||
Computing Hold Time ...
|
||||
Computing Min Clock to Output Delay ...
|
||||
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Running Performance Grade: 5
|
||||
Computing Setup Time ...
|
||||
Computing Max Clock to Output Delay ...
|
||||
Computing Hold Time ...
|
||||
Computing Min Clock to Output Delay ...
|
||||
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Running Performance Grade: 6
|
||||
Computing Setup Time ...
|
||||
Computing Max Clock to Output Delay ...
|
||||
Computing Hold Time ...
|
||||
Computing Min Clock to Output Delay ...
|
||||
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Running Performance Grade: M
|
||||
Computing Setup Time ...
|
||||
Computing Max Clock to Output Delay ...
|
||||
Computing Hold Time ...
|
||||
Computing Min Clock to Output Delay ...
|
||||
Done.
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -1,133 +0,0 @@
|
|||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.0.240.2
|
||||
// Written on Sat Oct 09 01:19:25 2021
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F -0.195 M 1.729 4
|
||||
CROW[1] nCRAS F -0.218 M 1.801 4
|
||||
Din[0] PHI2 F 6.339 4 1.186 4
|
||||
Din[0] nCCAS F 1.641 4 0.107 M
|
||||
Din[1] PHI2 F 6.084 4 1.570 4
|
||||
Din[1] nCCAS F 0.198 4 1.314 4
|
||||
Din[2] PHI2 F 3.778 4 1.771 4
|
||||
Din[2] nCCAS F 0.075 4 1.431 4
|
||||
Din[3] PHI2 F 4.331 4 1.705 4
|
||||
Din[3] nCCAS F -0.116 M 1.722 4
|
||||
Din[4] PHI2 F 6.176 4 1.711 4
|
||||
Din[4] nCCAS F 1.065 4 0.575 4
|
||||
Din[5] PHI2 F 4.684 4 1.261 4
|
||||
Din[5] nCCAS F -0.081 M 1.625 4
|
||||
Din[6] PHI2 F 5.243 4 0.356 4
|
||||
Din[6] nCCAS F 1.414 4 0.309 4
|
||||
Din[7] PHI2 F 6.602 4 1.175 4
|
||||
Din[7] nCCAS F -0.286 M 2.137 4
|
||||
MAin[0] PHI2 F 5.034 4 0.629 4
|
||||
MAin[0] nCRAS F 1.094 4 0.380 4
|
||||
MAin[1] PHI2 F 6.081 4 1.157 4
|
||||
MAin[1] nCRAS F 0.544 4 0.877 4
|
||||
MAin[2] PHI2 F 9.979 4 -0.319 M
|
||||
MAin[2] nCRAS F -0.050 M 1.401 4
|
||||
MAin[3] PHI2 F 9.162 4 -0.219 M
|
||||
MAin[3] nCRAS F 1.032 4 0.440 4
|
||||
MAin[4] PHI2 F 11.678 4 -0.770 M
|
||||
MAin[4] nCRAS F -0.150 M 1.620 4
|
||||
MAin[5] PHI2 F 8.668 4 -0.081 M
|
||||
MAin[5] nCRAS F -0.050 M 1.401 4
|
||||
MAin[6] PHI2 F 8.516 4 -0.025 M
|
||||
MAin[6] nCRAS F 1.003 4 0.478 4
|
||||
MAin[7] PHI2 F 9.320 4 -0.061 M
|
||||
MAin[7] nCRAS F 1.001 4 0.478 4
|
||||
MAin[8] nCRAS F -0.146 M 1.657 4
|
||||
MAin[9] nCRAS F -0.360 M 2.140 4
|
||||
PHI2 RCLK R 3.079 4 -0.602 M
|
||||
nCCAS RCLK R 3.574 4 -0.705 M
|
||||
nCCAS nCRAS F 3.232 4 -0.351 M
|
||||
nCRAS RCLK R 2.757 4 -0.470 M
|
||||
nFWE PHI2 F 5.913 4 0.723 4
|
||||
nFWE nCRAS F 0.547 4 0.890 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 10.062 4 3.164 M
|
||||
RA[0] RCLK R 10.645 4 3.471 M
|
||||
RA[0] nCRAS F 11.744 4 3.770 M
|
||||
RA[10] RCLK R 9.485 4 3.236 M
|
||||
RA[11] PHI2 R 11.513 4 3.824 M
|
||||
RA[1] RCLK R 10.921 4 3.549 M
|
||||
RA[1] nCRAS F 12.664 4 4.036 M
|
||||
RA[2] RCLK R 10.923 4 3.527 M
|
||||
RA[2] nCRAS F 12.463 4 3.984 M
|
||||
RA[3] RCLK R 11.178 4 3.615 M
|
||||
RA[3] nCRAS F 12.304 4 3.917 M
|
||||
RA[4] RCLK R 11.365 4 3.630 M
|
||||
RA[4] nCRAS F 13.243 4 4.179 M
|
||||
RA[5] RCLK R 11.365 4 3.630 M
|
||||
RA[5] nCRAS F 12.940 4 4.098 M
|
||||
RA[6] RCLK R 11.099 4 3.573 M
|
||||
RA[6] nCRAS F 12.162 4 3.870 M
|
||||
RA[7] RCLK R 10.948 4 3.552 M
|
||||
RA[7] nCRAS F 12.282 4 3.936 M
|
||||
RA[8] RCLK R 11.114 4 3.608 M
|
||||
RA[8] nCRAS F 12.909 4 4.116 M
|
||||
RA[9] RCLK R 11.005 4 3.561 M
|
||||
RA[9] nCRAS F 12.959 4 4.081 M
|
||||
RBA[0] nCRAS F 11.842 4 3.911 M
|
||||
RBA[1] nCRAS F 11.343 4 3.771 M
|
||||
RCKE RCLK R 9.884 4 3.362 M
|
||||
RDQMH RCLK R 10.941 4 3.559 M
|
||||
RDQML RCLK R 10.641 4 3.470 M
|
||||
RD[0] nCCAS F 12.628 4 4.413 M
|
||||
RD[1] nCCAS F 12.231 4 4.302 M
|
||||
RD[2] nCCAS F 12.231 4 4.302 M
|
||||
RD[3] nCCAS F 11.928 4 4.221 M
|
||||
RD[4] nCCAS F 12.427 4 4.361 M
|
||||
RD[5] nCCAS F 12.697 4 4.400 M
|
||||
RD[6] nCCAS F 12.427 4 4.361 M
|
||||
RD[7] nCCAS F 12.427 4 4.361 M
|
||||
nRCAS RCLK R 9.674 4 3.300 M
|
||||
nRCS RCLK R 9.674 4 3.300 M
|
||||
nRRAS RCLK R 9.797 4 3.322 M
|
||||
nRWE RCLK R 9.275 4 3.194 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
[ActiveSupport TRCE]
|
||||
; Setup Analysis
|
||||
Period_0 = 25.800 ns (350.000 ns);
|
||||
Period_1 = 2.500 ns (350.000 ns);
|
||||
Period_2 = 2.500 ns (350.000 ns);
|
||||
Period_3 = 12.427 ns (16.000 ns);
|
||||
Tco_4 = - (-);
|
||||
Tco_5 = - (-);
|
||||
Tco_6 = - (-);
|
||||
Tco_7 = - (-);
|
||||
Tco_8 = - (-);
|
||||
Tco_9 = - (-);
|
||||
Tco_10 = - (-);
|
||||
Tco_11 = - (-);
|
||||
Tco_12 = - (-);
|
||||
Tco_13 = - (-);
|
||||
Tco_14 = - (-);
|
||||
Tco_15 = - (-);
|
||||
Tco_16 = 9.485 ns (12.500 ns);
|
||||
Tco_17 = 11.005 ns (12.500 ns);
|
||||
Tco_18 = 11.114 ns (12.500 ns);
|
||||
Tco_19 = 10.948 ns (12.500 ns);
|
||||
Tco_20 = 11.099 ns (12.500 ns);
|
||||
Tco_21 = 11.365 ns (12.500 ns);
|
||||
Tco_22 = 11.365 ns (12.500 ns);
|
||||
Tco_23 = 11.178 ns (12.500 ns);
|
||||
Tco_24 = 10.923 ns (12.500 ns);
|
||||
Tco_25 = 10.921 ns (12.500 ns);
|
||||
Tco_26 = 10.645 ns (12.500 ns);
|
||||
Tco_27 = 9.674 ns (12.500 ns);
|
||||
Tco_28 = 9.884 ns (12.500 ns);
|
||||
Tco_29 = 9.275 ns (12.500 ns);
|
||||
Tco_30 = 9.797 ns (12.500 ns);
|
||||
Tco_31 = 9.674 ns (12.500 ns);
|
||||
Tco_32 = 10.941 ns (12.500 ns);
|
||||
Tco_33 = 10.641 ns (12.500 ns);
|
||||
Tco_34 = - (-);
|
||||
Tco_35 = - (-);
|
||||
Tco_36 = - (-);
|
||||
Tco_37 = - (-);
|
||||
Tco_38 = - (-);
|
||||
Tco_39 = - (-);
|
||||
Tco_40 = - (-);
|
||||
Failed = 0 (Total 41);
|
||||
Clock_ports = 4;
|
||||
Clock_nets = 5;
|
||||
; Hold Analysis
|
||||
Period_0 = - (-);
|
||||
Period_1 = - (-);
|
||||
Period_2 = - (-);
|
||||
Period_3 = - (-);
|
||||
Tco_4 = - (-);
|
||||
Tco_5 = - (-);
|
||||
Tco_6 = - (-);
|
||||
Tco_7 = - (-);
|
||||
Tco_8 = - (-);
|
||||
Tco_9 = - (-);
|
||||
Tco_10 = - (-);
|
||||
Tco_11 = - (-);
|
||||
Tco_12 = - (-);
|
||||
Tco_13 = - (-);
|
||||
Tco_14 = - (-);
|
||||
Tco_15 = - (-);
|
||||
Tco_16 = 3.236 ns (0.000 ns);
|
||||
Tco_17 = 3.561 ns (0.000 ns);
|
||||
Tco_18 = 3.608 ns (0.000 ns);
|
||||
Tco_19 = 3.552 ns (0.000 ns);
|
||||
Tco_20 = 3.573 ns (0.000 ns);
|
||||
Tco_21 = 3.630 ns (0.000 ns);
|
||||
Tco_22 = 3.630 ns (0.000 ns);
|
||||
Tco_23 = 3.615 ns (0.000 ns);
|
||||
Tco_24 = 3.527 ns (0.000 ns);
|
||||
Tco_25 = 3.549 ns (0.000 ns);
|
||||
Tco_26 = 3.471 ns (0.000 ns);
|
||||
Tco_27 = 3.300 ns (0.000 ns);
|
||||
Tco_28 = 3.362 ns (0.000 ns);
|
||||
Tco_29 = 3.194 ns (0.000 ns);
|
||||
Tco_30 = 3.322 ns (0.000 ns);
|
||||
Tco_31 = 3.300 ns (0.000 ns);
|
||||
Tco_32 = 3.559 ns (0.000 ns);
|
||||
Tco_33 = 3.470 ns (0.000 ns);
|
||||
Tco_34 = - (-);
|
||||
Tco_35 = - (-);
|
||||
Tco_36 = - (-);
|
||||
Tco_37 = - (-);
|
||||
Tco_38 = - (-);
|
||||
Tco_39 = - (-);
|
||||
Tco_40 = - (-);
|
||||
Failed = 0 (Total 41);
|
||||
Clock_ports = 4;
|
||||
Clock_nets = 5;
|
||||
|
|
@ -1,271 +0,0 @@
|
|||
synthesis: version Diamond (64-bit) 3.12.0.240.2
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Oct 09 01:19:13 2021
|
||||
|
||||
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
|
||||
|
||||
Synthesis options:
|
||||
The -a option is MachXO2.
|
||||
The -s option is 4.
|
||||
The -t option is TQFP100.
|
||||
The -d option is LCMXO2-640HC.
|
||||
Using package TQFP100.
|
||||
Using performance grade 4.
|
||||
|
||||
|
||||
##########################################################
|
||||
|
||||
### Lattice Family : MachXO2
|
||||
|
||||
### Device : LCMXO2-640HC
|
||||
|
||||
### Package : TQFP100
|
||||
|
||||
### Speed : 4
|
||||
|
||||
##########################################################
|
||||
|
||||
|
||||
|
||||
INFO - synthesis: User-Selected Strategy Settings
|
||||
Optimization goal = Balanced
|
||||
Top-level module name = RAM2GS.
|
||||
Target frequency = 200.000000 MHz.
|
||||
Maximum fanout = 1000.
|
||||
Timing path count = 3
|
||||
BRAM utilization = 100.000000 %
|
||||
DSP usage = true
|
||||
DSP utilization = 100.000000 %
|
||||
fsm_encoding_style = auto
|
||||
resolve_mixed_drivers = 0
|
||||
fix_gated_clocks = 1
|
||||
|
||||
Mux style = Auto
|
||||
Use Carry Chain = true
|
||||
carry_chain_length = 0
|
||||
Loop Limit = 1950.
|
||||
Use IO Insertion = TRUE
|
||||
Use IO Reg = AUTO
|
||||
|
||||
Resource Sharing = TRUE
|
||||
Propagate Constants = TRUE
|
||||
Remove Duplicate Registers = TRUE
|
||||
force_gsr = auto
|
||||
ROM style = auto
|
||||
RAM style = auto
|
||||
The -comp option is FALSE.
|
||||
The -syn option is FALSE.
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
|
||||
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
|
||||
-sdc option: SDC file input not used.
|
||||
-lpf option: Output file option is ON.
|
||||
Hardtimer checking is enabled (default). The -dt option is not used.
|
||||
The -r option is OFF. [ Remove LOC Properties is OFF. ]
|
||||
Technology check ok...
|
||||
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Compile design.
|
||||
Compile Design Begin
|
||||
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Top module name (Verilog): RAM2GS
|
||||
INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
|
||||
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Top-level module name = RAM2GS.
|
||||
######## Missing driver on net n1128. Patching with GND.
|
||||
######## Missing driver on net n1132. Patching with GND.
|
||||
######## Missing driver on net n1133. Patching with GND.
|
||||
######## Missing driver on net n1134. Patching with GND.
|
||||
######## Missing driver on net n1135. Patching with GND.
|
||||
######## Missing driver on net n1131. Patching with GND.
|
||||
######## Missing driver on net n1130. Patching with GND.
|
||||
######## Missing driver on net n1136. Patching with GND.
|
||||
######## Missing driver on net n1137. Patching with GND.
|
||||
######## Missing driver on net n1138. Patching with GND.
|
||||
######## Missing driver on net n1139. Patching with GND.
|
||||
######## Missing driver on net n1140. Patching with GND.
|
||||
######## Missing driver on net n1141. Patching with GND.
|
||||
######## Missing driver on net n1142. Patching with GND.
|
||||
######## Missing driver on net n1143. Patching with GND.
|
||||
######## Missing driver on net n1144. Patching with GND.
|
||||
######## Missing driver on net n1145. Patching with GND.
|
||||
######## Missing driver on net n1146. Patching with GND.
|
||||
######## Missing driver on net n1147. Patching with GND.
|
||||
######## Missing driver on net n1148. Patching with GND.
|
||||
######## Missing driver on net n1129. Patching with GND.
|
||||
######## Missing driver on net n1149. Patching with GND.
|
||||
######## Missing driver on net n1150. Patching with GND.
|
||||
######## Missing driver on net n1151. Patching with GND.
|
||||
######## Missing driver on net n1152. Patching with GND.
|
||||
######## Missing driver on net n1153. Patching with GND.
|
||||
######## Missing driver on net n1154. Patching with GND.
|
||||
######## Missing driver on net n1155. Patching with GND.
|
||||
######## Missing driver on net n1156. Patching with GND.
|
||||
######## Missing driver on net n1157. Patching with GND.
|
||||
INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
0000 -> 0000000000000001
|
||||
|
||||
0001 -> 0000000000000010
|
||||
|
||||
0010 -> 0000000000000100
|
||||
|
||||
0011 -> 0000000000001000
|
||||
|
||||
0100 -> 0000000000010000
|
||||
|
||||
0101 -> 0000000000100000
|
||||
|
||||
0110 -> 0000000001000000
|
||||
|
||||
0111 -> 0000000010000000
|
||||
|
||||
1000 -> 0000000100000000
|
||||
|
||||
1001 -> 0000001000000000
|
||||
|
||||
1010 -> 0000010000000000
|
||||
|
||||
1011 -> 0000100000000000
|
||||
|
||||
1100 -> 0001000000000000
|
||||
|
||||
1101 -> 0010000000000000
|
||||
|
||||
1110 -> 0100000000000000
|
||||
|
||||
1111 -> 1000000000000000
|
||||
|
||||
INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
00 -> 0001
|
||||
|
||||
01 -> 0010
|
||||
|
||||
10 -> 0100
|
||||
|
||||
11 -> 1000
|
||||
|
||||
|
||||
|
||||
|
||||
GSR will not be inferred because no asynchronous signal was found in the netlist.
|
||||
WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored.
|
||||
Applying 200.000000 MHz constraint to all clocks
|
||||
|
||||
WARNING - synthesis: No user .sdc file.
|
||||
Results of NGD DRC are available in RAM2GS_drc.log.
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
All blocks are expanded and NGD expansion is successful.
|
||||
Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
|
||||
|
||||
################### Begin Area Report (RAM2GS)######################
|
||||
Number of register bits => 119 of 877 (13 % )
|
||||
BB => 8
|
||||
CCU2D => 10
|
||||
EFB => 1
|
||||
FD1P3AX => 30
|
||||
FD1P3AY => 4
|
||||
FD1P3IX => 3
|
||||
FD1S3AX => 64
|
||||
FD1S3IX => 14
|
||||
FD1S3JX => 4
|
||||
GSR => 1
|
||||
IB => 25
|
||||
INV => 3
|
||||
LUT4 => 236
|
||||
OB => 30
|
||||
PFUMX => 16
|
||||
################### End Area Report ##################
|
||||
|
||||
################### Begin BlackBox Report ######################
|
||||
TSALL => 1
|
||||
################### End BlackBox Report ##################
|
||||
|
||||
################### Begin Clock Report ######################
|
||||
Clock Nets
|
||||
Number of Clocks: 5
|
||||
Net : RCLK_c, loads : 79
|
||||
Net : PHI2_c, loads : 11
|
||||
Net : nCRAS_c, loads : 2
|
||||
Net : nCCAS_c, loads : 2
|
||||
Net : wb_clk, loads : 1
|
||||
Clock Enable Nets
|
||||
Number of Clock Enables: 14
|
||||
Top 10 highest fanout Clock Enables:
|
||||
Net : RCLK_c_enable_27, loads : 16
|
||||
Net : RCLK_c_enable_20, loads : 4
|
||||
Net : RCLK_c_enable_25, loads : 2
|
||||
Net : RCLK_c_enable_24, loads : 2
|
||||
Net : RCLK_c_enable_29, loads : 2
|
||||
Net : PHI2_N_151_enable_5, loads : 2
|
||||
Net : PHI2_N_151_enable_3, loads : 2
|
||||
Net : PHI2_N_151_enable_1, loads : 1
|
||||
Net : Ready_N_280, loads : 1
|
||||
Net : PHI2_N_151_enable_6, loads : 1
|
||||
Highest fanout non-clock nets
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net : InitReady, loads : 36
|
||||
Net : FS_11, loads : 32
|
||||
Net : FS_10, loads : 32
|
||||
Net : FS_9, loads : 26
|
||||
Net : FS_7, loads : 25
|
||||
Net : FS_8, loads : 23
|
||||
Net : FS_6, loads : 21
|
||||
Net : FS_5, loads : 21
|
||||
Net : FS_12, loads : 20
|
||||
Net : CmdUFMShift, loads : 16
|
||||
################### End Clock Report ##################
|
||||
|
||||
Timing Report Summary
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets PHI2_c] | 200.000 MHz| 38.150 MHz| 8 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
|
||||
Peak Memory Usage: 58.262 MB
|
||||
|
||||
--------------------------------------------------------------
|
||||
Elapsed CPU time for LSE flow : 0.813 secs
|
||||
--------------------------------------------------------------
|
||||
|
|
@ -1,336 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Synthesis and Ngdbuild Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild Report</big></U></B>
|
||||
synthesis: version Diamond (64-bit) 3.12.0.240.2
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Oct 09 01:19:13 2021
|
||||
|
||||
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
|
||||
|
||||
Synthesis options:
|
||||
The -a option is MachXO2.
|
||||
The -s option is 4.
|
||||
The -t option is TQFP100.
|
||||
The -d option is LCMXO2-640HC.
|
||||
Using package TQFP100.
|
||||
Using performance grade 4.
|
||||
|
||||
|
||||
##########################################################
|
||||
|
||||
### Lattice Family : MachXO2
|
||||
|
||||
### Device : LCMXO2-640HC
|
||||
|
||||
### Package : TQFP100
|
||||
|
||||
### Speed : 4
|
||||
|
||||
##########################################################
|
||||
|
||||
|
||||
|
||||
INFO - synthesis: User-Selected Strategy Settings
|
||||
Optimization goal = Balanced
|
||||
Top-level module name = RAM2GS.
|
||||
Target frequency = 200.000000 MHz.
|
||||
Maximum fanout = 1000.
|
||||
Timing path count = 3
|
||||
BRAM utilization = 100.000000 %
|
||||
DSP usage = true
|
||||
DSP utilization = 100.000000 %
|
||||
fsm_encoding_style = auto
|
||||
resolve_mixed_drivers = 0
|
||||
fix_gated_clocks = 1
|
||||
|
||||
Mux style = Auto
|
||||
Use Carry Chain = true
|
||||
carry_chain_length = 0
|
||||
Loop Limit = 1950.
|
||||
Use IO Insertion = TRUE
|
||||
Use IO Reg = AUTO
|
||||
|
||||
Resource Sharing = TRUE
|
||||
Propagate Constants = TRUE
|
||||
Remove Duplicate Registers = TRUE
|
||||
force_gsr = auto
|
||||
ROM style = auto
|
||||
RAM style = auto
|
||||
The -comp option is FALSE.
|
||||
The -syn option is FALSE.
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
|
||||
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
|
||||
-sdc option: SDC file input not used.
|
||||
-lpf option: Output file option is ON.
|
||||
Hardtimer checking is enabled (default). The -dt option is not used.
|
||||
The -r option is OFF. [ Remove LOC Properties is OFF. ]
|
||||
Technology check ok...
|
||||
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Compile design.
|
||||
Compile Design Begin
|
||||
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Top module name (Verilog): RAM2GS
|
||||
INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
|
||||
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Top-level module name = RAM2GS.
|
||||
######## Missing driver on net n1128. Patching with GND.
|
||||
######## Missing driver on net n1132. Patching with GND.
|
||||
######## Missing driver on net n1133. Patching with GND.
|
||||
######## Missing driver on net n1134. Patching with GND.
|
||||
######## Missing driver on net n1135. Patching with GND.
|
||||
######## Missing driver on net n1131. Patching with GND.
|
||||
######## Missing driver on net n1130. Patching with GND.
|
||||
######## Missing driver on net n1136. Patching with GND.
|
||||
######## Missing driver on net n1137. Patching with GND.
|
||||
######## Missing driver on net n1138. Patching with GND.
|
||||
######## Missing driver on net n1139. Patching with GND.
|
||||
######## Missing driver on net n1140. Patching with GND.
|
||||
######## Missing driver on net n1141. Patching with GND.
|
||||
######## Missing driver on net n1142. Patching with GND.
|
||||
######## Missing driver on net n1143. Patching with GND.
|
||||
######## Missing driver on net n1144. Patching with GND.
|
||||
######## Missing driver on net n1145. Patching with GND.
|
||||
######## Missing driver on net n1146. Patching with GND.
|
||||
######## Missing driver on net n1147. Patching with GND.
|
||||
######## Missing driver on net n1148. Patching with GND.
|
||||
######## Missing driver on net n1129. Patching with GND.
|
||||
######## Missing driver on net n1149. Patching with GND.
|
||||
######## Missing driver on net n1150. Patching with GND.
|
||||
######## Missing driver on net n1151. Patching with GND.
|
||||
######## Missing driver on net n1152. Patching with GND.
|
||||
######## Missing driver on net n1153. Patching with GND.
|
||||
######## Missing driver on net n1154. Patching with GND.
|
||||
######## Missing driver on net n1155. Patching with GND.
|
||||
######## Missing driver on net n1156. Patching with GND.
|
||||
######## Missing driver on net n1157. Patching with GND.
|
||||
INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
0000 -> 0000000000000001
|
||||
|
||||
0001 -> 0000000000000010
|
||||
|
||||
0010 -> 0000000000000100
|
||||
|
||||
0011 -> 0000000000001000
|
||||
|
||||
0100 -> 0000000000010000
|
||||
|
||||
0101 -> 0000000000100000
|
||||
|
||||
0110 -> 0000000001000000
|
||||
|
||||
0111 -> 0000000010000000
|
||||
|
||||
1000 -> 0000000100000000
|
||||
|
||||
1001 -> 0000001000000000
|
||||
|
||||
1010 -> 0000010000000000
|
||||
|
||||
1011 -> 0000100000000000
|
||||
|
||||
1100 -> 0001000000000000
|
||||
|
||||
1101 -> 0010000000000000
|
||||
|
||||
1110 -> 0100000000000000
|
||||
|
||||
1111 -> 1000000000000000
|
||||
|
||||
INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
|
||||
original encoding -> new encoding (one-hot encoding)
|
||||
|
||||
00 -> 0001
|
||||
|
||||
01 -> 0010
|
||||
|
||||
10 -> 0100
|
||||
|
||||
11 -> 1000
|
||||
|
||||
|
||||
|
||||
|
||||
GSR will not be inferred because no asynchronous signal was found in the netlist.
|
||||
WARNING - synthesis: Initial value found on instance C1Submitted_542 will be ignored.
|
||||
Applying 200.000000 MHz constraint to all clocks
|
||||
|
||||
WARNING - synthesis: No user .sdc file.
|
||||
Results of NGD DRC are available in RAM2GS_drc.log.
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
All blocks are expanded and NGD expansion is successful.
|
||||
Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
|
||||
|
||||
################### Begin Area Report (RAM2GS)######################
|
||||
Number of register bits => 119 of 877 (13 % )
|
||||
BB => 8
|
||||
CCU2D => 10
|
||||
EFB => 1
|
||||
FD1P3AX => 30
|
||||
FD1P3AY => 4
|
||||
FD1P3IX => 3
|
||||
FD1S3AX => 64
|
||||
FD1S3IX => 14
|
||||
FD1S3JX => 4
|
||||
GSR => 1
|
||||
IB => 25
|
||||
INV => 3
|
||||
LUT4 => 236
|
||||
OB => 30
|
||||
PFUMX => 16
|
||||
################### End Area Report ##################
|
||||
|
||||
################### Begin BlackBox Report ######################
|
||||
TSALL => 1
|
||||
################### End BlackBox Report ##################
|
||||
|
||||
################### Begin Clock Report ######################
|
||||
Clock Nets
|
||||
Number of Clocks: 5
|
||||
Net : RCLK_c, loads : 79
|
||||
Net : PHI2_c, loads : 11
|
||||
Net : nCRAS_c, loads : 2
|
||||
Net : nCCAS_c, loads : 2
|
||||
Net : wb_clk, loads : 1
|
||||
Clock Enable Nets
|
||||
Number of Clock Enables: 14
|
||||
Top 10 highest fanout Clock Enables:
|
||||
Net : RCLK_c_enable_27, loads : 16
|
||||
Net : RCLK_c_enable_20, loads : 4
|
||||
Net : RCLK_c_enable_25, loads : 2
|
||||
Net : RCLK_c_enable_24, loads : 2
|
||||
Net : RCLK_c_enable_29, loads : 2
|
||||
Net : PHI2_N_151_enable_5, loads : 2
|
||||
Net : PHI2_N_151_enable_3, loads : 2
|
||||
Net : PHI2_N_151_enable_1, loads : 1
|
||||
Net : Ready_N_280, loads : 1
|
||||
Net : PHI2_N_151_enable_6, loads : 1
|
||||
Highest fanout non-clock nets
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net : InitReady, loads : 36
|
||||
Net : FS_11, loads : 32
|
||||
Net : FS_10, loads : 32
|
||||
Net : FS_9, loads : 26
|
||||
Net : FS_7, loads : 25
|
||||
Net : FS_8, loads : 23
|
||||
Net : FS_6, loads : 21
|
||||
Net : FS_5, loads : 21
|
||||
Net : FS_12, loads : 20
|
||||
Net : CmdUFMShift, loads : 16
|
||||
################### End Clock Report ##################
|
||||
|
||||
<A name="lse_trs"></A><B><U><big>Timing Report Summary</big></U></B>
|
||||
--------------
|
||||
--------------------------------------------------------------------------------
|
||||
Constraint | Constraint| Actual|Levels
|
||||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets PHI2_c] | 200.000 MHz| 38.150 MHz| 8 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
2 constraints not met.
|
||||
|
||||
|
||||
Peak Memory Usage: 58.262 MB
|
||||
|
||||
--------------------------------------------------------------
|
||||
Elapsed CPU time for LSE flow : 0.813 secs
|
||||
--------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,350 +0,0 @@
|
|||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
|
|
@ -1,350 +0,0 @@
|
|||
LSE_CPS_ID_1 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:15[8:13]"
|
||||
LSE_CPS_ID_2 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_3 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_4 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_5 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_6 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_7 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_8 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_9 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_10 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_11 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_12 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_13 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_14 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
|
||||
LSE_CPS_ID_15 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_16 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_17 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_18 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_19 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_20 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_21 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_22 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_23 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_24 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:133[9] 136[5]"
|
||||
LSE_CPS_ID_25 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_26 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_27 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_28 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_29 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_30 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_31 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_32 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_33 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_34 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_35 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_36 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_37 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_38 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_39 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_40 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_41 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_42 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_43 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_44 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_45 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_46 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_47 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_48 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_49 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_50 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_51 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_52 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_53 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_54 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_55 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_56 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_57 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_58 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_59 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_60 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_61 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_62 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_63 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_64 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_65 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_66 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_67 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:40[8:12]"
|
||||
LSE_CPS_ID_68 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:35[8:12]"
|
||||
LSE_CPS_ID_69 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:15[15:20]"
|
||||
LSE_CPS_ID_70 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:15[8:13]"
|
||||
LSE_CPS_ID_71 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:25[14:17]"
|
||||
LSE_CPS_ID_72 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:25[14:17]"
|
||||
LSE_CPS_ID_73 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:25[14:17]"
|
||||
LSE_CPS_ID_74 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:25[14:17]"
|
||||
LSE_CPS_ID_75 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:25[14:17]"
|
||||
LSE_CPS_ID_76 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:25[14:17]"
|
||||
LSE_CPS_ID_77 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:25[14:17]"
|
||||
LSE_CPS_ID_78 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:25[14:17]"
|
||||
LSE_CPS_ID_79 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:33[14:18]"
|
||||
LSE_CPS_ID_80 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:33[14:18]"
|
||||
LSE_CPS_ID_81 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_82 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_83 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_84 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_85 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_86 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_87 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_88 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_89 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_90 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:34[14:18]"
|
||||
LSE_CPS_ID_91 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:7[8:12]"
|
||||
LSE_CPS_ID_92 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:55[9:14]"
|
||||
LSE_CPS_ID_93 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:55[16:21]"
|
||||
LSE_CPS_ID_94 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:45[34:39]"
|
||||
LSE_CPS_ID_95 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:45[23:28]"
|
||||
LSE_CPS_ID_96 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:45[45:49]"
|
||||
LSE_CPS_ID_97 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:44[13:17]"
|
||||
LSE_CPS_ID_98 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:45[13:17]"
|
||||
LSE_CPS_ID_99 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_100 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_101 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_102 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_103 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_104 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_105 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_106 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_107 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_108 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_109 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_110 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:51[16:18]"
|
||||
LSE_CPS_ID_111 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:46[19:22]"
|
||||
LSE_CPS_ID_112 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:46[19:22]"
|
||||
LSE_CPS_ID_113 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:11[9:12]"
|
||||
LSE_CPS_ID_114 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:26[15:19]"
|
||||
LSE_CPS_ID_115 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:26[15:19]"
|
||||
LSE_CPS_ID_116 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:26[15:19]"
|
||||
LSE_CPS_ID_117 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:26[15:19]"
|
||||
LSE_CPS_ID_118 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:26[15:19]"
|
||||
LSE_CPS_ID_119 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:26[15:19]"
|
||||
LSE_CPS_ID_120 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:26[15:19]"
|
||||
LSE_CPS_ID_121 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:26[15:19]"
|
||||
LSE_CPS_ID_122 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
|
||||
LSE_CPS_ID_123 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
|
||||
LSE_CPS_ID_124 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
|
||||
LSE_CPS_ID_125 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
|
||||
LSE_CPS_ID_126 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
|
||||
LSE_CPS_ID_127 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
|
||||
LSE_CPS_ID_128 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
|
||||
LSE_CPS_ID_129 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_130 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_131 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_132 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_133 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_134 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_135 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_136 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_137 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_138 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_139 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_140 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_141 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_142 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_143 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_144 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_145 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_146 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_147 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_148 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_149 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:126[9] 130[5]"
|
||||
LSE_CPS_ID_150 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_151 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_152 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:160[14] 176[8]"
|
||||
LSE_CPS_ID_153 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_154 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:206[26:30]"
|
||||
LSE_CPS_ID_155 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_156 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
|
||||
LSE_CPS_ID_157 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
|
||||
LSE_CPS_ID_158 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:225[8:20]"
|
||||
LSE_CPS_ID_159 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
|
||||
LSE_CPS_ID_160 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_161 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
|
||||
LSE_CPS_ID_162 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:225[8:20]"
|
||||
LSE_CPS_ID_163 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
|
||||
LSE_CPS_ID_164 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
|
||||
LSE_CPS_ID_165 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
|
||||
LSE_CPS_ID_166 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_167 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_168 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_169 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_170 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
|
||||
LSE_CPS_ID_171 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_172 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_173 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_174 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_175 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:225[8:20]"
|
||||
LSE_CPS_ID_176 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
|
||||
LSE_CPS_ID_177 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_178 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_179 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_180 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_181 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
|
||||
LSE_CPS_ID_182 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_183 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_184 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_185 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_186 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_187 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_188 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_189 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_190 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_191 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_192 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_193 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_194 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_195 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:692[20:26]"
|
||||
LSE_CPS_ID_196 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_197 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_198 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_199 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_200 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:267[12] 276[6]"
|
||||
LSE_CPS_ID_201 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_202 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
|
||||
LSE_CPS_ID_203 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_204 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
|
||||
LSE_CPS_ID_205 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
|
||||
LSE_CPS_ID_206 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_207 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_208 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_209 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_210 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_211 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_212 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_213 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_214 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_215 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_216 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
|
||||
LSE_CPS_ID_217 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
|
||||
LSE_CPS_ID_218 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
|
||||
LSE_CPS_ID_219 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_220 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_221 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_222 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[12] 729[6]"
|
||||
LSE_CPS_ID_223 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_224 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_225 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_226 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
|
||||
LSE_CPS_ID_227 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
|
||||
LSE_CPS_ID_228 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
|
||||
LSE_CPS_ID_229 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_230 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:522[30:46]"
|
||||
LSE_CPS_ID_231 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
|
||||
LSE_CPS_ID_232 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:522[30:46]"
|
||||
LSE_CPS_ID_233 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_234 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_235 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:72[15:31]"
|
||||
LSE_CPS_ID_236 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
|
||||
LSE_CPS_ID_237 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_238 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
|
||||
LSE_CPS_ID_239 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_240 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
|
||||
LSE_CPS_ID_241 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_242 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[12] 729[6]"
|
||||
LSE_CPS_ID_243 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:522[30:46]"
|
||||
LSE_CPS_ID_244 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[12] 729[6]"
|
||||
LSE_CPS_ID_245 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_246 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_247 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_248 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_249 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_250 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_251 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_252 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[12] 729[6]"
|
||||
LSE_CPS_ID_253 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_254 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_255 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:464[4] 521[11]"
|
||||
LSE_CPS_ID_256 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:267[12] 276[6]"
|
||||
LSE_CPS_ID_257 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_258 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_259 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_260 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_261 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_262 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_263 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_264 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_265 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_266 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_267 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_268 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_269 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_270 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
|
||||
LSE_CPS_ID_271 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:72[15:31]"
|
||||
LSE_CPS_ID_272 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_273 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:72[15:31]"
|
||||
LSE_CPS_ID_274 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_275 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_276 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_277 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:224[12] 276[6]"
|
||||
LSE_CPS_ID_278 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:461[30:46]"
|
||||
LSE_CPS_ID_279 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_280 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_281 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:178[13] 223[7]"
|
||||
LSE_CPS_ID_282 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_283 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_284 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_285 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:91[22:51]"
|
||||
LSE_CPS_ID_286 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_287 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:19[12:17]"
|
||||
LSE_CPS_ID_288 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_289 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:222[16:37]"
|
||||
LSE_CPS_ID_290 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_291 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_292 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_293 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_294 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_295 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_296 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_297 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_298 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_299 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_300 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_301 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_302 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_303 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_304 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_305 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_306 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[12] 729[6]"
|
||||
LSE_CPS_ID_307 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_308 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_309 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:12[15:34]"
|
||||
LSE_CPS_ID_310 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:135[40:46]"
|
||||
LSE_CPS_ID_311 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_312 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:178[13] 223[7]"
|
||||
LSE_CPS_ID_313 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:224[12] 276[6]"
|
||||
LSE_CPS_ID_314 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_315 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_316 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:301[7:24]"
|
||||
LSE_CPS_ID_317 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_318 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:135[40:46]"
|
||||
LSE_CPS_ID_319 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
|
||||
LSE_CPS_ID_320 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:224[12] 276[6]"
|
||||
LSE_CPS_ID_321 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
|
||||
LSE_CPS_ID_322 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
|
||||
LSE_CPS_ID_323 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_324 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_325 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
|
||||
LSE_CPS_ID_326 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_327 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_328 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_329 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:187[13] 223[7]"
|
||||
LSE_CPS_ID_330 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_331 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:247[14] 254[8]"
|
||||
LSE_CPS_ID_332 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_333 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_334 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_335 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_336 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_337 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_338 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:187[13] 223[7]"
|
||||
LSE_CPS_ID_339 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:224[12] 276[6]"
|
||||
LSE_CPS_ID_340 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_341 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_342 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:57[17:46]"
|
||||
LSE_CPS_ID_343 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_344 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_345 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_346 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_347 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_348 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_349 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:7[8:12]"
|
||||
LSE_CPS_ID_350 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:15[15:20]"
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
[General]
|
||||
showNCD=true
|
||||
showPgroups=true
|
||||
showCongestion=false
|
||||
showConnsSelect=true
|
||||
showConnsBetween=true
|
||||
showConnsOutside=true
|
||||
showLPF=true
|
||||
showREGIONs=true
|
||||
showUGROUPs=true
|
||||
showPARITIONs=true
|
||||
showLogicalConnections=false
|
||||
dontShowBBoxOverlapWarning=false
|
||||
sceneInViewRect=@Variant(\0\0\0\x14@3h.|\xba\x3\x42@\xbd\b\xdd\x8c\x9aJ\xe0@\xdf\x1e\x8e\x8b\0\x46\x39@\xc7\x15kK[@\xe0)
|
||||
|
|
@ -1,4 +1,3 @@
|
|||
[General]
|
||||
Export.auto_tasks=Jedecgen
|
||||
PAR.auto_tasks=@@empty()
|
||||
Map.auto_tasks=@@empty()
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ sig_sort_ascending=true
|
|||
active_Sheet=Port Assignments
|
||||
|
||||
[Port%20Assignments]
|
||||
Name="154,0"
|
||||
Name="160,0"
|
||||
Group%20By="84,1"
|
||||
Pin="50,2"
|
||||
BANK="62,3"
|
||||
|
|
|
|||
|
|
@ -1,20 +1,20 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="RAM2GS_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
|
||||
<BaliProject version="3.2" title="LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2GS"/>
|
||||
<Source name="../RAM2GS-SPI.v" type="Verilog" type_short="Verilog">
|
||||
<Source name="../RAM2GS-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2GS"/>
|
||||
</Source>
|
||||
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
|
||||
<Source name="REFB.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="RAM2GS_LCMXO2_640HC.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Source name="../RAM2GS-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="../RAM2GS.sdc" type="Synplify Design Constraints File" type_short="SDC">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="RAM2GS_LCMXO2_640HC1.sty"/>
|
||||
<Strategy name="Strategy1" file="LCMXO2_640HC1.sty"/>
|
||||
</BaliProject>
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
BLOCK RESETPATHS;
|
||||
BLOCK ASYNCPATHS;
|
||||
|
|
@ -6,24 +6,14 @@
|
|||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn230815045824"></A><B><U><big>pn230815045824</big></U></B>
|
||||
#Start recording tcl command: 8/15/2023 04:58:13
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC
|
||||
RAM2GS_LCMXO2_1200HC
|
||||
#Start recording tcl command: 8/15/2023 04:58:24
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
|
||||
#Stop recording: 8/15/2023 04:58:24
|
||||
|
||||
|
||||
|
||||
<A name="pn230815050055"></A><B><U><big>pn230815050055</big></U></B>
|
||||
#Start recording tcl command: 8/15/2023 05:00:44
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
#Stop recording: 8/15/2023 05:00:55
|
||||
<PRE><A name="pn230816203441"></A><B><U><big>pn230816203441</big></U></B>
|
||||
#Start recording tcl command: 8/16/2023 20:34:10
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project new -name "LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "synplify"
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
|
||||
prj_project save
|
||||
prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf"
|
||||
#Stop recording: 8/16/2023 20:34:41
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#Start recording tcl command: 8/16/2023 20:34:10
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project new -name "LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "synplify"
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
|
||||
prj_project save
|
||||
prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf"
|
||||
#Stop recording: 8/16/2023 20:34:41
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
#Start recording tcl command: 8/16/2023 20:34:55
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Synthesis -impl impl1
|
||||
prj_run Map -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
|
||||
prj_run Export -impl impl1
|
||||
#Stop recording: 8/16/2023 21:03:53
|
||||
|
|
@ -1,205 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Both" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="70" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="Auto" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
#Start recording tcl command: 8/15/2023 04:58:13
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC
|
||||
RAM2GS_LCMXO2_1200HC
|
||||
#Start recording tcl command: 8/15/2023 04:58:24
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
|
||||
#Stop recording: 8/15/2023 04:58:24
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
#Start recording tcl command: 8/15/2023 05:00:44
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
#Stop recording: 8/15/2023 05:00:55
|
||||
|
|
@ -1,79 +0,0 @@
|
|||
#Start recording tcl command: 8/15/2023 22:16:47
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
|
||||
prj_run Export -impl impl1
|
||||
pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
launch_synplify_prj impl1
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_strgy set_value -strategy Strategy1 syn_pipelining_retiming=None syn_frequency=70
|
||||
prj_strgy set_value -strategy Strategy1 map_io_reg=Both
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_project close
|
||||
pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_project close
|
||||
pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_project close
|
||||
pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_project close
|
||||
pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_program run
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
pgr_program run
|
||||
pgr_project save "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_project save
|
||||
prj_project close
|
||||
#Stop recording: 8/16/2023 01:57:20
|
||||
|
|
@ -1,12 +1,12 @@
|
|||
(edif EFB
|
||||
(edif REFB
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2021 8 17 5 48 29)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.12.0.240.2"))))
|
||||
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ")
|
||||
(timestamp 2023 8 16 20 52 2)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
|
||||
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
|
|
@ -248,7 +248,7 @@
|
|||
(direction OUTPUT))
|
||||
(port CFGSTDBY
|
||||
(direction OUTPUT)))))
|
||||
(cell EFB
|
||||
(cell REFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
|
|
@ -383,7 +383,7 @@
|
|||
(property EFB_I2C1
|
||||
(string "DISABLED"))
|
||||
(property EFB_WB_CLK_FREQ
|
||||
(string "16.0")))
|
||||
(string "62.5")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
|
|
@ -544,7 +544,7 @@
|
|||
(joined
|
||||
(portRef wb_clk_i)
|
||||
(portRef WBCLKI (instanceRef EFBInst_0))))))))
|
||||
(design EFB
|
||||
(cellRef EFB
|
||||
(design REFB
|
||||
(cellRef REFB
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 16 20:52:14.413" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 08 16 20:52:02.825"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 08 16 20:52:02.871"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 16 20:52:02.871"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
|
|
@ -13,11 +13,11 @@ CoreType=LPM
|
|||
CoreStatus=Demo
|
||||
CoreName=EFB
|
||||
CoreRevision=1.2
|
||||
ModuleName=EFB
|
||||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=08/17/2021
|
||||
Time=05:48:29
|
||||
Date=08/16/2023
|
||||
Time=20:52:02
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
|
|
@ -81,7 +81,7 @@ ufm2=0
|
|||
ufm3=0
|
||||
ufm_cfg0=0
|
||||
ufm_cfg1=0
|
||||
wb_clk_freq=16
|
||||
wb_clk_freq=62.5
|
||||
ufm_usage=SHARED_EBR_TAG
|
||||
ufm_ebr=190
|
||||
ufm_remain=
|
||||
|
|
@ -138,4 +138,4 @@ t_wbport=0
|
|||
t_portlock=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
|
|
@ -0,0 +1 @@
|
|||
REFB.v
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Tue Aug 17 05:48:29 2021
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Aug 16 20:52:02 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -7,20 +7,20 @@ Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
Circuit name : EFB
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : EFB.edn
|
||||
Verilog output : EFB.v
|
||||
Verilog template : EFB_tmpl.v
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : EFB.srp
|
||||
Report output : REFB.srp
|
||||
Element Usage :
|
||||
EFB : 1
|
||||
Estimated Resource Usage:
|
||||
Binary file not shown.
|
|
@ -1,11 +1,11 @@
|
|||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
|
||||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 */
|
||||
/* Tue Aug 17 05:48:29 2021 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 */
|
||||
/* Wed Aug 16 20:52:02 2023 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
module EFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
||||
module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
||||
wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
|
||||
input wire wb_clk_i;
|
||||
input wire wb_rst_i;
|
||||
|
|
@ -74,7 +74,7 @@ module EFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
|||
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
|
||||
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "16.0" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "62.5" ;
|
||||
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
|
||||
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
|
||||
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
|
||||
|
|
@ -2,8 +2,8 @@ Starting process: Module
|
|||
|
||||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Tue Aug 17 05:48:29 2021
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Aug 16 20:52:02 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -13,25 +13,25 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n EFB -lang verilog -synth lse -bus_exp 7 -bb -type efb -arch xo2c00 -freq 16 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
Circuit name : EFB
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : EFB.edn
|
||||
Verilog output : EFB.v
|
||||
Verilog template : EFB_tmpl.v
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : EFB.srp
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
File: EFB.lpc created.
|
||||
File: REFB.lpc created.
|
||||
|
||||
|
||||
End process: completed successfully.
|
||||
|
|
@ -1,8 +1,8 @@
|
|||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.0.240.2 */
|
||||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* Tue Aug 17 05:48:29 2021 */
|
||||
/* Wed Aug 16 20:52:02 2023 */
|
||||
|
||||
/* parameterized module instance */
|
||||
EFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
.wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ),
|
||||
.wbc_ufm_irq( ));
|
||||
|
|
@ -85,7 +85,7 @@ set Para(install_dir) $env(TOOLRTF)
|
|||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
|
||||
set scuba "$Para(FPGAPath)/scuba"
|
||||
set modulename "EFB"
|
||||
set modulename "REFB"
|
||||
set lang "verilog"
|
||||
set lpcfile "$Para(sbp_path)/$modulename.lpc"
|
||||
set arch "xo2c00"
|
||||
|
|
@ -50,7 +50,7 @@ set Para(install_dir) $env(TOOLRTF)
|
|||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
|
||||
|
||||
set Para(ModuleName) "EFB"
|
||||
set Para(ModuleName) "REFB"
|
||||
set Para(Module) "EFB"
|
||||
set Para(libname) machxo2
|
||||
set Para(arch_name) xo2c00
|
||||
|
|
@ -63,59 +63,9 @@ set Para(SpeedGrade) "4"
|
|||
set Para(FMax) "100"
|
||||
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
|
||||
|
||||
#create LSE project file(*.synproj)
|
||||
proc CreateSynprojFile {} {
|
||||
global Para
|
||||
|
||||
if [catch {open $Para(ModuleName).synproj w} synprojFile] {
|
||||
puts "Cannot create LSE project file $Para(ModuleName).synproj."
|
||||
exit -1
|
||||
} else {
|
||||
puts $synprojFile "-a \"$Para(tech_syn)\"
|
||||
-d $Para(PartType)
|
||||
-t $Para(Package)
|
||||
-s $Para(SpeedGrade)
|
||||
-frequency 200
|
||||
-optimization_goal Balanced
|
||||
-bram_utilization 100
|
||||
-ramstyle auto
|
||||
-romstyle auto
|
||||
-use_carry_chain 1
|
||||
-carry_chain_length 0
|
||||
-force_gsr auto
|
||||
-resource_sharing 1
|
||||
-propagate_constants 1
|
||||
-remove_duplicate_regs 1
|
||||
-mux_style Auto
|
||||
-max_fanout 1000
|
||||
-fsm_encoding_style Auto
|
||||
-twr_paths 3
|
||||
-fix_gated_clocks 1
|
||||
-use_io_insertion 0
|
||||
-resolve_mixed_drivers 0
|
||||
-use_io_reg 1
|
||||
|
||||
-lpf 1
|
||||
-p $Para(sbp_path)
|
||||
-ver \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\"
|
||||
\"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\"
|
||||
\"$Para(sbp_path)/$Para(ModuleName).v\"
|
||||
-top $Para(ModuleName)
|
||||
-ngo \"$Para(sbp_path)/$Para(ModuleName).ngo\"
|
||||
"
|
||||
close $synprojFile
|
||||
}
|
||||
}
|
||||
|
||||
#LSE
|
||||
CreateSynprojFile
|
||||
set ldcfile "$Para(sbp_path)/$Para(ModuleName).ldc"
|
||||
set synthesis "$Para(FPGAPath)/synthesis"
|
||||
if {[file exists $ldcfile] == 0} {
|
||||
set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -gui} msg]
|
||||
} else {
|
||||
set Para(result) [catch {eval exec $synthesis -f \"$Para(ModuleName).synproj\" -sdc \"$ldcfile\" -gui} msg]
|
||||
}
|
||||
#edif2ngd
|
||||
set edif2ngd "$Para(FPGAPath)/edif2ngd"
|
||||
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
|
||||
#puts $msg
|
||||
|
||||
#ngdbuild
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
-- all messages logged in file hdlparser.log
|
||||
-- Analyzing Verilog file 'C:/lscc/diamond/3.12/cae_library/synthesis/verilog/machxo2.v' (VERI-1482)
|
||||
-- Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v' (VERI-1482)
|
||||
|
|
@ -6,46 +6,37 @@
|
|||
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692156613"/>
|
||||
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692233986"/>
|
||||
</Milestone>
|
||||
<Milestone name="Map" build_result="2" build_time="1692156605">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1692156605"/>
|
||||
<Task name="MapTrace" build_result="0" update_result="2" update_time="1692156605"/>
|
||||
<Task name="MapVerilogSimFile" build_result="0" update_result="2" update_time="1692156605"/>
|
||||
<Task name="MapVHDLSimFile" build_result="0" update_result="2" update_time="1692156605"/>
|
||||
<Milestone name="Map" build_result="2" build_time="1692233977">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1692233977"/>
|
||||
<Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="PAR" build_result="2" build_time="1692156611">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1692156611"/>
|
||||
<Task name="PARTrace" build_result="0" update_result="2" update_time="1692156611"/>
|
||||
<Task name="IOTiming" build_result="0" update_result="2" update_time="1692156611"/>
|
||||
<Milestone name="PAR" build_result="2" build_time="1692233984">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1692233984"/>
|
||||
<Task name="PARTrace" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1692155568">
|
||||
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692155568"/>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1692233976">
|
||||
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692233976"/>
|
||||
</Milestone>
|
||||
<Milestone name="TOOL_Report" build_result="0" build_time="0">
|
||||
<Task name="HDLE" build_result="2" update_result="0" update_time="1692155394"/>
|
||||
<Task name="BKM" build_result="0" update_result="2" update_time="1692155394"/>
|
||||
<Task name="HDLE" build_result="0" update_result="2" update_time="1692233963"/>
|
||||
<Task name="BKM" build_result="0" update_result="2" update_time="1692233963"/>
|
||||
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="Translate" build_result="2" build_time="1692155568">
|
||||
<Task name="Translate" build_result="2" update_result="0" update_time="1692155568"/>
|
||||
<Milestone name="Translate" build_result="2" build_time="1692233976">
|
||||
<Task name="Translate" build_result="2" update_result="0" update_time="1692233976"/>
|
||||
</Milestone>
|
||||
<Report name=".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" last_build_time="1692090205" last_build_size="67964"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.bgn" last_build_time="1692156613" last_build_size="4423"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.edi" last_build_time="1692155566" last_build_size="135533"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ior" last_build_time="1692154601" last_build_size="6815"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.jed" last_build_time="1692156613" last_build_size="177183"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.lsedata" last_build_time="1692090203" last_build_size="237766"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ncd" last_build_time="1692156611" last_build_size="204561"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.ngd" last_build_time="1692155568" last_build_size="153585"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.tw1" last_build_time="1692154592" last_build_size="17596"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.twr" last_build_time="1692154599" last_build_size="92704"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_map.ncd" last_build_time="1692156605" last_build_size="149601"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf" last_build_time="1692154593" last_build_size="123467"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvho.vho" last_build_time="1692154593" last_build_size="989165"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf" last_build_time="1692154592" last_build_size="123052"/>
|
||||
<Report name="RAM2GS_LCMXO2_640HC_impl1_mapvo.vo" last_build_time="1692154592" last_build_size="134272"/>
|
||||
<Report name="LCMXO2_640HC_impl1.bgn" last_build_time="1692233986" last_build_size="4399"/>
|
||||
<Report name="LCMXO2_640HC_impl1.edi" last_build_time="1692233975" last_build_size="204145"/>
|
||||
<Report name="LCMXO2_640HC_impl1.jed" last_build_time="1692233986" last_build_size="177085"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ncd" last_build_time="1692233984" last_build_size="278109"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ngd" last_build_time="1692233976" last_build_size="207794"/>
|
||||
<Report name="LCMXO2_640HC_impl1_map.ncd" last_build_time="1692233977" last_build_size="197654"/>
|
||||
</Strategy>
|
||||
</BuildStatus>
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1 +0,0 @@
|
|||
RAM2GS_rtl.vdb
|
||||
|
|
@ -1,33 +1,11 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Tue Aug 17 06:21:09 2021 *
|
||||
NOTE DATE CREATED: Wed Aug 16 20:59:46 2023 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RCLK : 63 : in *
|
||||
NOTE PINS nFWE : 15 : in *
|
||||
NOTE PINS nCRAS : 17 : in *
|
||||
NOTE PINS nCCAS : 9 : in *
|
||||
NOTE PINS Din[0] : 3 : in *
|
||||
NOTE PINS Din[1] : 96 : in *
|
||||
NOTE PINS Din[2] : 88 : in *
|
||||
NOTE PINS Din[3] : 97 : in *
|
||||
NOTE PINS Din[4] : 99 : in *
|
||||
NOTE PINS Din[5] : 98 : in *
|
||||
NOTE PINS Din[6] : 2 : in *
|
||||
NOTE PINS Din[7] : 1 : in *
|
||||
NOTE PINS CROW[0] : 10 : in *
|
||||
NOTE PINS CROW[1] : 16 : in *
|
||||
NOTE PINS MAin[0] : 14 : in *
|
||||
NOTE PINS MAin[1] : 12 : in *
|
||||
NOTE PINS MAin[2] : 13 : in *
|
||||
NOTE PINS MAin[3] : 21 : in *
|
||||
NOTE PINS MAin[4] : 20 : in *
|
||||
NOTE PINS MAin[5] : 19 : in *
|
||||
NOTE PINS MAin[6] : 24 : in *
|
||||
NOTE PINS MAin[7] : 18 : in *
|
||||
NOTE PINS MAin[8] : 25 : in *
|
||||
NOTE PINS MAin[9] : 32 : in *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS Dout[0] : 76 : out *
|
||||
NOTE PINS PHI2 : 8 : in *
|
||||
NOTE PINS RDQML : 48 : out *
|
||||
NOTE PINS RDQMH : 51 : out *
|
||||
|
|
@ -35,37 +13,59 @@ NOTE PINS nRCAS : 52 : out *
|
|||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS RCLK : 62 : in *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[3] : 71 : out *
|
||||
NOTE PINS RA[4] : 74 : out *
|
||||
NOTE PINS RA[5] : 70 : out *
|
||||
NOTE PINS RA[6] : 68 : out *
|
||||
NOTE PINS RA[7] : 75 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[9] : 62 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS Dout[0] : 76 : out *
|
||||
NOTE PINS Dout[1] : 86 : out *
|
||||
NOTE PINS Dout[2] : 87 : out *
|
||||
NOTE PINS Dout[3] : 85 : out *
|
||||
NOTE PINS Dout[4] : 83 : out *
|
||||
NOTE PINS Dout[5] : 84 : out *
|
||||
NOTE PINS Dout[6] : 78 : out *
|
||||
NOTE PINS Dout[7] : 82 : out *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 75 : out *
|
||||
NOTE PINS RA[6] : 68 : out *
|
||||
NOTE PINS RA[5] : 70 : out *
|
||||
NOTE PINS RA[4] : 74 : out *
|
||||
NOTE PINS RA[3] : 71 : out *
|
||||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS nFWE : 15 : in *
|
||||
NOTE PINS nCRAS : 17 : in *
|
||||
NOTE PINS nCCAS : 9 : in *
|
||||
NOTE PINS Dout[7] : 82 : out *
|
||||
NOTE PINS Dout[6] : 78 : out *
|
||||
NOTE PINS Dout[5] : 84 : out *
|
||||
NOTE PINS Dout[4] : 83 : out *
|
||||
NOTE PINS Dout[3] : 85 : out *
|
||||
NOTE PINS Dout[2] : 87 : out *
|
||||
NOTE PINS Dout[1] : 86 : out *
|
||||
NOTE PINS Din[7] : 1 : in *
|
||||
NOTE PINS Din[6] : 2 : in *
|
||||
NOTE PINS Din[5] : 98 : in *
|
||||
NOTE PINS Din[4] : 99 : in *
|
||||
NOTE PINS Din[3] : 97 : in *
|
||||
NOTE PINS Din[2] : 88 : in *
|
||||
NOTE PINS Din[1] : 96 : in *
|
||||
NOTE PINS Din[0] : 3 : in *
|
||||
NOTE PINS CROW[1] : 16 : in *
|
||||
NOTE PINS CROW[0] : 10 : in *
|
||||
NOTE PINS MAin[9] : 32 : in *
|
||||
NOTE PINS MAin[8] : 25 : in *
|
||||
NOTE PINS MAin[7] : 18 : in *
|
||||
NOTE PINS MAin[6] : 24 : in *
|
||||
NOTE PINS MAin[5] : 19 : in *
|
||||
NOTE PINS MAin[4] : 20 : in *
|
||||
NOTE PINS MAin[3] : 21 : in *
|
||||
NOTE PINS MAin[2] : 13 : in *
|
||||
NOTE PINS MAin[1] : 12 : in *
|
||||
NOTE PINS MAin[0] : 14 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.verilog
|
||||
|
||||
Register bits: 109 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 10 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 27 100.0
|
||||
FD1P3IX 3 100.0
|
||||
FD1S3AX 51 100.0
|
||||
FD1S3IX 3 100.0
|
||||
GSR 1 100.0
|
||||
IB 25 100.0
|
||||
IFS1P3DX 9 100.0
|
||||
INV 8 100.0
|
||||
OB 30 100.0
|
||||
OFS1P3BX 4 100.0
|
||||
OFS1P3DX 11 100.0
|
||||
OFS1P3JX 1 100.0
|
||||
ORCALUT4 206 100.0
|
||||
PFUMX 1 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 405
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
VHI 1 50.0
|
||||
VLO 1 50.0
|
||||
|
||||
TOTAL 3
|
||||
|
|
@ -4,12 +4,12 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 23:30:11 2023
|
||||
Wed Aug 16 20:59:44 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
|
||||
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
|
|
@ -22,7 +22,7 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
Reading Preference File from LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
|
|
@ -70,7 +70,7 @@ Creating bit map...
|
|||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
|
||||
Saving bit stream in "LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
|
|
@ -79,8 +79,8 @@ UFM Size: 191 Pages (128*191 Bits).
|
|||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 0 Page.
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 246 MB
|
||||
Peak Memory Usage: 245 MB
|
||||
Binary file not shown.
|
|
@ -6,7 +6,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Tue Aug 15 23:30:09 2023
|
||||
Wed Aug 16 20:59:41 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
|
@ -68,9 +68,6 @@ Pinout by Port Name:
|
|||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| UFMCLK | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| UFMSDI | 29/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| UFMSDO | 27/2 | LVCMOS33_IN | PB4A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
|
|
@ -78,7 +75,6 @@ Pinout by Port Name:
|
|||
| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nUFMCS | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
|
|
@ -121,10 +117,10 @@ Pinout by Pin Number:
|
|||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | |
|
||||
| 27/2 | UFMSDO | LOCATED | LVCMOS33_IN | PB4A | CSSPIN | | |
|
||||
| 28/2 | UFMCLK | LOCATED | LVCMOS33_OUT | PB4B | | | |
|
||||
| 29/2 | UFMSDI | LOCATED | LVCMOS33_OUT | PB4C | | | |
|
||||
| 30/2 | nUFMCS | LOCATED | LVCMOS33_OUT | PB4D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
|
||||
|
|
@ -255,9 +251,6 @@ LOCATE COMP "RD[4]" SITE "40";
|
|||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "UFMCLK" SITE "28";
|
||||
LOCATE COMP "UFMSDI" SITE "29";
|
||||
LOCATE COMP "UFMSDO" SITE "27";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
|
|
@ -265,7 +258,6 @@ LOCATE COMP "nRCAS" SITE "52";
|
|||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
LOCATE COMP "nUFMCS" SITE "30";
|
||||
|
||||
|
||||
|
||||
|
|
@ -277,5 +269,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 15 23:30:11 2023
|
||||
Wed Aug 16 20:59:42 2023
|
||||
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
|
||||
Sat Oct 09 01:19:16 2021
|
||||
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
|
||||
Wed Aug 16 20:59:37 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
|
||||
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
|
|
@ -26,62 +26,66 @@ Device utilization summary:
|
|||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
|
||||
SLICE 131/320 40% used
|
||||
SLICE 117/320 36% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 401
|
||||
Number of Connections: 1131
|
||||
Number of Signals: 380
|
||||
Number of Connections: 1008
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 4 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 52)
|
||||
PHI2_c (driver: PHI2, clk load #: 13)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 7)
|
||||
nCCAS_c (driver: nCCAS, clk load #: 4)
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 46)
|
||||
PHI2_c (driver: PHI2, clk load #: 19)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 10)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
No signal is selected as secondary clock.
|
||||
The following 2 signals are selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
..............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 65362.
|
||||
...................
|
||||
Placer score = 55012.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 65089
|
||||
Placer score = 54994
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 1 out of 8 (12%)
|
||||
General PIO: 3 out of 80 (3%)
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 4 out of 80 (5%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 52
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7
|
||||
PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 4
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 4 out of 8 (50%)
|
||||
SECONDARY: 0 out of 8 (0%)
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 2 out of 8 (25%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
|
@ -102,22 +106,21 @@ I/O Bank Usage Summary:
|
|||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 4 secs
|
||||
Total placer CPU time: 3 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1131 unrouted.
|
||||
0 connections routed; 1008 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Completed router resource preassignment. Real time: 6 secs
|
||||
Completed router resource preassignment. Real time: 5 secs
|
||||
|
||||
Start NBR router at 01:19:22 10/09/21
|
||||
Start NBR router at 20:59:43 08/16/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
|
@ -132,53 +135,54 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 01:19:22 10/09/21
|
||||
Start NBR special constraint process at 20:59:43 08/16/23
|
||||
|
||||
Start NBR section for initial routing at 01:19:22 10/09/21
|
||||
Start NBR section for initial routing at 20:59:43 08/16/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 01:19:22 10/09/21
|
||||
Start NBR section for normal routing at 20:59:43 08/16/23
|
||||
Level 1, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 2
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
|
||||
|
||||
Start NBR section for re-routing at 01:19:23 10/09/21
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
|
||||
Level 4, iteration 0
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 0
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for post-routing at 01:19:23 10/09/21
|
||||
Start NBR section for re-routing at 20:59:44 08/16/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for post-routing at 20:59:44 08/16/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
|
@ -186,7 +190,7 @@ NBR Summary
|
|||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 1.135ns
|
||||
Estimated worst slack<setup> : 4.922ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
|
@ -196,16 +200,16 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
|
|||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Total CPU time 7 secs
|
||||
Total CPU time 6 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 1131 routed (100.00%); 0 unrouted.
|
||||
End of route. 1008 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
|
@ -213,13 +217,13 @@ All signals are completely routed.
|
|||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 1.135
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 7 secs
|
||||
Total CPU time to completion: 6 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
|
@ -1,21 +1,25 @@
|
|||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 2;
|
||||
GLOBAL_PRIMARY_USED = 3;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 39;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 46;
|
||||
; Global primary clock #1
|
||||
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
|
||||
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 18;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 19;
|
||||
; Global primary clock #2
|
||||
GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_2_LOADNUM = 10;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 2;
|
||||
; Global secondary clock #0
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 11;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = un1_wb_clk32_i;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 10;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = CE;
|
||||
; Global secondary clock #1
|
||||
GLOBAL_SECONDARY_1_SIGNALNAME = nCCAS_c;
|
||||
GLOBAL_SECONDARY_1_DRIVERTYPE = PIO;
|
||||
|
|
@ -32,7 +36,7 @@ BANK_1_AVAIL = 20;
|
|||
BANK_1_VCCIO = 3.3V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 16;
|
||||
BANK_2_USED = 12;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 3.3V;
|
||||
BANK_2_VREF1 = NA;
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue