2023-08-20 11:10:11 +00:00
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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2024-01-07 02:52:05 +00:00
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# Written on Sat Jan 6 06:24:50 2024
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2023-08-20 11:10:11 +00:00
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##### FILES SYNTAX CHECKED ##############################################
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2023-09-21 09:45:45 +00:00
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Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
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2023-08-20 11:10:11 +00:00
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#Run constraint checker to find more issues with constraints.
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#########################################################################
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No issues found in constraint syntax.
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Clock Summary
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*************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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---------------------------------------------------------------------------------------
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0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 48
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0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19
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0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14
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0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8
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=======================================================================================
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Clock Load Summary
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******************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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----------------------------------------------------------------------------------------
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RCLK 48 RCLK(port) CASr2.C - -
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PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
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nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
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nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
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========================================================================================
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