Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 63+4(JTAG)/80 84% used
63+4(JTAG)/79 85% bonded
SLICE 131/320 40% used
EFB 1/1 100% used
Number of Signals: 401
Number of Connections: 1131
Pin Constraint Summary:
63 out of 63 pins locked (100% locked).
The following 4 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 52)
PHI2_c (driver: PHI2, clk load #: 13)
nCRAS_c (driver: nCRAS, clk load #: 7)
nCCAS_c (driver: nCCAS, clk load #: 4)
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal "nCCAS_c" is selected to use Primary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 1131 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.