idk
This commit is contained in:
Zane Kaminski
parent
3364401289
commit
bbab55626a
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@ -29,6 +29,34 @@ prj_run Export -impl impl1 -forceAll
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<A name="pn210817062320"></A><B><U><big>pn210817062320</big></U></B>
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#Start recording tcl command: 8/17/2021 05:49:30
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#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
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prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/EFB.v"
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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prj_run Synthesis -impl impl1
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prj_run Synthesis -impl impl1 -forceOne
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prj_run Map -impl impl1 -forceOne
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceOne
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#Stop recording: 8/17/2021 06:23:20
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<BR>
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<BR>
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<BR>
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@ -0,0 +1,6 @@
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#Start recording tcl command: 10/9/2021 01:18:46
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#Project Location: C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
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prj_project open "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
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prj_run Map -impl impl1 -forceAll
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prj_run PAR -impl impl1 -forceAll
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#Stop recording: 10/10/2021 06:41:44
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@ -2,26 +2,26 @@
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<BuildStatus>
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<Strategy name="Strategy1">
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<Milestone name="Export" build_result="0" build_time="0">
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<Task name="IBIS" build_result="0" update_result="2" update_time="1629195665"/>
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<Task name="IBIS" build_result="0" update_result="2" update_time="1633756763"/>
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<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
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<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
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||||
<Task name="Bitgen" build_result="2" update_result="0" update_time="1629195667"/>
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<Task name="Jedecgen" build_result="2" update_result="0" update_time="1629195669"/>
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<Task name="Bitgen" build_result="0" update_result="2" update_time="1633756763"/>
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<Task name="Jedecgen" build_result="0" update_result="2" update_time="1633756763"/>
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</Milestone>
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<Milestone name="Map" build_result="2" build_time="1629195651">
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<Task name="Map" build_result="2" update_result="0" update_time="1629195651"/>
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<Task name="MapTrace" build_result="2" update_result="0" update_time="1629195651"/>
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<Milestone name="Map" build_result="2" build_time="1633756755">
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<Task name="Map" build_result="2" update_result="0" update_time="1633756755"/>
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<Task name="MapTrace" build_result="2" update_result="0" update_time="1633756755"/>
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<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
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<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
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</Milestone>
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<Milestone name="PAR" build_result="2" build_time="1629195661">
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<Task name="PAR" build_result="2" update_result="0" update_time="1629195661"/>
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<Task name="PARTrace" build_result="2" update_result="0" update_time="1629195661"/>
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<Task name="IOTiming" build_result="2" update_result="0" update_time="1629195663"/>
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<Milestone name="PAR" build_result="2" build_time="1633756763">
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<Task name="PAR" build_result="2" update_result="0" update_time="1633756763"/>
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<Task name="PARTrace" build_result="2" update_result="0" update_time="1633756764"/>
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<Task name="IOTiming" build_result="2" update_result="0" update_time="1633756765"/>
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</Milestone>
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<Milestone name="Synthesis" build_result="2" build_time="1629195586">
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<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1629195586"/>
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<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1629195585"/>
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<Milestone name="Synthesis" build_result="2" build_time="1633756754">
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<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1633756754"/>
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<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1633756753"/>
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</Milestone>
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<Milestone name="TOOL_Report" build_result="0" build_time="0">
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<Task name="HDLE" build_result="2" update_result="0" update_time="1629194861"/>
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@ -30,17 +30,17 @@
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<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
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<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
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</Milestone>
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<Report name=".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" last_build_time="1629195651" last_build_size="90359"/>
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<Report name=".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" last_build_time="1633756755" last_build_size="91027"/>
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<Report name="IBIS/RAM2GS_LCMXO2_640HC_impl1.ibs" last_build_time="0" last_build_size="0"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.bgn" last_build_time="1629195669" last_build_size="4441"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.bit" last_build_time="1629195667" last_build_size="6667"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.ior" last_build_time="1629195663" last_build_size="6533"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.ior" last_build_time="1633756765" last_build_size="6451"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.jed" last_build_time="1629195669" last_build_size="177066"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.lsedata" last_build_time="1629195585" last_build_size="407682"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.ncd" last_build_time="1629195661" last_build_size="302666"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.ngd" last_build_time="1629195586" last_build_size="234541"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.tw1" last_build_time="1629195651" last_build_size="113451"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.twr" last_build_time="1629195661" last_build_size="194524"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1_map.ncd" last_build_time="1629195650" last_build_size="212106"/>
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||||
<Report name="RAM2GS_LCMXO2_640HC_impl1.lsedata" last_build_time="1633756753" last_build_size="407682"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.ncd" last_build_time="1633756763" last_build_size="302666"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.ngd" last_build_time="1633756754" last_build_size="234541"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.tw1" last_build_time="1633756755" last_build_size="113287"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1.twr" last_build_time="1633756764" last_build_size="194360"/>
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<Report name="RAM2GS_LCMXO2_640HC_impl1_map.ncd" last_build_time="1633756755" last_build_size="212106"/>
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</Strategy>
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</BuildStatus>
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Binary file not shown.
Binary file not shown.
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@ -6,7 +6,7 @@ Performance Grade: 4
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PACKAGE: TQFP100
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Package Status: Final Version 1.39
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Tue Aug 17 06:20:57 2021
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Sat Oct 09 01:19:20 2021
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Pinout by Port Name:
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+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
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@ -269,5 +269,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Tue Aug 17 06:20:59 2021
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Sat Oct 09 01:19:22 2021
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@ -1,9 +1,9 @@
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Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
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Tue Aug 17 06:20:51 2021
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Sat Oct 09 01:19:16 2021
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PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
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Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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@ -58,12 +58,12 @@ Finished Placer Phase 0. REAL time: 0 secs
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Starting Placer Phase 1.
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....................
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Placer score = 65362.
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Finished Placer Phase 1. REAL time: 6 secs
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Finished Placer Phase 1. REAL time: 4 secs
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Starting Placer Phase 2.
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.
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Placer score = 65089
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Finished Placer Phase 2. REAL time: 6 secs
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Finished Placer Phase 2. REAL time: 4 secs
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------------------ Clock Report ------------------
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@ -102,7 +102,7 @@ I/O Bank Usage Summary:
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| 3 | 18 / 20 ( 90%) | 3.3V | - |
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+----------+----------------+------------+-----------+
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Total placer CPU time: 5 secs
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Total placer CPU time: 4 secs
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Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
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@ -115,9 +115,9 @@ WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of t
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WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
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Signal=wb_clk loads=1 clock_loads=1
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Completed router resource preassignment. Real time: 8 secs
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Completed router resource preassignment. Real time: 6 secs
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Start NBR router at 06:20:59 08/17/21
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Start NBR router at 01:19:22 10/09/21
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*****************************************************************
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Info: NBR allows conflicts(one node used by more than one signal)
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@ -132,53 +132,53 @@ Note: NBR uses a different method to calculate timing slacks. The
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your design.
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*****************************************************************
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Start NBR special constraint process at 06:20:59 08/17/21
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Start NBR special constraint process at 01:19:22 10/09/21
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Start NBR section for initial routing at 06:20:59 08/17/21
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Start NBR section for initial routing at 01:19:22 10/09/21
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Level 1, iteration 1
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0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 8 secs
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Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs
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Level 2, iteration 1
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1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs
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Level 3, iteration 1
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1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
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Level 4, iteration 1
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26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
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Info: Initial congestion level at 75% usage is 0
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Info: Initial congestion area at 75% usage is 0 (0.00%)
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Start NBR section for normal routing at 06:21:00 08/17/21
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Start NBR section for normal routing at 01:19:22 10/09/21
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Level 1, iteration 1
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1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
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Level 2, iteration 1
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1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
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Level 3, iteration 1
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1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
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Level 4, iteration 1
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12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
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Level 4, iteration 2
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5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
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Level 4, iteration 3
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
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Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
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Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
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Start NBR section for re-routing at 06:21:00 08/17/21
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Start NBR section for re-routing at 01:19:23 10/09/21
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
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Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
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Start NBR section for post-routing at 06:21:00 08/17/21
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Start NBR section for post-routing at 01:19:23 10/09/21
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End NBR router with 0 unrouted connection
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@ -196,8 +196,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
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WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
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Signal=wb_clk loads=1 clock_loads=1
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Total CPU time 9 secs
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Total REAL time: 10 secs
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Total CPU time 7 secs
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Total REAL time: 7 secs
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Completely routed.
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End of route. 1131 routed (100.00%); 0 unrouted.
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@ -219,8 +219,8 @@ PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
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PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
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PAR_SUMMARY::Number of errors = 0
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Total CPU time to completion: 9 secs
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Total REAL time to completion: 10 secs
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Total CPU time to completion: 7 secs
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Total REAL time to completion: 7 secs
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par done!
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@ -4,12 +4,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Tue Aug 17 06:20:51 2021
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Sat Oct 09 01:19:16 2021
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C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
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RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
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RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
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C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
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RAM2GS_LCMXO2_640HC_impl1.prf -gui
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Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
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@ -17,11 +16,11 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
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Level/ Number Worst Timing Worst Timing Run NCD
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Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
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---------- -------- ----- ------ ----------- ----------- ---- ------
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5_1 * 0 1.135 0 0.304 0 10 Completed
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5_1 * 0 1.135 0 0.304 0 07 Completed
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* : Design saved.
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Total (real) run time for 1-seed: 10 secs
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Total (real) run time for 1-seed: 7 secs
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par done!
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@ -1,9 +1,9 @@
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<top name = "RAM2GS" library = "work" arch = "" entry = "Verilog">
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<clocks>
|
||||
<clockitem name = "PHI2" type = "port" />
|
||||
<clockitem name = "nCCAS" type = "port" />
|
||||
<clockitem name = "nCRAS" type = "port" />
|
||||
<clockitem name = "nCCAS" type = "port" />
|
||||
<clockitem name = "PHI2" type = "port" />
|
||||
<clockitem name = "RCLK" type = "port" />
|
||||
<clockitem name = "wb_clk" type = "net" />
|
||||
</clocks>
|
||||
|
|
|
|||
|
|
@ -8,15 +8,14 @@ Design Information
|
|||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
|
||||
rs/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2
|
||||
_640HC_impl1.lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMX
|
||||
O2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
|
||||
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
|
||||
rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX
|
||||
O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/
|
||||
LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.0.240.2
|
||||
Mapped on: 08/17/21 06:20:50
|
||||
Mapped on: 10/09/21 01:19:14
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
|
@ -60,17 +59,17 @@ Design Summary
|
|||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 14
|
||||
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
|
||||
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/17/21 06:20:50
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
|
||||
Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
|
||||
Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
|
||||
Net InitReady: 1 loads, 1 LSLICEs
|
||||
|
|
@ -126,17 +125,17 @@ IO (PIO) Attributes
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVTTL33 | |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/17/21 06:20:50
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nFWE | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -192,17 +191,17 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVTTL33 | |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/17/21 06:20:50
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nRWE | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -258,17 +257,17 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVTTL33 | |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/17/21 06:20:50
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| RD[2] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -324,17 +323,17 @@ Embedded Functional Block Connection Summary
|
|||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/17/21 06:20:50
|
||||
Design: RAM2GS Date: 10/09/21 01:19:14
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
|
|
@ -366,7 +365,7 @@ Run Time and Memory Usage
|
|||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 36 MB
|
||||
Peak Memory Usage: 37 MB
|
||||
|
||||
|
||||
|
||||
|
|
@ -389,6 +388,7 @@ Run Time and Memory Usage
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 6
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -6,7 +6,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Tue Aug 17 06:20:57 2021
|
||||
Sat Oct 09 01:19:20 2021
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
|
@ -269,5 +269,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 17 06:20:59 2021
|
||||
Sat Oct 09 01:19:22 2021
|
||||
|
||||
|
|
|
|||
|
|
@ -4,12 +4,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 17 06:20:51 2021
|
||||
Sat Oct 09 01:19:16 2021
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
|
||||
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -gui
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
|
|
@ -17,21 +16,21 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
|||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 1.135 0 0.304 0 10 Completed
|
||||
5_1 * 0 1.135 0 0.304 0 07 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 10 secs
|
||||
Total (real) run time for 1-seed: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
|
||||
Tue Aug 17 06:20:51 2021
|
||||
Sat Oct 09 01:19:16 2021
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
|
@ -86,12 +85,12 @@ Finished Placer Phase 0. REAL time: 0 secs
|
|||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 65362.
|
||||
Finished Placer Phase 1. REAL time: 6 secs
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 65089
|
||||
Finished Placer Phase 2. REAL time: 6 secs
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
|
@ -130,7 +129,7 @@ I/O Bank Usage Summary:
|
|||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 5 secs
|
||||
Total placer CPU time: 4 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
|
@ -143,9 +142,9 @@ WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of t
|
|||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Completed router resource preassignment. Real time: 8 secs
|
||||
Completed router resource preassignment. Real time: 6 secs
|
||||
|
||||
Start NBR router at 06:20:59 08/17/21
|
||||
Start NBR router at 01:19:22 10/09/21
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
|
@ -160,53 +159,53 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 06:20:59 08/17/21
|
||||
Start NBR special constraint process at 01:19:22 10/09/21
|
||||
|
||||
Start NBR section for initial routing at 06:20:59 08/17/21
|
||||
Start NBR section for initial routing at 01:19:22 10/09/21
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 8 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 06:21:00 08/17/21
|
||||
Start NBR section for normal routing at 01:19:22 10/09/21
|
||||
Level 1, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 1
|
||||
12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 2
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
|
||||
|
||||
Start NBR section for re-routing at 06:21:00 08/17/21
|
||||
Start NBR section for re-routing at 01:19:23 10/09/21
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for post-routing at 06:21:00 08/17/21
|
||||
Start NBR section for post-routing at 01:19:23 10/09/21
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
|
@ -224,8 +223,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
|
|||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Total CPU time 9 secs
|
||||
Total REAL time: 10 secs
|
||||
Total CPU time 7 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 1131 routed (100.00%); 0 unrouted.
|
||||
|
||||
|
|
@ -247,8 +246,8 @@ PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
|||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 9 secs
|
||||
Total REAL time to completion: 10 secs
|
||||
Total CPU time to completion: 7 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Tue Aug 17 06:20:50 2021
|
||||
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RCLK" SITE "63" ;
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Tue Aug 17 06:20:51 2021
|
||||
Sat Oct 09 01:19:15 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -23,7 +23,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
|
|
@ -1302,7 +1302,7 @@ Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Tue Aug 17 06:20:51 2021
|
||||
Sat Oct 09 01:19:15 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -1312,7 +1312,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Tue Aug 17 06:21:01 2021
|
||||
Sat Oct 09 01:19:23 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -23,7 +23,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
|
|
@ -2376,7 +2376,7 @@ Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
|
||||
Tue Aug 17 06:21:01 2021
|
||||
Sat Oct 09 01:19:24 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -2386,7 +2386,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,m
|
||||
|
|
|
|||
|
|
@ -38,9 +38,9 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.0.240.2
|
||||
// Written on Tue Aug 17 06:21:03 2021
|
||||
// Written on Sat Oct 09 01:19:25 2021
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
|
||||
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
|
|
|
|||
|
|
@ -30,12 +30,12 @@
|
|||
|
||||
|
||||
-lpf 1
|
||||
-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
|
||||
-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
|
||||
-p "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
|
||||
-ver "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
|
||||
-top RAM2GS
|
||||
|
||||
|
||||
-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
|
||||
-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
|
||||
|
||||
-ngd "RAM2GS_LCMXO2_640HC_impl1.ngd"
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ FS_972_add_4_19/CO
|
|||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Tue Aug 17 06:20:50 2021
|
||||
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RCLK" SITE "63" ;
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -16,15 +16,14 @@
|
|||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
|
||||
rs/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2
|
||||
_640HC_impl1.lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMX
|
||||
O2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
|
||||
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
|
||||
rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX
|
||||
O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/
|
||||
LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.0.240.2
|
||||
Mapped on: 08/17/21 06:20:50
|
||||
Mapped on: 10/09/21 01:19:14
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
|
|
@ -67,8 +66,8 @@ Mapped on: 08/17/21 06:20:50
|
|||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 14
|
||||
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
|
||||
|
||||
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
|
||||
|
||||
Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
|
||||
Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
|
||||
Net InitReady: 1 loads, 1 LSLICEs
|
||||
|
|
@ -127,8 +126,8 @@ Mapped on: 08/17/21 06:20:50
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| nFWE | INPUT | LVTTL33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -184,8 +183,8 @@ Mapped on: 08/17/21 06:20:50
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| nRWE | OUTPUT | LVTTL33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -241,8 +240,8 @@ Mapped on: 08/17/21 06:20:50
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| RD[2] | BIDIR | LVTTL33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVTTL33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
|
@ -300,8 +299,8 @@ Block i1 was optimized away.
|
|||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
|
||||
--------------------
|
||||
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
|
|
@ -337,7 +336,7 @@ Instance Name: ufmefb
|
|||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 36 MB
|
||||
Peak Memory Usage: 37 MB
|
||||
|
||||
|
||||
|
||||
|
|
@ -362,6 +361,7 @@ Instance Name: ufmefb
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Tue Aug 17 06:20:57 2021
|
||||
Sat Oct 09 01:19:20 2021
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
|
@ -278,7 +278,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 17 06:20:59 2021
|
||||
Sat Oct 09 01:19:22 2021
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -12,12 +12,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 17 06:20:51 2021
|
||||
Sat Oct 09 01:19:16 2021
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
|
||||
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
|
||||
RAM2GS_LCMXO2_640HC_impl1.prf -gui
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
|
|
@ -26,22 +25,22 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
|||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 1.135 0 0.304 0 10 Completed
|
||||
5_1 * 0 1.135 0 0.304 0 07 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 10 secs
|
||||
Total (real) run time for 1-seed: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
|
||||
Tue Aug 17 06:20:51 2021
|
||||
Sat Oct 09 01:19:16 2021
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
|
@ -97,12 +96,12 @@ Finished Placer Phase 0. REAL time: 0 secs
|
|||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 65362.
|
||||
Finished Placer Phase 1. REAL time: 6 secs
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 65089
|
||||
Finished Placer Phase 2. REAL time: 6 secs
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
|
||||
|
|
@ -142,7 +141,7 @@ I/O Bank Usage Summary:
|
|||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 5 secs
|
||||
Total placer CPU time: 4 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
|
@ -155,9 +154,9 @@ WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of t
|
|||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Completed router resource preassignment. Real time: 8 secs
|
||||
Completed router resource preassignment. Real time: 6 secs
|
||||
|
||||
Start NBR router at 06:20:59 08/17/21
|
||||
Start NBR router at 01:19:22 10/09/21
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
|
@ -172,53 +171,53 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 06:20:59 08/17/21
|
||||
Start NBR special constraint process at 01:19:22 10/09/21
|
||||
|
||||
Start NBR section for initial routing at 06:20:59 08/17/21
|
||||
Start NBR section for initial routing at 01:19:22 10/09/21
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 8 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 06:21:00 08/17/21
|
||||
Start NBR section for normal routing at 01:19:22 10/09/21
|
||||
Level 1, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 1
|
||||
12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 2
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
|
||||
|
||||
Start NBR section for re-routing at 06:21:00 08/17/21
|
||||
Start NBR section for re-routing at 01:19:23 10/09/21
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
|
||||
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for post-routing at 06:21:00 08/17/21
|
||||
Start NBR section for post-routing at 01:19:23 10/09/21
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
|
@ -236,8 +235,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
|
|||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Total CPU time 9 secs
|
||||
Total REAL time: 10 secs
|
||||
Total CPU time 7 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 1131 routed (100.00%); 0 unrouted.
|
||||
|
||||
|
|
@ -259,8 +258,8 @@ PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
|||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 9 secs
|
||||
Total REAL time to completion: 10 secs
|
||||
Total CPU time to completion: 7 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">I/O Timing Analysis </SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
</TR>
|
||||
|
|
@ -62,15 +62,15 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2021/08/17 06:21:51</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2021/10/09 01:19:25</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
|
||||
Tue Aug 17 06:20:51 2021
|
||||
Sat Oct 09 01:19:15 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
|
|
@ -1395,7 +1395,7 @@ Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
|
||||
Tue Aug 17 06:20:51 2021
|
||||
Sat Oct 09 01:19:15 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -1405,7 +1405,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
|
||||
Tue Aug 17 06:21:01 2021
|
||||
Sat Oct 09 01:19:23 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
|
|
@ -2469,7 +2469,7 @@ Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
|
||||
Tue Aug 17 06:21:01 2021
|
||||
Sat Oct 09 01:19:24 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -2479,7 +2479,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|||
|
||||
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,m
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
--------------------------------------------------------------------------------
|
||||
Lattice Synthesis Timing Report, Version
|
||||
Tue Aug 17 06:19:46 2021
|
||||
Sat Oct 09 01:19:14 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -331,5 +331,5 @@ Timing errors: 1272 Score: 5951146
|
|||
Constraints cover 1577 paths, 335 nets, and 954 connections (77.9% coverage)
|
||||
|
||||
|
||||
Peak memory: 59748352 bytes, TRCE: 3297280 bytes, DLYMAN: 0 bytes
|
||||
Peak memory: 60768256 bytes, TRCE: 3186688 bytes, DLYMAN: 0 bytes
|
||||
CPU_TIME_REPORT: 0 secs
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice Synthesis Timing Report, Version
|
||||
Tue Aug 17 05:43:37 2021
|
||||
Sat Oct 09 01:19:14 2021
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -27,248 +27,272 @@ Report level: verbose report, limited to 3 items per constraint
|
|||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
|
||||
Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c]
|
||||
130 items scored, 125 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i4 to CmdLEDEN_545 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i4 to CmdLEDEN_545
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[4]
|
||||
LUT4 --- 0.493 C to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP Cmdn8MEGEN_546 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i4 to Cmdn8MEGEN_546
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[4]
|
||||
LUT4 --- 0.493 C to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.606ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
|
||||
|
||||
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.821ns data_path Bank_i5 to CmdLEDEN_545 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
|
||||
|
||||
Path Details: Bank_i5 to CmdLEDEN_545
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i5 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[5]
|
||||
LUT4 --- 0.493 B to Z i3734_4_lut
|
||||
Route 1 e 0.941 n4610
|
||||
LUT4 --- 0.493 B to Z i3751_4_lut
|
||||
Route 2 e 1.141 n4628
|
||||
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
|
||||
Route 4 e 1.340 n2384
|
||||
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
|
||||
Route 2 e 1.141 n4889
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
|
||||
Route 4 e 1.340 XOR8MEG_N_149
|
||||
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
|
||||
Route 1 e 0.941 n4882
|
||||
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
|
||||
Route 2 e 1.141 PHI2_N_151_enable_5
|
||||
--------
|
||||
12.821 (30.4% logic, 69.6% route), 8 logic levels.
|
||||
|
||||
Warning: 13.106 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
|
||||
Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c]
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
|
||||
120 items scored, 116 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.528ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i1 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_541 (to PHI2_c -)
|
||||
|
||||
Delay: 12.743ns (30.6% logic, 69.4% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.743ns data_path Bank_i1 to CmdEnable_541 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.528ns
|
||||
|
||||
Path Details: Bank_i1 to CmdEnable_541
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c)
|
||||
Route 2 e 1.198 Bank[1]
|
||||
LUT4 --- 0.493 B to Z i1819_2_lut
|
||||
Route 1 e 0.941 n2427
|
||||
LUT4 --- 0.493 C to Z i1857_4_lut
|
||||
Route 1 e 0.941 n2465
|
||||
LUT4 --- 0.493 A to Z i13_4_lut_adj_4
|
||||
Route 5 e 1.405 n1712
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_12
|
||||
Route 2 e 1.141 n2551
|
||||
LUT4 --- 0.493 D to Z i1827_4_lut
|
||||
Route 1 e 0.941 n2435
|
||||
LUT4 --- 0.493 B to Z i3_4_lut_adj_1
|
||||
Route 4 e 1.340 C1Submitted_N_200
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_119_enable_1
|
||||
--------
|
||||
12.743 (30.6% logic, 69.4% route), 8 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.471ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i3 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_541 (to PHI2_c -)
|
||||
|
||||
Delay: 12.686ns (30.7% logic, 69.3% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.686ns data_path Bank_i3 to CmdEnable_541 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.471ns
|
||||
|
||||
Path Details: Bank_i3 to CmdEnable_541
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[3]
|
||||
LUT4 --- 0.493 B to Z i1799_2_lut
|
||||
Route 2 e 1.141 n2407
|
||||
LUT4 --- 0.493 A to Z i1857_4_lut
|
||||
Route 1 e 0.941 n2465
|
||||
LUT4 --- 0.493 A to Z i13_4_lut_adj_4
|
||||
Route 5 e 1.405 n1712
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_12
|
||||
Route 2 e 1.141 n2551
|
||||
LUT4 --- 0.493 D to Z i1827_4_lut
|
||||
Route 1 e 0.941 n2435
|
||||
LUT4 --- 0.493 B to Z i3_4_lut_adj_1
|
||||
Route 4 e 1.340 C1Submitted_N_200
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_119_enable_1
|
||||
--------
|
||||
12.686 (30.7% logic, 69.3% route), 8 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 10.471ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK Bank_i6 (from PHI2_c +)
|
||||
Destination: FD1P3AX SP CmdEnable_541 (to PHI2_c -)
|
||||
|
||||
Delay: 12.686ns (30.7% logic, 69.3% route), 8 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
12.686ns data_path Bank_i6 to CmdEnable_541 violates
|
||||
2.500ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 2.215ns) by 10.471ns
|
||||
|
||||
Path Details: Bank_i6 to CmdEnable_541
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q Bank_i6 (from PHI2_c)
|
||||
Route 1 e 0.941 Bank[6]
|
||||
LUT4 --- 0.493 A to Z i1799_2_lut
|
||||
Route 2 e 1.141 n2407
|
||||
LUT4 --- 0.493 A to Z i1857_4_lut
|
||||
Route 1 e 0.941 n2465
|
||||
LUT4 --- 0.493 A to Z i13_4_lut_adj_4
|
||||
Route 5 e 1.405 n1712
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_12
|
||||
Route 2 e 1.141 n2551
|
||||
LUT4 --- 0.493 D to Z i1827_4_lut
|
||||
Route 1 e 0.941 n2435
|
||||
LUT4 --- 0.493 B to Z i3_4_lut_adj_1
|
||||
Route 4 e 1.340 C1Submitted_N_200
|
||||
LUT4 --- 0.493 C to Z i34_4_lut
|
||||
Route 1 e 0.941 PHI2_N_119_enable_1
|
||||
--------
|
||||
12.686 (30.7% logic, 69.3% route), 8 logic levels.
|
||||
|
||||
Warning: 13.028 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
|
||||
466 items scored, 158 timing errors detected.
|
||||
1392 items scored, 1147 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.233ns
|
||||
Error: The following path violates requirements by 10.222ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_725__i9 (from RCLK_c +)
|
||||
Destination: FD1P3IX SP n8MEGEN_557 (to RCLK_c +)
|
||||
Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
|
||||
|
||||
Delay: 7.948ns (33.3% logic, 66.7% route), 6 logic levels.
|
||||
Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
7.948ns data_path FS_725__i9 to n8MEGEN_557 violates
|
||||
15.062ns data_path FS_972__i8 to wb_adr_i4 violates
|
||||
5.000ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
|
||||
|
||||
Path Details: FS_725__i9 to n8MEGEN_557
|
||||
Path Details: FS_972__i8 to wb_adr_i4
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_725__i9 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[9]
|
||||
LUT4 --- 0.493 A to Z i1847_4_lut
|
||||
Route 1 e 0.941 n2455
|
||||
LUT4 --- 0.493 B to Z i1855_4_lut
|
||||
Route 1 e 0.941 n2463
|
||||
LUT4 --- 0.493 B to Z i14_4_lut
|
||||
Route 1 e 0.941 n2384
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_13
|
||||
Route 1 e 0.020 n2385
|
||||
MUXL5 --- 0.233 BLUT to Z i26
|
||||
Route 2 e 1.141 RCLK_c_enable_10
|
||||
L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
|
||||
Route 23 e 1.894 FS[8]
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i28_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[4]
|
||||
--------
|
||||
7.948 (33.3% logic, 66.7% route), 6 logic levels.
|
||||
15.062 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.233ns
|
||||
Error: The following path violates requirements by 10.222ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_725__i9 (from RCLK_c +)
|
||||
Destination: FD1P3IX SP LEDEN_556 (to RCLK_c +)
|
||||
Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i6 (to RCLK_c +)
|
||||
|
||||
Delay: 7.948ns (33.3% logic, 66.7% route), 6 logic levels.
|
||||
Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
7.948ns data_path FS_725__i9 to LEDEN_556 violates
|
||||
15.062ns data_path FS_972__i8 to wb_adr_i6 violates
|
||||
5.000ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
|
||||
|
||||
Path Details: FS_725__i9 to LEDEN_556
|
||||
Path Details: FS_972__i8 to wb_adr_i6
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_725__i9 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[9]
|
||||
LUT4 --- 0.493 A to Z i1847_4_lut
|
||||
Route 1 e 0.941 n2455
|
||||
LUT4 --- 0.493 B to Z i1855_4_lut
|
||||
Route 1 e 0.941 n2463
|
||||
LUT4 --- 0.493 B to Z i14_4_lut
|
||||
Route 1 e 0.941 n2384
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_13
|
||||
Route 1 e 0.020 n2385
|
||||
MUXL5 --- 0.233 BLUT to Z i26
|
||||
Route 2 e 1.141 RCLK_c_enable_10
|
||||
L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
|
||||
Route 23 e 1.894 FS[8]
|
||||
LUT4 --- 0.493 B to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i29_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[6]
|
||||
--------
|
||||
7.948 (33.3% logic, 66.7% route), 6 logic levels.
|
||||
15.062 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
|
||||
Error: The following path violates requirements by 3.233ns
|
||||
Error: The following path violates requirements by 10.216ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell name (clock net +/-)
|
||||
|
||||
Source: FD1S3AX CK FS_725__i8 (from RCLK_c +)
|
||||
Destination: FD1P3IX SP n8MEGEN_557 (to RCLK_c +)
|
||||
Source: FD1S3AX CK FS_972__i6 (from RCLK_c +)
|
||||
Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
|
||||
|
||||
Delay: 7.948ns (33.3% logic, 66.7% route), 6 logic levels.
|
||||
Delay: 15.056ns (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
7.948ns data_path FS_725__i8 to n8MEGEN_557 violates
|
||||
15.056ns data_path FS_972__i6 to wb_adr_i4 violates
|
||||
5.000ns delay constraint less
|
||||
0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
|
||||
0.160ns L_S requirement (totaling 4.840ns) by 10.216ns
|
||||
|
||||
Path Details: FS_725__i8 to n8MEGEN_557
|
||||
Path Details: FS_972__i6 to wb_adr_i4
|
||||
|
||||
Name Fanout Delay (ns) Pins Resource(Cell.Net)
|
||||
L_CO --- 0.444 CK to Q FS_725__i8 (from RCLK_c)
|
||||
Route 3 e 1.315 FS[8]
|
||||
LUT4 --- 0.493 B to Z i1821_2_lut
|
||||
Route 1 e 0.941 n2429
|
||||
LUT4 --- 0.493 C to Z i1855_4_lut
|
||||
Route 1 e 0.941 n2463
|
||||
LUT4 --- 0.493 B to Z i14_4_lut
|
||||
Route 1 e 0.941 n2384
|
||||
LUT4 --- 0.493 D to Z i3_4_lut_adj_13
|
||||
Route 1 e 0.020 n2385
|
||||
MUXL5 --- 0.233 BLUT to Z i26
|
||||
Route 2 e 1.141 RCLK_c_enable_10
|
||||
L_CO --- 0.444 CK to Q FS_972__i6 (from RCLK_c)
|
||||
Route 21 e 1.888 FS[6]
|
||||
LUT4 --- 0.493 A to Z i1_2_lut_rep_75
|
||||
Route 4 e 1.340 n4924
|
||||
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
|
||||
Route 1 e 0.941 n98
|
||||
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
|
||||
Route 2 e 1.141 n2199
|
||||
LUT4 --- 0.493 B to Z i92_4_lut
|
||||
Route 1 e 0.941 n53
|
||||
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
|
||||
Route 1 e 0.020 n1_adj_6
|
||||
MUXL5 --- 0.233 ALUT to Z i29
|
||||
Route 1 e 0.941 n14_adj_3
|
||||
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
|
||||
Route 2 e 1.141 n12_adj_8
|
||||
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
|
||||
Route 2 e 1.141 n14_adj_7
|
||||
LUT4 --- 0.493 A to Z i28_3_lut
|
||||
Route 1 e 0.941 wb_adr_7__N_60[4]
|
||||
--------
|
||||
7.948 (33.3% logic, 66.7% route), 6 logic levels.
|
||||
15.056 (30.7% logic, 69.3% route), 10 logic levels.
|
||||
|
||||
Warning: 8.233 ns is the maximum delay for this constraint.
|
||||
Warning: 15.222 ns is the maximum delay for this constraint.
|
||||
|
||||
|
||||
<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
|
||||
|
|
@ -278,16 +302,16 @@ Constraint | Constraint| Actual|Levels
|
|||
--------------------------------------------------------------------------------
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk3 [get_nets nCCAS_c] | -| -| 0
|
||||
clk3 [get_nets PHI2_c] | 5.000 ns| 26.212 ns| 8 *
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk2 [get_nets nCRAS_c] | -| -| 0
|
||||
clk2 [get_nets nCCAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk1 [get_nets PHI2_c] | 5.000 ns| 26.056 ns| 8 *
|
||||
clk1 [get_nets nCRAS_c] | -| -| 0
|
||||
| | |
|
||||
create_clock -period 5.000000 -name | | |
|
||||
clk0 [get_nets RCLK_c] | 5.000 ns| 8.233 ns| 6 *
|
||||
clk0 [get_nets RCLK_c] | 5.000 ns| 15.222 ns| 10 *
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -297,39 +321,13 @@ clk0 [get_nets RCLK_c] | 5.000 ns| 8.233 ns| 6 *
|
|||
--------------------------------------------------------------------------------
|
||||
Critical Nets | Loads| Errors| % of total
|
||||
--------------------------------------------------------------------------------
|
||||
n1712 | 5| 104| 37.96%
|
||||
n14 | 16| 200| 15.72%
|
||||
| | |
|
||||
n2465 | 1| 52| 18.98%
|
||||
n12_adj_8 | 2| 198| 15.57%
|
||||
| | |
|
||||
n2251 | 1| 41| 14.96%
|
||||
n14_adj_3 | 1| 183| 14.39%
|
||||
| | |
|
||||
n2551 | 2| 40| 14.60%
|
||||
| | |
|
||||
n2250 | 1| 39| 14.23%
|
||||
| | |
|
||||
n2252 | 1| 39| 14.23%
|
||||
| | |
|
||||
XOR8MEG_N_117 | 3| 34| 12.41%
|
||||
| | |
|
||||
n2249 | 1| 33| 12.04%
|
||||
| | |
|
||||
n2253 | 1| 33| 12.04%
|
||||
| | |
|
||||
C1Submitted_N_200 | 4| 32| 11.68%
|
||||
| | |
|
||||
n2379 | 2| 32| 11.68%
|
||||
| | |
|
||||
n2435 | 1| 32| 11.68%
|
||||
| | |
|
||||
RCLK_c_enable_10 | 2| 30| 10.95%
|
||||
| | |
|
||||
n2384 | 1| 30| 10.95%
|
||||
| | |
|
||||
n2385 | 1| 30| 10.95%
|
||||
| | |
|
||||
n2407 | 2| 28| 10.22%
|
||||
| | |
|
||||
n2453 | 2| 28| 10.22%
|
||||
n14_adj_7 | 2| 176| 13.84%
|
||||
| | |
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -337,12 +335,12 @@ n2453 | 2| 28| 10.22%
|
|||
<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 274 Score: 1700966
|
||||
Timing errors: 1272 Score: 5951146
|
||||
|
||||
Constraints cover 587 paths, 177 nets, and 436 connections (66.4% coverage)
|
||||
Constraints cover 1577 paths, 335 nets, and 954 connections (77.9% coverage)
|
||||
|
||||
|
||||
Peak memory: 55074816 bytes, TRCE: 434176 bytes, DLYMAN: 0 bytes
|
||||
Peak memory: 60768256 bytes, TRCE: 3186688 bytes, DLYMAN: 0 bytes
|
||||
CPU_TIME_REPORT: 0 secs
|
||||
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -29,9 +29,9 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.0.240.2
|
||||
// Written on Tue Aug 17 06:21:03 2021
|
||||
// Written on Sat Oct 09 01:19:25 2021
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
|
||||
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 17 06:19:45 2021
|
||||
Sat Oct 09 01:19:13 2021
|
||||
|
||||
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
|
||||
|
||||
Synthesis options:
|
||||
The -a option is MachXO2.
|
||||
|
|
@ -61,11 +61,11 @@ ROM style = auto
|
|||
RAM style = auto
|
||||
The -comp option is FALSE.
|
||||
The -syn option is FALSE.
|
||||
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
|
||||
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
|
||||
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
|
||||
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
|
||||
-sdc option: SDC file input not used.
|
||||
-lpf option: Output file option is ON.
|
||||
|
|
@ -76,15 +76,15 @@ Technology check ok...
|
|||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Compile design.
|
||||
Compile Design Begin
|
||||
Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
|
||||
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Top module name (Verilog): RAM2GS
|
||||
INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
|
||||
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
|
||||
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
|
||||
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
|
||||
INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
|
||||
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
|
||||
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
|
|
@ -264,8 +264,8 @@ clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
|
|||
2 constraints not met.
|
||||
|
||||
|
||||
Peak Memory Usage: 57.273 MB
|
||||
Peak Memory Usage: 58.262 MB
|
||||
|
||||
--------------------------------------------------------------
|
||||
Elapsed CPU time for LSE flow : 0.952 secs
|
||||
Elapsed CPU time for LSE flow : 0.813 secs
|
||||
--------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -14,10 +14,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Tue Aug 17 06:19:45 2021
|
||||
Sat Oct 09 01:19:13 2021
|
||||
|
||||
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
|
||||
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
|
||||
|
||||
Synthesis options:
|
||||
The -a option is MachXO2.
|
||||
|
|
@ -70,11 +70,11 @@ ROM style = auto
|
|||
RAM style = auto
|
||||
The -comp option is FALSE.
|
||||
The -syn option is FALSE.
|
||||
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
|
||||
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
|
||||
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
|
||||
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
|
||||
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
|
||||
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
|
||||
-sdc option: SDC file input not used.
|
||||
-lpf option: Output file option is ON.
|
||||
|
|
@ -85,15 +85,15 @@ Technology check ok...
|
|||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Compile design.
|
||||
Compile Design Begin
|
||||
Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
|
||||
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
|
||||
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
|
||||
Top module name (Verilog): RAM2GS
|
||||
INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
|
||||
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
|
||||
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
|
||||
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
|
||||
INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
|
||||
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
|
||||
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
|
||||
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
|
||||
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
|
||||
|
|
@ -273,10 +273,10 @@ clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
|
|||
2 constraints not met.
|
||||
|
||||
|
||||
Peak Memory Usage: 57.273 MB
|
||||
Peak Memory Usage: 58.262 MB
|
||||
|
||||
--------------------------------------------------------------
|
||||
Elapsed CPU time for LSE flow : 0.952 secs
|
||||
Elapsed CPU time for LSE flow : 0.813 secs
|
||||
--------------------------------------------------------------
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,350 +1,350 @@
|
|||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
|
||||
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
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LSE_CPS_ID_130 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_131 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_132 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_133 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_134 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_135 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_136 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_137 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_138 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_139 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_140 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_141 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_142 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_143 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_144 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_145 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_146 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_149 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:126[9] 130[5]"
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LSE_CPS_ID_150 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
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LSE_CPS_ID_151 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
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LSE_CPS_ID_153 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
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LSE_CPS_ID_154 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:206[26:30]"
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LSE_CPS_ID_155 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_156 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
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LSE_CPS_ID_157 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
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LSE_CPS_ID_158 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:225[8:20]"
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LSE_CPS_ID_159 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
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LSE_CPS_ID_160 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_161 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
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LSE_CPS_ID_162 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:225[8:20]"
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LSE_CPS_ID_163 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
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LSE_CPS_ID_164 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
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LSE_CPS_ID_165 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:115[9] 117[5]"
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LSE_CPS_ID_166 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_167 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_168 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_169 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_170 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:59[14:16]"
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LSE_CPS_ID_171 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_172 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_173 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_174 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_175 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:225[8:20]"
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LSE_CPS_ID_176 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:97[9] 112[5]"
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LSE_CPS_ID_177 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
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LSE_CPS_ID_178 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
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LSE_CPS_ID_179 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
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LSE_CPS_ID_180 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_181 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
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LSE_CPS_ID_182 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
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LSE_CPS_ID_183 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
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LSE_CPS_ID_184 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
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LSE_CPS_ID_185 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_186 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_187 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
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LSE_CPS_ID_188 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_189 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
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LSE_CPS_ID_190 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
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LSE_CPS_ID_191 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_192 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
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LSE_CPS_ID_193 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
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LSE_CPS_ID_194 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_195 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:692[20:26]"
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LSE_CPS_ID_196 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:90[9] 94[5]"
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LSE_CPS_ID_197 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_198 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
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LSE_CPS_ID_199 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
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LSE_CPS_ID_200 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:267[12] 276[6]"
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LSE_CPS_ID_201 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
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LSE_CPS_ID_202 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
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LSE_CPS_ID_203 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_204 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
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LSE_CPS_ID_205 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
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LSE_CPS_ID_206 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_207 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_208 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_209 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_210 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
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LSE_CPS_ID_211 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
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LSE_CPS_ID_213 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_214 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
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LSE_CPS_ID_215 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
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LSE_CPS_ID_217 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:255[11:15]"
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LSE_CPS_ID_218 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:351[9] 730[5]"
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LSE_CPS_ID_219 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_220 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
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LSE_CPS_ID_221 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
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LSE_CPS_ID_222 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[12] 729[6]"
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LSE_CPS_ID_223 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_224 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
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LSE_CPS_ID_225 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_226 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:280[9] 315[5]"
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LSE_CPS_ID_227 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
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LSE_CPS_ID_228 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
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LSE_CPS_ID_229 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_230 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:522[30:46]"
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LSE_CPS_ID_231 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
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LSE_CPS_ID_232 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:522[30:46]"
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LSE_CPS_ID_233 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
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LSE_CPS_ID_234 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
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LSE_CPS_ID_235 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:72[15:31]"
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LSE_CPS_ID_236 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
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LSE_CPS_ID_237 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_238 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
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LSE_CPS_ID_239 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
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LSE_CPS_ID_240 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:648[30:46]"
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LSE_CPS_ID_241 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
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LSE_CPS_ID_242 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[12] 729[6]"
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LSE_CPS_ID_243 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:522[30:46]"
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LSE_CPS_ID_244 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[12] 729[6]"
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LSE_CPS_ID_245 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_246 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
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LSE_CPS_ID_247 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
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LSE_CPS_ID_248 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
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LSE_CPS_ID_249 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
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LSE_CPS_ID_250 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_251 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_252 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[12] 729[6]"
|
||||
LSE_CPS_ID_253 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_254 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_255 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:464[4] 521[11]"
|
||||
LSE_CPS_ID_256 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:267[12] 276[6]"
|
||||
LSE_CPS_ID_257 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_258 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_259 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_260 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_261 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_262 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_263 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_264 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_265 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_266 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_267 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_268 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_269 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_270 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:304[17:31]"
|
||||
LSE_CPS_ID_271 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:72[15:31]"
|
||||
LSE_CPS_ID_272 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_273 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:72[15:31]"
|
||||
LSE_CPS_ID_274 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_275 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_276 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_277 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:224[12] 276[6]"
|
||||
LSE_CPS_ID_278 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:461[30:46]"
|
||||
LSE_CPS_ID_279 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_280 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_281 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:178[13] 223[7]"
|
||||
LSE_CPS_ID_282 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_283 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:83[9] 87[5]"
|
||||
LSE_CPS_ID_284 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[30:46]"
|
||||
LSE_CPS_ID_285 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:91[22:51]"
|
||||
LSE_CPS_ID_286 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_287 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:19[12:17]"
|
||||
LSE_CPS_ID_288 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:139[9] 277[5]"
|
||||
LSE_CPS_ID_289 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:222[16:37]"
|
||||
LSE_CPS_ID_290 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_291 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_292 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_293 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_294 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_295 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_296 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_297 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_298 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_299 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_300 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_301 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_302 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_303 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_304 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_305 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_306 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[12] 729[6]"
|
||||
LSE_CPS_ID_307 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_308 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_309 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:12[15:34]"
|
||||
LSE_CPS_ID_310 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:135[40:46]"
|
||||
LSE_CPS_ID_311 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_312 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:178[13] 223[7]"
|
||||
LSE_CPS_ID_313 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:224[12] 276[6]"
|
||||
LSE_CPS_ID_314 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:525[4] 647[11]"
|
||||
LSE_CPS_ID_315 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_316 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:301[7:24]"
|
||||
LSE_CPS_ID_317 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_318 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:135[40:46]"
|
||||
LSE_CPS_ID_319 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
|
||||
LSE_CPS_ID_320 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:224[12] 276[6]"
|
||||
LSE_CPS_ID_321 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
|
||||
LSE_CPS_ID_322 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
|
||||
LSE_CPS_ID_323 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_324 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_325 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
|
||||
LSE_CPS_ID_326 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_327 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_328 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_329 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:187[13] 223[7]"
|
||||
LSE_CPS_ID_330 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_331 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:247[14] 254[8]"
|
||||
LSE_CPS_ID_332 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_333 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
|
||||
LSE_CPS_ID_334 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_335 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_336 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:359[12] 729[6]"
|
||||
LSE_CPS_ID_337 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_338 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:187[13] 223[7]"
|
||||
LSE_CPS_ID_339 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:224[12] 276[6]"
|
||||
LSE_CPS_ID_340 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
|
||||
LSE_CPS_ID_341 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:78[13:15]"
|
||||
LSE_CPS_ID_342 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:57[17:46]"
|
||||
LSE_CPS_ID_343 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_344 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_345 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_346 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_347 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
|
||||
LSE_CPS_ID_348 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
|
||||
LSE_CPS_ID_349 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:7[8:12]"
|
||||
LSE_CPS_ID_350 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:15[15:20]"
|
||||
|
|
|
|||
|
|
@ -340,13 +340,17 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
|
||||
// Submit command
|
||||
if (CMDWR & CmdEnable) begin
|
||||
if (Din[7:4]==4'h0) begin
|
||||
if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin
|
||||
// LCMXO, LCMXO2, iCE40 ignore this unless Din[2] and Din[1] set
|
||||
// MAX w/ LED ignores this unless Din[2] set
|
||||
// MAX w/o LED does not check Din[3:1].
|
||||
XOR8MEG <= Din[0];
|
||||
end else if (Din[7:4]==4'h1) begin
|
||||
CmdLEDEN <= ~Din[1];
|
||||
Cmdn8MEGEN <= ~Din[0];
|
||||
CmdSubmitted <= 1'b1;
|
||||
end else if (Din[7:4]==4'h2 && Din[3]==1'b0) begin
|
||||
end else if (Din[7:4]==4'h2) begin
|
||||
// MAX commands
|
||||
CmdLEDEN <= LEDEN;
|
||||
Cmdn8MEGEN <= n8MEGEN;
|
||||
CmdUFMErase <= Din[3];
|
||||
|
|
@ -354,6 +358,15 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
CmdDRCLK <= Din[1];
|
||||
CmdDRDIn <= Din[0];
|
||||
CmdSubmitted <= 1'b1;
|
||||
end else if (Din[7:4]==4'h3 && ~Din[3]) begin
|
||||
// Reserved for LCMXO2 commands
|
||||
// Din[1] - Shift when high, execute when low
|
||||
// Din[0] - Shift data
|
||||
end else if (Din[7:4]==4'h3 && Din[3]) begin
|
||||
// Reserved for SPI (LCMXO, iCE40) commands
|
||||
// Din[2] - CS
|
||||
// Din[1] - SCK
|
||||
// Din[0] - SDI
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue