2023-08-20 11:10:11 +00:00
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2023-08-15 09:05:47 +00:00
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Starting: parse design source files
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(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
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2023-08-20 11:10:11 +00:00
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(VERI-1482) Analyzing Verilog file 'Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v'
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(VERI-1482) Analyzing Verilog file 'Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v'
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INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
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INFO - Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-614,10) (VERI-9000) elaborating module 'RAM2GS'
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INFO - Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
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2023-08-17 01:04:05 +00:00
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INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
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INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
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INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
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2023-08-15 09:05:47 +00:00
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Done: design load finished with (0) errors, and (0) warnings
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</PRE></BODY></HTML>
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