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RAM2GS
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This commit is contained in:
Zane Kaminski 2023-08-13 05:16:51 -04:00
parent 43042eb1ee
commit 065ad56ccc
70 changed files with 830 additions and 828 deletions
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CPLD/MAXII/db/RAM2GS.asm.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691914219957 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691914219957 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:10:19 2023 " "Processing started: Sun Aug 13 04:10:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691914219957 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691914219957 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691914219957 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691914220207 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691914220223 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691914220223 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691914220363 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:10:20 2023 " "Processing ended: Sun Aug 13 04:10:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691914220363 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691914220363 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691914220363 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691914220363 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916642301 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916642301 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:42 2023 " "Processing started: Sun Aug 13 04:50:42 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916642301 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691916642301 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691916642301 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691916642519 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691916642535 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691916642535 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916642660 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:42 2023 " "Processing ended: Sun Aug 13 04:50:42 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916642660 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916642660 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916642660 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691916642660 ""}

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CPLD/MAXII/db/RAM2GS.db_info
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Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Version_Index = 503488000
Creation_Time = Sun Aug 13 04:09:48 2023
Creation_Time = Sun Aug 13 04:50:24 2023

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CPLD/MAXII/db/RAM2GS.fit.qmsg
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691914217113 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691914217113 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691914217113 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691914217144 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691914217144 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691914217176 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691914217176 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691914217347 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691914217347 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691914217473 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691914217473 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691914217488 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691914217488 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691914217488 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691914217488 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691914217504 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691914217504 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691914217504 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691914217520 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691914217520 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691914217551 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691914217582 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691914217582 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691914217582 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691914217582 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914217613 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691914217644 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691914217785 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914217926 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691914217941 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691914218301 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914218301 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691914218332 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "17 " "Router estimated average interconnect usage is 17% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691914218488 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691914218488 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691914218629 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691914218629 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914218629 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691914218660 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691914218660 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691914218691 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691914218754 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691914218785 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:10:18 2023 " "Processing ended: Sun Aug 13 04:10:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691914218785 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691914218785 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691914218785 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691914218785 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691916639926 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691916639926 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691916639926 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916639973 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916639973 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691916639988 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691916640004 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691916640098 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691916640144 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691916640160 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691916640160 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691916640160 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691916640160 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916640160 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916640160 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916640160 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691916640176 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691916640191 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691916640223 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691916640223 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691916640223 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691916640223 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640238 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691916640254 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691916640332 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640441 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691916640441 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691916640816 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640816 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691916640832 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "22 " "Router estimated average interconnect usage is 22% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691916640957 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691916640957 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691916641098 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691916641098 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916641098 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691916641113 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916641113 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691916641144 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691916641176 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:41 2023 " "Processing ended: Sun Aug 13 04:50:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691916641207 ""}

2
CPLD/MAXII/db/RAM2GS.hier_info
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@ -78,11 +78,11 @@ Din[0] => Equal15.IN4
Din[0] => Cmdn8MEGEN.DATAB
Din[1] => XOR8MEG.IN1
Din[1] => CmdDRCLK.DATAB
Din[1] => CmdLEDEN.DATAB
Din[1] => WRD[1].DATAIN
Din[1] => Bank[1].DATAIN
Din[1] => Equal14.IN7
Din[1] => Equal15.IN7
Din[1] => CmdLEDEN.DATAB
Din[2] => CmdUFMPrgm.DATAB
Din[2] => WRD[2].DATAIN
Din[2] => Bank[2].DATAIN

BIN
CPLD/MAXII/db/RAM2GS.hif
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BIN
CPLD/MAXII/db/RAM2GS.map.cdb
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BIN
CPLD/MAXII/db/RAM2GS.map.hdb
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54
CPLD/MAXII/db/RAM2GS.map.qmsg
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@ -1,27 +1,27 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691914206145 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691914206145 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:10:06 2023 " "Processing started: Sun Aug 13 04:10:06 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691914206145 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914206145 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914206145 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691914206473 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691914206473 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691914214816 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691914214832 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914214832 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691914214879 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691914214879 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691914214879 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691914214879 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914214879 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691914214926 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691914214941 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691914214941 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691914214941 "|RAM2GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691914214988 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691914215035 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691914215379 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691914215473 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691914215473 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691914215473 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691914215473 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691914215473 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691914215473 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914215582 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4701 " "Peak virtual memory: 4701 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691914215598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:10:15 2023 " "Processing ended: Sun Aug 13 04:10:15 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691914215598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691914215598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691914215598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691914215598 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916629644 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916629644 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:29 2023 " "Processing started: Sun Aug 13 04:50:29 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916629644 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916629644 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916629644 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691916629957 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691916629957 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691916638098 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916638098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916638098 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916638129 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916638129 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916638129 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916638129 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916638129 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691916638160 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916638160 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916638160 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916638160 "|RAM2GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916638176 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916638192 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691916638488 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691916638488 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691916638488 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691916638488 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691916638488 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691916638488 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916638535 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4700 " "Peak virtual memory: 4700 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916638551 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:38 2023 " "Processing ended: Sun Aug 13 04:50:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916638551 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916638551 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916638551 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916638551 ""}

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@ -1,25 +1,25 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691914221676 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691914221676 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:10:21 2023 " "Processing started: Sun Aug 13 04:10:21 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691914221676 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691914221676 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691914221676 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691914221785 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691914221926 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691914221926 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914221957 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914221957 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691914222004 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691914222144 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691914222196 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914222197 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691914222198 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691914222198 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691914222202 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691914222205 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691914222220 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.193 -97.128 PHI2 " " -9.193 -97.128 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.818 -246.083 RCLK " " -8.818 -246.083 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.245 -5.591 nCRAS " " -1.245 -5.591 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222223 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914222223 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.888 " "Worst-case hold slack is -16.888" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.888 -16.888 DRCLK " " -16.888 -16.888 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.289 -16.289 ARCLK " " -16.289 -16.289 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.679 -2.377 PHI2 " " -0.679 -2.377 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.104 -0.104 nCRAS " " -0.104 -0.104 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.157 0.000 RCLK " " 1.157 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222239 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914222239 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691914222239 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691914222239 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691914222254 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691914222254 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691914222332 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691914222348 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691914222348 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4677 " "Peak virtual memory: 4677 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691914222410 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:10:22 2023 " "Processing ended: Sun Aug 13 04:10:22 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691914222410 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691914222410 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691914222410 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691914222410 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916643769 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916643769 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:43 2023 " "Processing started: Sun Aug 13 04:50:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916643769 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916643769 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916643769 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691916643863 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691916643988 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691916643988 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644019 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644019 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691916644066 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691916644207 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691916644254 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644254 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691916644270 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691916644270 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691916644270 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.541 -253.391 RCLK " " -8.541 -253.391 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.503 -92.361 PHI2 " " -8.503 -92.361 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.149 -5.683 nCRAS " " -1.149 -5.683 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -17.185 " "Worst-case hold slack is -17.185" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.185 -17.185 DRCLK " " -17.185 -17.185 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.694 -16.694 ARCLK " " -16.694 -16.694 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.367 -1.096 nCRAS " " -0.367 -1.096 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.107 -0.165 PHI2 " " -0.107 -0.165 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.163 0.000 RCLK " " 1.163 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916644301 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644301 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691916644379 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916644395 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916644395 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4677 " "Peak virtual memory: 4677 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:44 2023 " "Processing ended: Sun Aug 13 04:50:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691916644441 ""}

BIN
CPLD/MAXII/db/RAM2GS.sta.rdb
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Binary file not shown.

BIN
CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb
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Binary file not shown.

10
CPLD/MAXII/db/RAM2GS.tmw_info
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@ -1,6 +1,6 @@
start_full_compilation:s:00:00:18
start_analysis_synthesis:s:00:00:11-start_full_compilation
start_full_compilation:s:00:00:16
start_analysis_synthesis:s:00:00:10-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:03-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:03-start_full_compilation
start_fitter:s:00:00:02-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:02-start_full_compilation

BIN
CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt
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16
CPLD/MAXII/output_files/RAM2GS.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for RAM2GS
Sun Aug 13 04:10:20 2023
Sun Aug 13 04:50:42 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Aug 13 04:10:20 2023 ;
; Assembler Status ; Successful - Sun Aug 13 04:50:42 2023 ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
+----------------+---------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------------------------------+
; JTAG usercode ; 0x001743AE ;
; Checksum ; 0x0017462E ;
; JTAG usercode ; 0x00171C35 ;
; Checksum ; 0x00172025 ;
+----------------+---------------------------------------------------------------------------------+
@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sun Aug 13 04:10:19 2023
Info: Processing started: Sun Aug 13 04:50:42 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4662 megabytes
Info: Processing ended: Sun Aug 13 04:10:20 2023
Info: Elapsed time: 00:00:01
Info: Peak virtual memory: 4663 megabytes
Info: Processing ended: Sun Aug 13 04:50:42 2023
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

2
CPLD/MAXII/output_files/RAM2GS.done
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@ -1 +1 @@
Sun Aug 13 04:10:23 2023
Sun Aug 13 04:50:45 2023

147
CPLD/MAXII/output_files/RAM2GS.fit.rpt
View File

@ -1,5 +1,5 @@
Fitter report for RAM2GS
Sun Aug 13 04:10:18 2023
Sun Aug 13 04:50:41 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Sun Aug 13 04:10:18 2023 ;
; Fitter Status ; Successful - Sun Aug 13 04:50:41 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
@ -130,13 +130,13 @@ https://fpgasoftware.intel.com/eula.
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.04 ;
; Average used ; 1.05 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.7% ;
; Processors 3-4 ; 1.2% ;
; Processor 2 ; 1.8% ;
; Processors 3-4 ; 1.5% ;
+----------------------------+-------------+
@ -172,7 +172,7 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 98 / 240 ( 41 % ) ;
; Total LABs ; 22 / 24 ( 92 % ) ;
; Total LABs ; 23 / 24 ( 96 % ) ;
; Logic elements in carry chains ; 17 ;
; Virtual pins ; 0 ;
; I/O pins ; 63 / 80 ( 79 % ) ;
@ -186,8 +186,8 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; Global signals ; 4 ;
; -- Global clocks ; 4 / 4 ( 100 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 20.4% / 22.3% / 18.4% ;
; Peak interconnect usage (total/H/V) ; 20.4% / 22.3% / 18.4% ;
; Average interconnect usage (total/H/V) ; 26.5% / 24.7% / 28.5% ;
; Peak interconnect usage (total/H/V) ; 26.5% / 24.7% / 28.5% ;
; Maximum fan-out ; 55 ;
; Highest non-global fan-out ; 41 ;
; Total fan-out ; 661 ;
@ -259,10 +259,10 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/
; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -505,16 +505,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; CmdDRDIn~2 ; LC_X6_Y1_N1 ; 4 ; Clock enable ; no ; -- ; -- ;
; CmdLEDEN~1 ; LC_X6_Y1_N3 ; 3 ; Clock enable ; no ; -- ; -- ;
; DRDIn~1 ; LC_X2_Y1_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK1 ;
; CmdDRDIn~2 ; LC_X5_Y3_N9 ; 4 ; Clock enable ; no ; -- ; -- ;
; CmdLEDEN~1 ; LC_X5_Y3_N3 ; 3 ; Clock enable ; no ; -- ; -- ;
; DRDIn~1 ; LC_X6_Y4_N1 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ;
; Ready ; LC_X7_Y2_N7 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; always8~7 ; LC_X6_Y2_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
; comb~0 ; LC_X3_Y4_N0 ; 8 ; Output enable ; no ; -- ; -- ;
; Ready ; LC_X6_Y2_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; always8~7 ; LC_X7_Y3_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
; comb~0 ; LC_X7_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ;
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ;
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ;
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
@ -523,10 +523,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+----------------------+------------------+
; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK1 ;
; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK3 ;
; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ;
; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ;
; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK3 ;
; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK1 ;
+-------+----------+---------+----------------------+------------------+
@ -535,64 +535,64 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 126 / 784 ( 16 % ) ;
; Direct links ; 61 / 888 ( 7 % ) ;
; C4s ; 175 / 784 ( 22 % ) ;
; Direct links ; 36 / 888 ( 4 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 14 / 32 ( 44 % ) ;
; LUT chains ; 20 / 216 ( 9 % ) ;
; Local interconnects ; 264 / 888 ( 30 % ) ;
; R4s ; 129 / 704 ( 18 % ) ;
; Local interconnects ; 274 / 888 ( 31 % ) ;
; R4s ; 148 / 704 ( 21 % ) ;
+-----------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 7.95) ; Number of LABs (Total = 22) ;
; Number of Logic Elements (Average = 7.61) ; Number of LABs (Total = 23) ;
+--------------------------------------------+------------------------------+
; 1 ; 2 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 13 ;
; 9 ; 5 ;
; 10 ; 9 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.36) ; Number of LABs (Total = 22) ;
; LAB-wide Signals (Average = 1.43) ; Number of LABs (Total = 23) ;
+------------------------------------+------------------------------+
; 1 Clock ; 15 ;
; 1 Clock enable ; 3 ;
; 1 Sync. clear ; 3 ;
; 1 Sync. load ; 2 ;
; 2 Clocks ; 7 ;
; 1 Clock ; 17 ;
; 1 Clock enable ; 2 ;
; 1 Sync. clear ; 5 ;
; 1 Sync. load ; 3 ;
; 2 Clocks ; 6 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.23) ; Number of LABs (Total = 22) ;
; Number of Signals Sourced (Average = 7.87) ; Number of LABs (Total = 23) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 9 ;
; 11 ; 3 ;
; 8 ; 1 ;
; 9 ; 5 ;
; 10 ; 8 ;
; 11 ; 1 ;
; 12 ; 1 ;
+---------------------------------------------+------------------------------+
@ -600,18 +600,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.64) ; Number of LABs (Total = 22) ;
; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 23) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 1 ; 3 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 5 ;
; 6 ; 0 ;
; 7 ; 4 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 3 ;
; 9 ; 2 ;
; 10 ; 3 ;
+-------------------------------------------------+------------------------------+
@ -619,26 +619,27 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 9.73) ; Number of LABs (Total = 22) ;
; Number of Distinct Inputs (Average = 9.74) ; Number of LABs (Total = 23) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 6 ; 3 ;
; 7 ; 3 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 3 ;
; 8 ; 2 ;
; 9 ; 0 ;
; 10 ; 3 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 16 ; 3 ;
; 17 ; 2 ;
; 16 ; 2 ;
; 17 ; 1 ;
; 18 ; 1 ;
+---------------------------------------------+------------------------------+
@ -661,8 +662,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------+----------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
; I/O ; RCLK ; 3.3 ;
; I/O ; nCRAS ; 3.0 ;
; I/O ; nCRAS ; 4.0 ;
; I/O ; RCLK ; 3.7 ;
+-----------------+----------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
@ -673,9 +674,9 @@ This will disable optimization of problematic paths and expose them for further
+-----------------+----------------------+-------------------+
; Source Register ; Destination Register ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
; nCCAS ; CBR ; 3.041 ;
; nCRAS ; RASr ; 1.214 ;
; PHI2 ; PHI2r ; 1.107 ;
; nCCAS ; CBR ; 4.013 ;
; PHI2 ; PHI2r ; 1.523 ;
; nCRAS ; RASr ; 0.916 ;
+-----------------+----------------------+-------------------+
Note: This table only shows the top 3 path(s) that have the largest delay added for hold.
@ -736,20 +737,20 @@ Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 17% of the available device resources
Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170195): Router estimated average interconnect usage is 22% of the available device resources
Info (170196): Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.26 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.25 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 5345 megabytes
Info: Processing ended: Sun Aug 13 04:10:18 2023
Info: Processing ended: Sun Aug 13 04:50:41 2023
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02
Info: Total CPU time (on all processors): 00:00:03
+----------------------------+

2
CPLD/MAXII/output_files/RAM2GS.fit.summary
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@ -1,4 +1,4 @@
Fitter Status : Successful - Sun Aug 13 04:10:18 2023
Fitter Status : Successful - Sun Aug 13 04:50:41 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS

16
CPLD/MAXII/output_files/RAM2GS.flow.rpt
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@ -1,5 +1,5 @@
Flow report for RAM2GS
Sun Aug 13 04:10:22 2023
Sun Aug 13 04:50:44 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Sun Aug 13 04:10:20 2023 ;
; Flow Status ; Successful - Sun Aug 13 04:50:42 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 08/13/2023 04:10:06 ;
; Start date & time ; 08/13/2023 04:50:29 ;
; Main task ; Compilation ;
; Revision Name ; RAM2GS ;
+-------------------+---------------------+
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 207120313862967.169191420613564 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.169191662914016 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4701 MB ; 00:00:23 ;
; Fitter ; 00:00:02 ; 1.0 ; 5345 MB ; 00:00:02 ;
; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ;
; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4700 MB ; 00:00:23 ;
; Fitter ; 00:00:02 ; 1.0 ; 5345 MB ; 00:00:03 ;
; Assembler ; 00:00:00 ; 1.0 ; 4662 MB ; 00:00:00 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 4677 MB ; 00:00:01 ;
; Total ; 00:00:13 ; -- ; -- ; 00:00:26 ;
; Total ; 00:00:12 ; -- ; -- ; 00:00:27 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

10
CPLD/MAXII/output_files/RAM2GS.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for RAM2GS
Sun Aug 13 04:10:15 2023
Sun Aug 13 04:50:38 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:10:15 2023 ;
; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:50:38 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
@ -270,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sun Aug 13 04:10:06 2023
Info: Processing started: Sun Aug 13 04:50:29 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
@ -301,8 +301,8 @@ Info (21057): Implemented 248 device resources after synthesis - the final resou
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 4701 megabytes
Info: Processing ended: Sun Aug 13 04:10:15 2023
Info: Peak virtual memory: 4700 megabytes
Info: Processing ended: Sun Aug 13 04:50:38 2023
Info: Elapsed time: 00:00:09
Info: Total CPU time (on all processors): 00:00:23

2
CPLD/MAXII/output_files/RAM2GS.map.summary
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@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Sun Aug 13 04:10:15 2023
Analysis & Synthesis Status : Successful - Sun Aug 13 04:50:38 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS

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CPLD/MAXII/output_files/RAM2GS.pof
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929
CPLD/MAXII/output_files/RAM2GS.sta.rpt
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38
CPLD/MAXII/output_files/RAM2GS.sta.summary
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@ -10,36 +10,36 @@ Type : Setup 'DRCLK'
Slack : -99.000
TNS : -99.000
Type : Setup 'PHI2'
Slack : -9.193
TNS : -97.128
Type : Setup 'RCLK'
Slack : -8.818
TNS : -246.083
Slack : -8.541
TNS : -253.391
Type : Setup 'PHI2'
Slack : -8.503
TNS : -92.361
Type : Setup 'nCRAS'
Slack : -1.245
TNS : -5.591
Slack : -1.149
TNS : -5.683
Type : Hold 'DRCLK'
Slack : -16.888
TNS : -16.888
Slack : -17.185
TNS : -17.185
Type : Hold 'ARCLK'
Slack : -16.289
TNS : -16.289
Type : Hold 'PHI2'
Slack : -0.679
TNS : -2.377
Slack : -16.694
TNS : -16.694
Type : Hold 'nCRAS'
Slack : -0.104
TNS : -0.104
Slack : -0.367
TNS : -1.096
Type : Hold 'PHI2'
Slack : -0.107
TNS : -0.165
Type : Hold 'RCLK'
Slack : 1.157
Slack : 1.163
TNS : 0.000
Type : Minimum Pulse Width 'ARCLK'

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14
CPLD/MAXV/db/RAM2GS.asm.qmsg
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@ -1,7 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691915194082 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915194082 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:26:33 2023 " "Processing started: Sun Aug 13 04:26:33 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915194082 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691915194082 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691915194082 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691915194348 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691915194363 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691915194379 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915194488 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:26:34 2023 " "Processing ended: Sun Aug 13 04:26:34 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915194488 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915194488 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915194488 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691915194488 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916603004 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916603004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:02 2023 " "Processing started: Sun Aug 13 04:50:02 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916603004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691916603004 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691916603004 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691916603223 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691916603254 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691916603254 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:03 2023 " "Processing ended: Sun Aug 13 04:50:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691916603363 ""}

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CPLD/MAXV/db/RAM2GS.db_info
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@ -1,3 +1,3 @@
Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Version_Index = 503488000
Creation_Time = Sun Aug 13 04:15:04 2023
Creation_Time = Sun Aug 13 04:37:09 2023

90
CPLD/MAXV/db/RAM2GS.fit.qmsg
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@ -1,45 +1,45 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691915191832 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691915191832 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691915191832 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691915191879 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691915191879 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691915191894 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691915191894 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915192004 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915192004 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915192004 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691915192004 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691915192066 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691915192066 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691915192066 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691915192066 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915192066 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691915192066 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691915192066 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691915192066 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691915192066 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915192082 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691915192082 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691915192098 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691915192129 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691915192129 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691915192129 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691915192129 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192144 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691915192160 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691915192238 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192332 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691915192348 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691915192676 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192676 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691915192691 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691915192816 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691915192816 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691915192957 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691915192957 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192957 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691915192957 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915192973 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691915192988 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691915193020 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915193057 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:26:33 2023 " "Processing ended: Sun Aug 13 04:26:33 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915193057 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915193057 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915193057 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691915193057 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691916600692 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691916600692 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691916600707 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916600739 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916600739 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691916600770 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691916600770 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916600894 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916600894 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916600894 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691916600894 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691916600941 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691916600941 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691916600941 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691916600941 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691916600941 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916600941 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916600941 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916600941 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691916600957 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691916600973 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691916600988 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691916600988 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691916601004 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691916601004 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601019 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691916601035 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691916601113 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601223 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691916601223 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691916601567 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601567 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691916601582 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691916601707 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691916601707 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691916601832 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691916601832 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601832 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691916601848 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601848 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691916601879 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691916601910 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916601941 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:01 2023 " "Processing ended: Sun Aug 13 04:50:01 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916601941 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916601941 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916601941 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691916601941 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691915181672 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915181672 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:26:21 2023 " "Processing started: Sun Aug 13 04:26:21 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915181672 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915181672 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915181672 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691915181972 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691915181972 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691915190051 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915190051 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915190051 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691915190082 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691915190082 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915190082 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915190082 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915190082 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 "|RAM2GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691915190113 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691915190129 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915190379 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691915190410 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691915190410 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691915190410 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691915190410 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691915190410 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691915190410 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915190457 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915190488 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:26:30 2023 " "Processing ended: Sun Aug 13 04:26:30 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915190488 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915190488 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915190488 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915190488 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916590238 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916590238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:49:50 2023 " "Processing started: Sun Aug 13 04:49:50 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916590238 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916590238 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916590238 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691916590566 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691916590566 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691916598863 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598863 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916598863 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916598894 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916598894 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598894 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598894 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916598894 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916598941 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916598941 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""}
{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691916599238 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691916599238 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916599285 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:49:59 2023 " "Processing ended: Sun Aug 13 04:49:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916599301 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691915195644 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915195644 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:26:35 2023 " "Processing started: Sun Aug 13 04:26:35 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915195644 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691915195644 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691915195644 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691915195754 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691915195879 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691915195879 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915195910 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915195910 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691915195957 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691915196129 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691915196160 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915196160 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915196160 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691915196160 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691915196160 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691915196176 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691915196176 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.164 -118.093 PHI2 " " -10.164 -118.093 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.387 -288.937 RCLK " " -9.387 -288.937 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.870 -7.136 nCRAS " " -2.870 -7.136 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196176 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915196176 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.578 " "Worst-case hold slack is -16.578" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.578 -16.578 DRCLK " " -16.578 -16.578 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.552 -16.552 ARCLK " " -16.552 -16.552 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.611 -0.993 PHI2 " " -0.611 -0.993 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.443 0.000 nCRAS " " 0.443 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915196191 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691915196191 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691915196191 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915196191 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915196191 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691915196254 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691915196269 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691915196269 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915196317 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:26:36 2023 " "Processing ended: Sun Aug 13 04:26:36 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915196317 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915196317 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915196317 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691915196317 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916604691 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916604691 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:04 2023 " "Processing started: Sun Aug 13 04:50:04 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916604691 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916604691 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916604691 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691916604801 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691916604942 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691916604942 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916604988 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916604988 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691916605035 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691916605223 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691916605254 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916605254 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691916605254 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691916605254 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691916605269 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691916605269 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.164 -118.093 PHI2 " " -10.164 -118.093 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.387 -288.937 RCLK " " -9.387 -288.937 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.870 -7.136 nCRAS " " -2.870 -7.136 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916605269 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.578 " "Worst-case hold slack is -16.578" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.578 -16.578 DRCLK " " -16.578 -16.578 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.552 -16.552 ARCLK " " -16.552 -16.552 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.611 -0.993 PHI2 " " -0.611 -0.993 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.443 0.000 nCRAS " " 0.443 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916605269 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916605285 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916605285 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916605285 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691916605332 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916605363 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916605363 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916605410 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:05 2023 " "Processing ended: Sun Aug 13 04:50:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916605410 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916605410 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916605410 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691916605410 ""}

BIN
CPLD/MAXV/db/RAM2GS.sta.rdb
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BIN
CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb
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8
CPLD/MAXV/db/RAM2GS.tmw_info
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@ -1,6 +1,6 @@
start_full_compilation:s:00:00:15
start_full_compilation:s:00:00:17
start_analysis_synthesis:s:00:00:10-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:02-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation
start_fitter:s:00:00:03-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:03-start_full_compilation

BIN
CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt
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10
CPLD/MAXV/output_files/RAM2GS.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for RAM2GS
Sun Aug 13 04:26:34 2023
Sun Aug 13 04:50:03 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Aug 13 04:26:34 2023 ;
; Assembler Status ; Successful - Sun Aug 13 04:50:03 2023 ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sun Aug 13 04:26:33 2023
Info: Processing started: Sun Aug 13 04:50:02 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4662 megabytes
Info: Processing ended: Sun Aug 13 04:26:34 2023
Info: Processing ended: Sun Aug 13 04:50:03 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Info: Total CPU time (on all processors): 00:00:00

2
CPLD/MAXV/output_files/RAM2GS.done
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@ -1 +1 @@
Sun Aug 13 04:26:36 2023
Sun Aug 13 04:50:06 2023

12
CPLD/MAXV/output_files/RAM2GS.fit.rpt
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@ -1,5 +1,5 @@
Fitter report for RAM2GS
Sun Aug 13 04:26:33 2023
Sun Aug 13 04:50:01 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Sun Aug 13 04:26:33 2023 ;
; Fitter Status ; Successful - Sun Aug 13 04:50:01 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
@ -136,7 +136,7 @@ https://fpgasoftware.intel.com/eula.
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.5% ;
; Processors 3-4 ; 1.3% ;
; Processors 3-4 ; 1.4% ;
+----------------------------+-------------+
@ -731,7 +731,7 @@ Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@ -750,8 +750,8 @@ Warning (169174): The Reserve All Unused Pins setting has not been specified, an
Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 5345 megabytes
Info: Processing ended: Sun Aug 13 04:26:33 2023
Info: Elapsed time: 00:00:02
Info: Processing ended: Sun Aug 13 04:50:01 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:02

2
CPLD/MAXV/output_files/RAM2GS.fit.summary
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@ -1,4 +1,4 @@
Fitter Status : Successful - Sun Aug 13 04:26:33 2023
Fitter Status : Successful - Sun Aug 13 04:50:01 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS

12
CPLD/MAXV/output_files/RAM2GS.flow.rpt
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@ -1,5 +1,5 @@
Flow report for RAM2GS
Sun Aug 13 04:26:36 2023
Sun Aug 13 04:50:05 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Sun Aug 13 04:26:34 2023 ;
; Flow Status ; Successful - Sun Aug 13 04:50:03 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 08/13/2023 04:26:21 ;
; Start date & time ; 08/13/2023 04:49:50 ;
; Main task ; Compilation ;
; Revision Name ; RAM2GS ;
+-------------------+---------------------+
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------+---------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 207120313862967.169191518110472 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.169191659008924 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
@ -85,10 +85,10 @@ https://fpgasoftware.intel.com/eula.
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4702 MB ; 00:00:22 ;
; Fitter ; 00:00:02 ; 1.0 ; 5345 MB ; 00:00:02 ;
; Fitter ; 00:00:01 ; 1.0 ; 5345 MB ; 00:00:02 ;
; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ;
; Total ; 00:00:13 ; -- ; -- ; 00:00:25 ;
; Total ; 00:00:12 ; -- ; -- ; 00:00:25 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

10
CPLD/MAXV/output_files/RAM2GS.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for RAM2GS
Sun Aug 13 04:26:30 2023
Sun Aug 13 04:49:59 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:26:30 2023 ;
; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:49:59 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
@ -152,7 +152,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------+-----------------+----------------------------------------+----------------------------------------------------------+---------+
; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v ; ;
; RAM2GS.mif ; yes ; Auto-Found Memory Initialization File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/RAM2GS.mif ; ;
; ram2gs.mif ; yes ; Auto-Found Memory Initialization File ; D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/ram2gs.mif ; ;
+----------------------------------+-----------------+----------------------------------------+----------------------------------------------------------+---------+
@ -270,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sun Aug 13 04:26:21 2023
Info: Processing started: Sun Aug 13 04:49:50 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
@ -302,7 +302,7 @@ Info (21057): Implemented 248 device resources after synthesis - the final resou
Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 4702 megabytes
Info: Processing ended: Sun Aug 13 04:26:30 2023
Info: Processing ended: Sun Aug 13 04:49:59 2023
Info: Elapsed time: 00:00:09
Info: Total CPU time (on all processors): 00:00:22

2
CPLD/MAXV/output_files/RAM2GS.map.summary
View File

@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Sun Aug 13 04:26:30 2023
Analysis & Synthesis Status : Successful - Sun Aug 13 04:49:59 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS

6
CPLD/MAXV/output_files/RAM2GS.sta.rpt
View File

@ -1,5 +1,5 @@
Timing Analyzer report for RAM2GS
Sun Aug 13 04:26:36 2023
Sun Aug 13 04:50:05 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
@ -948,7 +948,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sun Aug 13 04:26:35 2023
Info: Processing started: Sun Aug 13 04:50:04 2023
Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@ -1001,7 +1001,7 @@ Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 4676 megabytes
Info: Processing ended: Sun Aug 13 04:26:36 2023
Info: Processing ended: Sun Aug 13 04:50:05 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01