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RAM2GS
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Update RAM4GS-ExtSPI.v

This commit is contained in:
Zane Kaminski 2021-08-16 19:00:10 -04:00
parent 49f44f0b84
commit 3c767ecbad
1 changed files with 10 additions and 5 deletions
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15
CPLD/RAM4GS-ExtSPI.v
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@ -1,5 +1,5 @@
module RAM4GS(PHI2, MAin, CROW, Din, Dout, module RAM4GS(PHI2, MAin, CROW, Din, Dout,
nCCAS, nCRAS, nFWE, nCCAS, nCRAS, nFWE, LED,
RBA, RA, RD, nRCS, RCLK, RCKE, RBA, RA, RD, nRCS, RCLK, RCKE,
nRWE, nRRAS, nRCAS, RDQMH, RDQML, nRWE, nRRAS, nRCAS, RDQMH, RDQML,
nUFMCS, UFMCLK, UFMSDI, UFMSDO); nUFMCS, UFMCLK, UFMSDI, UFMSDO);
@ -7,6 +7,10 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
/* 65816 Phase 2 Clock */ /* 65816 Phase 2 Clock */
input PHI2; input PHI2;
/* Activity LED */
reg LEDEN = 0;
output LED = ~(~nCRAS && LEDEN);
/* Async. DRAM Control Inputs */ /* Async. DRAM Control Inputs */
input nCCAS, nCRAS; input nCCAS, nCRAS;
@ -363,13 +367,14 @@ module RAM4GS(PHI2, MAin, CROW, Din, Dout,
endcase endcase
end else if (~InitReady && FS[17:10]==8'h03) begin end else if (~InitReady && FS[17:10]==8'h03) begin
nUFMCS <= 1'b0; nUFMCS <= 1'b0;
UFMCLK <= 1'b0; UFMCLK <= FS[4];
UFMSDI <= 1'b0; UFMSDI <= 1'b0;
// Latch n8MEGEN // Latch n8MEGEN and LEDEN
if (FS[9:4]==6'h00 && FS[3:0]==4'hF) n8MEGEN <= ~UFMSDO; if (FS[9:5]==5'h00 && FS[4:0]==5'h1F) n8MEGEN <= ~UFMSDO;
if (FS[9:5]==5'h01 && FS[4:0]==5'h1F) LEDEN <= ~UFMSDO;
end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin
nUFMCS <= 1'b0; nUFMCS <= 1'b0;
UFMCLK <= FS[1]; UFMCLK <= FS[4];
UFMSDI <= 1'b0; UFMSDI <= 1'b0;
end else if (~InitReady) begin end else if (~InitReady) begin
nUFMCS <= 1'b1; nUFMCS <= 1'b1;