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MAX II and MAX V compiling?

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Zane Kaminski 2021-08-16 18:49:47 -04:00
parent cf456efea1
commit 49f44f0b84
248 changed files with 4495 additions and 4809 deletions
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485253603 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:53 2020 " "Processing started: Thu Jul 23 02:20:53 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485253603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485253603 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485254775 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485254806 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:55 2020 " "Processing ended: Thu Jul 23 02:20:55 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485255322 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485255322 ""}

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CPLD/AGM-src/db/RAM4GS.fit.qmsg
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595485244993 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595485245024 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595485245243 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595485245680 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595485245711 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595485246102 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595485246102 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595485246305 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595485246336 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595485246383 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595485246383 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595485246399 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595485246399 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246415 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595485246430 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246446 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246461 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246461 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595485246477 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595485246477 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595485246493 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595485246555 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595485246555 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246633 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595485246649 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595485246665 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595485246665 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485246712 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595485247071 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485247462 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595485247477 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595485248884 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485248899 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595485248946 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595485249462 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595485249462 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250243 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.53 " "Total time spent on timing analysis during the Fitter is 0.53 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485250259 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485250275 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485250290 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485250525 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "376 " "Peak virtual memory: 376 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:50 2020 " "Processing ended: Thu Jul 23 02:20:50 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485250759 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485250759 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485235413 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:35 2020 " "Processing started: Thu Jul 23 02:20:35 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485235413 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485237304 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595485237601 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237632 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595485237804 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595485237804 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595485238085 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595485238148 "|RAM4GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238195 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595485238320 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595485240304 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595485240523 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595485240523 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595485240523 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595485240929 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:20:41 2020 " "Processing ended: Thu Jul 23 02:20:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485241148 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595485258541 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:20:57 2020 " "Processing started: Thu Jul 23 02:20:57 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485258557 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485258573 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485258791 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485259791 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485260010 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485260260 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485260838 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485261042 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261057 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485261120 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485261260 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261292 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261323 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261339 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485261354 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485261370 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485261854 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485261995 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "288 " "Peak virtual memory: 288 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:21:02 2020 " "Processing ended: Thu Jul 23 02:21:02 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485262245 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484987367 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 32-bit " "Running Quartus II 32-bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:27 2020 " "Processing started: Thu Jul 23 02:16:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595484987383 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595484989226 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM4GS.v(52) " "Verilog HDL warning at RAM4GS.v(52): extended using \"x\" or \"z\"" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1595484989445 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram4gs.v 1 1 " "Found 1 design units, including 1 entities, in source file ram4gs.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM4GS " "Found entity 1: RAM4GS" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989476 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989617 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1595484989633 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_1br " "Found entity 1: UFM_altufm_none_1br" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1595484989633 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM4GS " "Elaborating entity \"RAM4GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1595484989805 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM4GS.v(154) " "Verilog HDL assignment warning at RAM4GS.v(154): truncated value with size 32 to match size of target (2)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 154 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM4GS.v(159) " "Verilog HDL assignment warning at RAM4GS.v(159): truncated value with size 32 to match size of target (18)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 159 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM4GS.v(286) " "Verilog HDL assignment warning at RAM4GS.v(286): truncated value with size 32 to match size of target (4)" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 286 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1595484989836 "|RAM4GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM4GS.v" "UFM_inst" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 83 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484989883 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_1br UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component " "Elaborating entity \"UFM_altufm_none_1br\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_1br:UFM_altufm_none_1br_component\"" { } { { "UFM.v" "UFM_altufm_none_1br_component" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1595484990008 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 21 -1 0 } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 52 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1595484991508 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_OPINS" "29 " "Implemented 29 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_LCELLS" "178 " "Implemented 178 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1595484991726 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1595484991726 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1595484991726 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1595484992133 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 32-bit " "Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "303 " "Peak virtual memory: 303 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:32 2020 " "Processing ended: Thu Jul 23 02:16:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595484992398 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1595484995336 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 32-bit " "Running Quartus II 32-bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:33 2020 " "Processing started: Thu Jul 23 02:16:33 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595484995351 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1595484995351 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1595484995367 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "0" "" "Project = RAM4GS" { } { } 0 0 "Project = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "0" "" "Revision = RAM4GS" { } { } 0 0 "Revision = RAM4GS" 0 0 "Fitter" 0 0 1595484995523 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1595484996148 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM4GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM4GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1595484996164 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1595484996367 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1595484996648 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1595484996679 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1595484996992 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1595484996992 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1595484997164 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1595484997179 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1595484997210 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1595484997210 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1595484997210 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997210 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1595484997226 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997226 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 34 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~2 " "Destination \"comb~2\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1595484997257 ""} } { { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "RAM4GS.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/RAM4GS.v" 10 -1 0 } } { "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1595484997257 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1595484997273 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1595484997320 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1595484997320 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997382 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1595484997398 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1595484997414 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1595484997414 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484997445 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1595484997742 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484998117 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1595484998132 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1595484999460 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595484999460 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1595484999507 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM4GS/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1595484999976 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1595484999976 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000632 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.50 " "Total time spent on timing analysis during the Fitter is 0.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1595485000663 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1595485000679 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1595485000742 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg " "Generated suppressed messages file /Repos/RAM4GS/cpld/output_files/RAM4GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1595485001117 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:41 2020 " "Processing ended: Thu Jul 23 02:16:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485001429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1595485001429 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1595485004085 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 32-bit " "Running Quartus II 32-bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:43 2020 " "Processing started: Thu Jul 23 02:16:43 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485004101 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1595485004101 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1595485005116 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1595485005148 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 32-bit " "Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "296 " "Peak virtual memory: 296 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:45 2020 " "Processing ended: Thu Jul 23 02:16:45 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485005632 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1595485005632 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1595485006413 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1595485008366 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 32-bit " "Running Quartus II 32-bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 23 02:16:47 2020 " "Processing started: Thu Jul 23 02:16:47 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1595485008398 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM4GS -c RAM4GS " "Command: quartus_sta RAM4GS -c RAM4GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1595485008413 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1595485008601 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1595485009444 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1595485009663 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1595485009898 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1595485010507 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1595485010726 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010757 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1595485010773 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1595485010851 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.292 -92.804 PHI2 " " -9.292 -92.804 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.365 -253.063 RCLK " " -8.365 -253.063 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.490 -0.577 nCRAS " " -0.490 -0.577 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010882 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.306 " "Worst-case hold slack is -16.306" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.306 -16.306 DRCLK " " -16.306 -16.306 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.272 -16.272 ARCLK " " -16.272 -16.272 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.874 -0.874 RCLK " " -0.874 -0.874 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.396 -0.396 PHI2 " " -0.396 -0.396 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.125 -0.125 nCRAS " " -0.125 -0.125 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010898 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010913 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1595485010929 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1595485010944 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1595485011241 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1595485011366 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 32-bit " "Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "277 " "Peak virtual memory: 277 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 23 02:16:51 2020 " "Processing ended: Thu Jul 23 02:16:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485011538 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus II Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1595485012647 ""}

26
CPLD/AGM-src/greybox_tmp/cbx_args.txt
View File

@ -1,26 +0,0 @@
ERASE_TIME=500000000
INTENDED_DEVICE_FAMILY="MAX II"
LPM_FILE=RAM4GS.mif
LPM_HINT=UNUSED
LPM_TYPE=altufm_none
OSC_FREQUENCY=180000
PORT_ARCLKENA=PORT_UNUSED
PORT_DRCLKENA=PORT_UNUSED
PROGRAM_TIME=1600000
WIDTH_UFM_ADDRESS=9
DEVICE_FAMILY="MAX II"
CBX_AUTO_BLACKBOX=ALL
CBX_AUTO_BLACKBOX=ALL
arclk
ardin
arshft
busy
drclk
drdin
drdout
drshft
erase
osc
oscena
program
rtpbusy

BIN
CPLD/AGM-src/incremental_db/compiled_partitions/RAM4GS.root_partition.map.kpt
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Binary file not shown.

13
CPLD/AGM-src/output_files/RAM4GS.cdf
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@ -1,13 +0,0 @@
/* Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPM240T100) Path("Z:/Repos/RAM4GS/cpld/output_files/") File("RAM4GS.pof") MfrSpec(OpMask(3) SEC_Device(EPM240T100) Child_OpMask(2 3 3));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1
CPLD/AGM-src/output_files/RAM4GS.done
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@ -1 +0,0 @@
Thu Jul 23 02:21:03 2020

11
CPLD/AGM-src/output_files/RAM4GS.fit.summary
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@ -1,11 +0,0 @@
Fitter Status : Successful - Thu Jul 23 02:20:50 2020
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM4GS
Top-level Entity Name : RAM4GS
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 170 / 240 ( 71 % )
Total pins : 62 / 80 ( 78 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

8
CPLD/AGM-src/output_files/RAM4GS.jdi
View File

@ -1,8 +0,0 @@
<sld_project_info>
<project>
<hash md5_digest_80b="6d7ef2df313eca11db51"/>
</project>
<file_info>
<file device="EPM240T100C5" path="RAM4GS.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

9
CPLD/AGM-src/output_files/RAM4GS.map.summary
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@ -1,9 +0,0 @@
Analysis & Synthesis Status : Successful - Thu Jul 23 02:20:40 2020
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM4GS
Top-level Entity Name : RAM4GS
Family : MAX II
Total logic elements : 178
Total pins : 62
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

BIN
CPLD/AGM-src/output_files/RAM4GS.pof
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1588
CPLD/AGM-src/output_files/RAM4GS.sta.rpt
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File diff suppressed because it is too large Load Diff

10
CPLD/AGM-src/RAM4GS.qpf → CPLD/MAX/MAXII/RAM2GS-MAXII.qpf Executable file → Normal file
View File

@ -16,15 +16,15 @@
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 21:16:34 March 08, 2020
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 18:32:31 August 16, 2021
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "21:16:34 March 08, 2020"
DATE = "18:32:31 August 16, 2021"
# Revisions
PROJECT_REVISION = "RAM4GS"
PROJECT_REVISION = "RAM2GS"

7
CPLD/MAXII/RAM4GS.qsf → CPLD/MAX/MAXII/RAM2GS.qsf Executable file → Normal file
View File

@ -38,12 +38,10 @@
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34 MARCH 08, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name SDC_FILE constraints.sdc
set_global_assignment -name VERILOG_FILE RAM4GS.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -174,7 +172,6 @@ set_location_assignment PIN_95 -to RD[6]
set_location_assignment PIN_97 -to RD[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
set_global_assignment -name MIF_FILE RAM4GS.mif
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
@ -210,4 +207,6 @@ set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_global_assignment -name VERILOG_FILE "../RAM2GS-MAX.v"
set_global_assignment -name MIF_FILE "../RAM2GS-MAX.mif"
set_global_assignment -name QIP_FILE UFM.qip

BIN
CPLD/MAX/MAXII/RAM2GS.qws Normal file
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0
CPLD/AGM-src/UFM.qip → CPLD/MAX/MAXII/UFM.qip Executable file → Normal file
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32
CPLD/MAXII/UFM.v → CPLD/MAX/MAXII/UFM.v Executable file → Normal file
View File

@ -33,8 +33,8 @@
//applicable agreement for further details.
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM4GS.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:39:SJ cbx_a_graycounter 2013:06:12:18:03:39:SJ cbx_altufm_none 2013:06:12:18:03:40:SJ cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_lpm_compare 2013:06:12:18:03:40:SJ cbx_lpm_counter 2013:06:12:18:03:40:SJ cbx_lpm_decode 2013:06:12:18:03:40:SJ cbx_lpm_mux 2013:06:12:18:03:40:SJ cbx_maxii 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ cbx_util_mgl 2013:06:12:18:03:40:SJ VERSION_END
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2GS-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
@ -43,7 +43,7 @@
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module UFM_altufm_none_1br
module UFM_altufm_none_imr
(
arclk,
ardin,
@ -117,23 +117,23 @@ module UFM_altufm_none_1br
defparam
maxii_ufm_block1.address_width = 9,
maxii_ufm_block1.erase_time = 500000000,
maxii_ufm_block1.init_file = "RAM4GS.mif",
maxii_ufm_block1.init_file = "RAM2GS-MAX.mif",
maxii_ufm_block1.mem1 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem10 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem11 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem12 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem13 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem14 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem15 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem16 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem2 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem3 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem4 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem5 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem6 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem7 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem8 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem9 = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem8 = 512'hFFFF7FFF000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000,
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
maxii_ufm_block1.lpm_type = "maxii_ufm";
@ -155,7 +155,7 @@ module UFM_altufm_none_1br
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
endmodule //UFM_altufm_none_1br
endmodule //UFM_altufm_none_imr
//VALID FILE
@ -200,7 +200,7 @@ module UFM (
wire drdout = sub_wire2;
wire busy = sub_wire3;
UFM_altufm_none_1br UFM_altufm_none_1br_component (
UFM_altufm_none_imr UFM_altufm_none_imr_component (
.arshft (arshft),
.drclk (drclk),
.erase (erase),
@ -224,7 +224,7 @@ endmodule
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: LPM_FILE STRING "RAM4GS.mif"
// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2GS-MAX.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"

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@ -0,0 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153617401 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153617401 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing started: Mon Aug 16 18:40:17 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153617401 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1629153617401 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1629153617401 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1629153617637 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1629153617652 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "381 " "Peak virtual memory: 381 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:17 2021 " "Processing ended: Mon Aug 16 18:40:17 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153617808 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1629153617808 ""}

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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Mon Jun 15 13:43:18 2020
Creation_Time = Mon Aug 16 18:36:28 2021

46
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@ -0,0 +1,46 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1629153614132 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1629153614132 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153614183 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1629153614183 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1629153614309 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1629153614325 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1629153614465 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1629153614465 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 63 " "No exact pin location assignment(s) for 1 pins of 63 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "LED " "Pin LED not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LED } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LED } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 336 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1629153614512 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1629153614512 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1629153614621 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1629153614621 ""}
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1629153614621 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1629153614621 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1629153614637 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1629153614637 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153614637 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1629153614637 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153614637 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 38 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 7 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PHI2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 332 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 18 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCRAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 334 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~3 " "Destination \"comb~3\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 19 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Quartus II" 0 -1 1629153614653 ""} } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 14 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { nCCAS } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 0 { 0 ""} 0 333 9224 9983 0} } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1629153614653 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1629153614668 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1629153614668 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1629153614699 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1629153614699 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1629153614699 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1629153614699 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1629153614715 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1629153614715 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1629153614715 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153614715 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 24 18 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1629153614715 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1629153614715 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1629153614715 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153614746 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1629153614887 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153615071 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1629153615085 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1629153615678 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153615678 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1629153615709 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1629153615943 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1629153615943 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153616286 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1629153616286 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1629153616302 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1629153616333 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1629153616395 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "548 " "Peak virtual memory: 548 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:16 2021 " "Processing ended: Mon Aug 16 18:40:16 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153616427 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1629153616427 ""}

21
CPLD/AGM-src/db/RAM4GS.hier_info → CPLD/MAX/MAXII/db/RAM2GS.hier_info Executable file → Normal file
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@ -1,4 +1,4 @@
|RAM4GS
|RAM2GS
PHI2 => Bank[0].CLK
PHI2 => Bank[1].CLK
PHI2 => Bank[2].CLK
@ -152,12 +152,14 @@ nCRAS => RowA[8].CLK
nCRAS => RowA[9].CLK
nCRAS => RBA[0]~reg0.CLK
nCRAS => RBA[1]~reg0.CLK
nCRAS => comb.IN1
nCRAS => RASr.DATAIN
nFWE => comb.IN1
nFWE => CMDWR.IN1
nFWE => ADWR.IN1
nFWE => C1WR.IN1
nFWE => FWEr.DATAIN
LED <= comb.DB_MAX_OUTPUT_PORT_TYPE
RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
@ -184,9 +186,10 @@ nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
RCLK => UFMProgram.CLK
RCLK => UFMErase.CLK
RCLK => UFMReqErase.CLK
RCLK => n8MEGEN.CLK
RCLK => LEDEN.CLK
RCLK => UFMInitDone.CLK
RCLK => UFMD.CLK
RCLK => n8MEGEN.CLK
RCLK => UFMD[15].CLK
RCLK => DRShift.CLK
RCLK => DRDIn.CLK
RCLK => DRCLK.CLK
@ -243,7 +246,7 @@ RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
|RAM4GS|UFM:UFM_inst
|RAM2GS|UFM:UFM_inst
arclk => arclk.IN1
ardin => ardin.IN1
arshft => arshft.IN1
@ -253,13 +256,13 @@ drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy
drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout
osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc
rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy
busy <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.busy
drdout <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.drdout
osc <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.osc
rtpbusy <= UFM_altufm_none_imr:UFM_altufm_none_imr_component.rtpbusy
|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component
|RAM2GS|UFM:UFM_inst|UFM_altufm_none_imr:UFM_altufm_none_imr_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT

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CPLD/MAX/MAXII/db/RAM2GS.hif Normal file
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CPLD/MAX/MAXII/db/RAM2GS.ipinfo Normal file
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2
CPLD/AGM-src/db/RAM4GS.lpc.html → CPLD/MAX/MAXII/db/RAM2GS.lpc.html Executable file → Normal file
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@ -16,7 +16,7 @@
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >UFM_inst|UFM_altufm_none_1br_component</TD>
<TD >UFM_inst|UFM_altufm_none_imr_component</TD>
<TD >9</TD>
<TD >0</TD>
<TD >0</TD>

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CPLD/MAX/MAXII/db/RAM2GS.lpc.rdb Normal file
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2
CPLD/AGM-src/db/RAM4GS.lpc.txt → CPLD/MAX/MAXII/db/RAM2GS.lpc.txt Executable file → Normal file
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@ -3,6 +3,6 @@
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; UFM_inst|UFM_altufm_none_1br_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst|UFM_altufm_none_imr_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst ; 9 ; 1 ; 0 ; 1 ; 4 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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CPLD/MAX/MAXII/db/RAM2GS.map.cdb Normal file
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CPLD/MAX/MAXII/db/RAM2GS.map.hdb Normal file
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0
CPLD/AGM-src/db/RAM4GS.map.logdb → CPLD/MAX/MAXII/db/RAM2GS.map.logdb Executable file → Normal file
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27
CPLD/MAX/MAXII/db/RAM2GS.map.qmsg Normal file
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@ -0,0 +1,27 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153611805 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:11 2021 " "Processing started: Mon Aug 16 18:40:11 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153611805 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153612070 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(56) " "Verilog HDL warning at RAM2GS-MAX.v(56): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1629153612117 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/dog/documents/github/ram2gs/cpld/max/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612117 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153612117 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153612179 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1629153612179 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_imr " "Found entity 1: UFM_altufm_none_imr" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1629153612179 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1629153612195 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(158) " "Verilog HDL assignment warning at RAM2GS-MAX.v(158): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 158 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(163) " "Verilog HDL assignment warning at RAM2GS-MAX.v(163): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 163 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(290) " "Verilog HDL assignment warning at RAM2GS-MAX.v(290): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 290 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1629153612210 "|RAM2GS"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 87 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153612257 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_imr UFM:UFM_inst\|UFM_altufm_none_imr:UFM_altufm_none_imr_component " "Elaborating entity \"UFM_altufm_none_imr\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_imr:UFM_altufm_none_imr_component\"" { } { { "UFM.v" "UFM_altufm_none_imr_component" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1629153612257 ""}
{ "Critical Warning" "WCDB_CDB_FILE_NOT_FOUND" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif " "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/RAM2GS-MAX.mif -- setting all initial values to 0" { } { } 1 127003 "Can't find Memory Initialization File or Hexadecimal (Intel-Format) File %1!s! -- setting all initial values to 0" 0 0 "Quartus II" 0 -1 1629153612257 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
{ "Warning" "WFTM_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 25 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/RAM2GS-MAX.v" 56 -1 0 } } } 0 18029 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Quartus II" 0 -1 1629153612725 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "241 " "Implemented 241 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_LCELLS" "177 " "Implemented 177 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1629153612865 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1629153612865 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1629153612865 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/MAX/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1629153612943 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "421 " "Peak virtual memory: 421 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:12 2021 " "Processing ended: Mon Aug 16 18:40:12 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153612959 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1629153618889 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 16 18:40:18 2021 " "Processing started: Mon Aug 16 18:40:18 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1629153618889 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1629153618967 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1629153619091 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153619138 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1629153619138 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1629153619201 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1629153619419 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1629153619466 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619466 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1629153619466 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1629153619481 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.339 -245.761 RCLK " " -8.339 -245.761 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.271 -88.383 PHI2 " " -8.271 -88.383 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.317 -2.784 nCRAS " " -0.317 -2.784 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.858 " "Worst-case hold slack is -16.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.858 -16.858 ARCLK " " -16.858 -16.858 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.363 -16.363 DRCLK " " -16.363 -16.363 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.103 -0.195 nCRAS " " -0.103 -0.195 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.060 -0.060 PHI2 " " -0.060 -0.060 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.192 0.000 RCLK " " 1.192 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153619481 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1629153619481 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1629153619481 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1629153619559 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153619575 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1629153619575 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "374 " "Peak virtual memory: 374 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 16 18:40:19 2021 " "Processing ended: Mon Aug 16 18:40:19 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1629153619622 ""}

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CPLD/MAX/MAXII/db/RAM2GS.sta.rdb Normal file
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CPLD/MAX/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb Normal file
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CPLD/AGM-src/constraints.sdc → CPLD/MAX/MAXII/db/RAM2GS.syn_hier_info Executable file → Normal file
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CPLD/MAX/MAXII/db/RAM2GS.tmw_info Normal file
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@ -0,0 +1,6 @@
start_full_compilation:s:00:00:09
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:04-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:02-start_full_compilation

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CPLD/MAX/MAXII/db/RAM2GS.vpr.ammdb Normal file
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