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RAM2GS
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Fixed wishbone bus

This commit is contained in:
Zane Kaminski 2023-08-17 03:38:57 -04:00
parent 8e3c43b7fc
commit 43e816b74c
2 changed files with 215 additions and 80 deletions
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137
CPLD/RAM2GS-LCMXO.lpf Normal file
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@ -0,0 +1,137 @@
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
IOBUF ALLPORTS PULLMODE=UP IO_TYPE=LVCMOS33 ;
IOBUF PORT "CROW[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=FAST ;
IOBUF PORT "CROW[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "PHI2" PULLMODE=DOWN IO_TYPE=LVCMOS33 ;
IOBUF PORT "RCLK" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "nCCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ;
IOBUF PORT "nCRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ;
IOBUF PORT "Din[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "Din[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "Din[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "Din[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "Din[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "Din[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "Din[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "Din[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[8]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "MAin[9]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "nFWE" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=14 OPENDRAIN=OFF ;
IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
LOCATE COMP "Dout[0]" SITE "1" ;
LOCATE COMP "Dout[6]" SITE "2" ;
LOCATE COMP "Dout[7]" SITE "3" ;
LOCATE COMP "Dout[4]" SITE "4" ;
LOCATE COMP "Dout[5]" SITE "5" ;
LOCATE COMP "Dout[1]" SITE "7" ;
LOCATE COMP "Dout[2]" SITE "8" ;
LOCATE COMP "Dout[3]" SITE "6" ;
LOCATE COMP "LED" SITE "57" ;
LOCATE COMP "RA[0]" SITE "98" ;
LOCATE COMP "RA[1]" SITE "89" ;
LOCATE COMP "RA[2]" SITE "94" ;
LOCATE COMP "RA[3]" SITE "97" ;
LOCATE COMP "RA[4]" SITE "99" ;
LOCATE COMP "RA[5]" SITE "95" ;
LOCATE COMP "RA[6]" SITE "91" ;
LOCATE COMP "RA[7]" SITE "100" ;
LOCATE COMP "RA[8]" SITE "96" ;
LOCATE COMP "RA[9]" SITE "85" ;
LOCATE COMP "RA[10]" SITE "87" ;
LOCATE COMP "RA[11]" SITE "79" ;
LOCATE COMP "RBA[0]" SITE "63" ;
LOCATE COMP "RBA[1]" SITE "83" ;
LOCATE COMP "RCKE" SITE "82" ;
LOCATE COMP "RDQMH" SITE "76" ;
LOCATE COMP "RDQML" SITE "61" ;
LOCATE COMP "UFMCLK" SITE "58" ;
LOCATE COMP "nUFMCS" SITE "53" ;
LOCATE COMP "nRWE" SITE "72" ;
LOCATE COMP "UFMSDI" SITE "56" ;
LOCATE COMP "nRCS" SITE "77" ;
LOCATE COMP "nRRAS" SITE "73" ;
LOCATE COMP "nRCAS" SITE "78" ;
LOCATE COMP "CROW[0]" SITE "32" ;
LOCATE COMP "CROW[1]" SITE "34" ;
LOCATE COMP "PHI2" SITE "39" ;
LOCATE COMP "nCRAS" SITE "43" ;
LOCATE COMP "RCLK" SITE "86" ;
LOCATE COMP "nCCAS" SITE "27" ;
LOCATE COMP "Din[0]" SITE "21" ;
LOCATE COMP "Din[1]" SITE "15" ;
LOCATE COMP "Din[2]" SITE "14" ;
LOCATE COMP "Din[3]" SITE "16" ;
LOCATE COMP "Din[4]" SITE "18" ;
LOCATE COMP "Din[5]" SITE "17" ;
LOCATE COMP "Din[6]" SITE "20" ;
LOCATE COMP "Din[7]" SITE "19" ;
LOCATE COMP "MAin[0]" SITE "23" ;
LOCATE COMP "MAin[1]" SITE "38" ;
LOCATE COMP "MAin[2]" SITE "37" ;
LOCATE COMP "MAin[3]" SITE "47" ;
LOCATE COMP "MAin[4]" SITE "46" ;
LOCATE COMP "MAin[5]" SITE "45" ;
LOCATE COMP "MAin[6]" SITE "49" ;
LOCATE COMP "MAin[7]" SITE "44" ;
LOCATE COMP "MAin[8]" SITE "50" ;
LOCATE COMP "MAin[9]" SITE "51" ;
LOCATE COMP "UFMSDO" SITE "55" ;
LOCATE COMP "nFWE" SITE "22" ;
LOCATE COMP "RD[0]" SITE "64" ;
LOCATE COMP "RD[1]" SITE "65" ;
LOCATE COMP "RD[2]" SITE "66" ;
LOCATE COMP "RD[3]" SITE "67" ;
LOCATE COMP "RD[4]" SITE "68" ;
LOCATE COMP "RD[5]" SITE "69" ;
LOCATE COMP "RD[6]" SITE "70" ;
LOCATE COMP "RD[7]" SITE "71" ;

158
CPLD/RAM2GS-LCMXO2.v
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@ -61,7 +61,6 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
/* UFM Interface */
reg wb_clk;
reg wb_rst;
reg wb_cyc_stb;
reg wb_we;
@ -71,7 +70,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
wire [7:0] wb_dato;
wire ufm_irq;
REFB ufmefb (
.wb_clk_i(wb_clk),
.wb_clk_i(RCLK),
.wb_rst_i(wb_rst),
.wb_cyc_i(wb_cyc_stb),
.wb_stb_i(wb_cyc_stb),
@ -85,7 +84,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
reg C1Submitted = 0;
reg ADSubmitted = 0;
reg CmdEnable = 0;
reg CmdSubmitted = 0;
reg CmdValid = 0;
reg Cmdn8MEGEN = 0;
reg CmdLEDEN = 0;
reg CmdUFMData = 0;
@ -326,75 +325,80 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
// if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
CmdValid <= 1'b0;
end else if (Din[7:4]==4'h0) begin // Unsupported type
XOR8MEG <= 0;
CmdValid <= 1'b0;
end else if (Din[7:4]==4'h1) begin
CmdLEDEN <= Din[1];
Cmdn8MEGEN <= ~Din[0];
CmdSubmitted <= 1'b1;
CmdUFMShift <= 1'b0;
CmdUFMWrite <= 1'b0;
CmdValid <= 1'b1;
end else if (Din[7:4]==4'h2) begin
// Reserved for MAX commands
CmdValid <= 1'b0;
end else if (Din[7:4]==4'h3 && !Din[3]) begin
// Reserved for SPI (LCMXO, iCE40) commands
// Din[2] - CS
// Din[1] - SCK
// Din[0] - SDI
CmdValid <= 1'b0;
end else if (Din[7:4]==4'h3 && Din[3]) begin
// LCMXO2 commands
// Din[1] - Shift when low, execute when high
// Din[0] - Shift data
CMDUFMWrite <= Din[1];
CmdUFMShift <= !Din[1];
CmdUFMWrite <= Din[1:0] == 2'b10;
CmdUFMData <= Din[0];
CmdLEDEN <= LEDEN;
Cmdn8MEGEN <= n8MEGEN;
CmdSubmitted <= 1'b1;
end
end
CmdValid <= 1'b1;
end else CmdValid <= 1'b0;
end else CmdValid <= 1'b0;
end
/* UFM Control */
always @(posedge RCLK) begin
if (~InitReady && FS[17:10]==8'h00) begin
wb_clk <= 1'b0;
wb_rst <= ~FS[9];
wb_cyc_stb <= 1'b0;
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h00;
wb_dati[7:0] <= 8'h00;
end else if (~InitReady && FS[17:10]==8'h01) begin
wb_clk <= FS[2];
wb_rst <= 1'b0;
case (FS[9:5])
5'h00: begin // Open frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h80;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h10;
end 5'h01: begin // Enable configuration interface - command
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h74;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h02: begin // Enable configuration interface - operand 1/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h08;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h03: begin // Enable configuration interface - operand 2/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h04: begin // Enable configuration interface - operand 3/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h1F: begin // Close frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end default: begin
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h00;
@ -403,59 +407,58 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
end
endcase
end else if (~InitReady && FS[17:10]==8'h02) begin
wb_clk <= FS[2];
wb_rst <= 1'b0;
case (FS[9:5])
5'h00: begin // Open frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h80;
wb_cyc_stb <= ~FS[4];
end 5'h01: begin // Poll status register - command
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h3C;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h02: begin // Poll status register - operand 1/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
end 5'h03: begin // Poll status register - operand 2/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h04: begin // Poll status register - operand 3/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
end 5'h05: begin // Read status register 1/4
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h73;
wb_dati[7:0] <= 8'h3C;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h06: begin // Read status register 2/4
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h73;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
end 5'h07: begin // Read status register 3/4
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h73;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h08: begin // Read status register 4/4
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h73;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
end 5'h1F: begin // Close frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end default: begin
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h00;
@ -464,59 +467,58 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
end
endcase
end else if (~InitReady && FS[17:10]==8'h03) begin
wb_clk <= FS[2];
wb_rst <= 1'b0;
case (FS[9:5])
5'h00: begin // Open frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h80;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h01: begin // Set UFM address - command
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'hB4;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h02: begin // Set UFM address - operand 1/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h03: begin // Set UFM address - operand 2/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h04: begin // Set UFM address - operand 3/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h05: begin // Set UFM address - data 1/4
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h40;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h06: begin // Set UFM address - data 2/4
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h07: begin // Set UFM address - data 3/4
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h08: begin // Set UFM address - data 4/4
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h01;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h1F: begin // Close frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end default: begin
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h00;
@ -525,41 +527,40 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
end
endcase
end else if (~InitReady && FS[17:10]==8'h04) begin
wb_clk <= FS[2];
wb_rst <= 1'b0;
case (FS[9:5])
5'h00: begin // Open frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h80;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h01: begin // Read UFM page - command
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'hCA;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h02: begin // Read UFM page - operand 1/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h10;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h03: begin // Read UFM page - operand 2/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h04: begin // Read UFM page - operand 3/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h01;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h05: begin // Read UFM page - data 1/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
if (FS[4:0]==5'h0C) begin
if (FS[4:0]==5'h1F) begin
LEDEN <= wb_dato[1];
n8MEGEN <= wb_dato[0];
end
@ -567,82 +568,82 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h07: begin // Read UFM page - data 3/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h08: begin // Read UFM page - data 4/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h09: begin // Read UFM page - data 5/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h0A: begin // Read UFM page - data 6/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h0B: begin // Read UFM page - data 7/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h0C: begin // Read UFM page - data 8/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h0D: begin // Read UFM page - data 9/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h0E: begin // Read UFM page - data 10/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h0F: begin // Read UFM page - data 11/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h10: begin // Read UFM page - data 12/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h11: begin // Read UFM page - data 13/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h12: begin // Read UFM page - data 14/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h13: begin // Read UFM page - data 15/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h14: begin // Read UFM page - data 16/16
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h1F: begin // Close frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end default: begin
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h00;
@ -651,34 +652,33 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
end
endcase
end else if (~InitReady && FS[17:10]==8'h05) begin
wb_clk <= FS[2];
wb_rst <= 1'b0;
case (FS[9:5])
5'h00: begin // Open frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h80;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h01: begin // Disable configuration interface - command
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h26;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h02: begin // Disable configuration interface - operand 1/2
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h03: begin // Disable configuration interface - operand 2/2
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h1F: begin // Close frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end default: begin
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h00;
@ -687,24 +687,23 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
end
endcase
end else if (~InitReady && FS[17:10]==8'h06) begin
wb_clk <= FS[2];
wb_rst <= 1'b0;
case (FS[9:5])
5'h00: begin // Open frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h80;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h01: begin // Disable configuration interface - command
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'hFF;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end 5'h1F: begin // Close frame
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h00;
wb_cyc_stb <= ~FS[4];
wb_cyc_stb <= FS[4:0]==5'h00;
end default: begin
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h00;
@ -713,23 +712,22 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
end
endcase
end else if (~InitReady) begin
wb_clk <= 1'b0;
wb_rst <= 1'b0;
wb_cyc_stb <= 1'b0;
wb_we <= 1'b0;
wb_adr[7:0] <= 8'h00;
wb_dati[7:0] <= 8'h00;
end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
end else if (~PHI2r2 & PHI2r3 & CmdValid) begin
wb_rst <= 1'b0;
// Set user command signals after PHI2 falls
LEDEN <= CmdLEDEN;
n8MEGEN <= Cmdn8MEGEN;
if (!CMDUFMWrite) begin
if (CmdUFMShift) begin
wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
wb_dati[7:0] <= { wb_dati[6:0], wb_we };
wb_we <= wb_cyc_stb;
wb_cyc_stb <= CmdUFMData;
wb_clk <= 1'b0;
end else wb_clk <= 1'b1;
end
wb_we <= CmdUFMData;
end
if (CmdUFMWrite) wb_cyc_stb <= 1;
end else wb_cyc_stb <= 0;
end
endmodule