Fixed wishbone bus
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8e3c43b7fc
commit
43e816b74c
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@ -0,0 +1,137 @@
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BLOCK RESETPATHS ;
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BLOCK ASYNCPATHS ;
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IOBUF ALLPORTS PULLMODE=UP IO_TYPE=LVCMOS33 ;
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IOBUF PORT "CROW[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=FAST ;
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IOBUF PORT "CROW[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "PHI2" PULLMODE=DOWN IO_TYPE=LVCMOS33 ;
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IOBUF PORT "RCLK" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "nCCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ;
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IOBUF PORT "nCRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Din[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Din[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Din[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Din[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Din[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Din[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Din[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Din[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[8]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "MAin[9]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "nFWE" PULLMODE=KEEPER IO_TYPE=LVCMOS33 ;
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IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
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IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
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IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
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IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
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IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
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IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
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IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
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IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=FAST DRIVE=4 ;
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IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=14 OPENDRAIN=OFF ;
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IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVCMOS33 SLEWRATE=SLOW DRIVE=4 ;
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LOCATE COMP "Dout[0]" SITE "1" ;
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LOCATE COMP "Dout[6]" SITE "2" ;
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LOCATE COMP "Dout[7]" SITE "3" ;
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LOCATE COMP "Dout[4]" SITE "4" ;
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LOCATE COMP "Dout[5]" SITE "5" ;
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LOCATE COMP "Dout[1]" SITE "7" ;
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LOCATE COMP "Dout[2]" SITE "8" ;
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LOCATE COMP "Dout[3]" SITE "6" ;
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LOCATE COMP "LED" SITE "57" ;
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LOCATE COMP "RA[0]" SITE "98" ;
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LOCATE COMP "RA[1]" SITE "89" ;
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LOCATE COMP "RA[2]" SITE "94" ;
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LOCATE COMP "RA[3]" SITE "97" ;
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LOCATE COMP "RA[4]" SITE "99" ;
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LOCATE COMP "RA[5]" SITE "95" ;
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LOCATE COMP "RA[6]" SITE "91" ;
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LOCATE COMP "RA[7]" SITE "100" ;
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LOCATE COMP "RA[8]" SITE "96" ;
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LOCATE COMP "RA[9]" SITE "85" ;
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LOCATE COMP "RA[10]" SITE "87" ;
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LOCATE COMP "RA[11]" SITE "79" ;
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LOCATE COMP "RBA[0]" SITE "63" ;
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LOCATE COMP "RBA[1]" SITE "83" ;
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LOCATE COMP "RCKE" SITE "82" ;
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LOCATE COMP "RDQMH" SITE "76" ;
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LOCATE COMP "RDQML" SITE "61" ;
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LOCATE COMP "UFMCLK" SITE "58" ;
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LOCATE COMP "nUFMCS" SITE "53" ;
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LOCATE COMP "nRWE" SITE "72" ;
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LOCATE COMP "UFMSDI" SITE "56" ;
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LOCATE COMP "nRCS" SITE "77" ;
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LOCATE COMP "nRRAS" SITE "73" ;
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LOCATE COMP "nRCAS" SITE "78" ;
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LOCATE COMP "CROW[0]" SITE "32" ;
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LOCATE COMP "CROW[1]" SITE "34" ;
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LOCATE COMP "PHI2" SITE "39" ;
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LOCATE COMP "nCRAS" SITE "43" ;
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LOCATE COMP "RCLK" SITE "86" ;
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LOCATE COMP "nCCAS" SITE "27" ;
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LOCATE COMP "Din[0]" SITE "21" ;
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LOCATE COMP "Din[1]" SITE "15" ;
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LOCATE COMP "Din[2]" SITE "14" ;
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LOCATE COMP "Din[3]" SITE "16" ;
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LOCATE COMP "Din[4]" SITE "18" ;
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LOCATE COMP "Din[5]" SITE "17" ;
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LOCATE COMP "Din[6]" SITE "20" ;
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LOCATE COMP "Din[7]" SITE "19" ;
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LOCATE COMP "MAin[0]" SITE "23" ;
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LOCATE COMP "MAin[1]" SITE "38" ;
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LOCATE COMP "MAin[2]" SITE "37" ;
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LOCATE COMP "MAin[3]" SITE "47" ;
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LOCATE COMP "MAin[4]" SITE "46" ;
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LOCATE COMP "MAin[5]" SITE "45" ;
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LOCATE COMP "MAin[6]" SITE "49" ;
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LOCATE COMP "MAin[7]" SITE "44" ;
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LOCATE COMP "MAin[8]" SITE "50" ;
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LOCATE COMP "MAin[9]" SITE "51" ;
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LOCATE COMP "UFMSDO" SITE "55" ;
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LOCATE COMP "nFWE" SITE "22" ;
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LOCATE COMP "RD[0]" SITE "64" ;
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LOCATE COMP "RD[1]" SITE "65" ;
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LOCATE COMP "RD[2]" SITE "66" ;
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LOCATE COMP "RD[3]" SITE "67" ;
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LOCATE COMP "RD[4]" SITE "68" ;
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LOCATE COMP "RD[5]" SITE "69" ;
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LOCATE COMP "RD[6]" SITE "70" ;
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LOCATE COMP "RD[7]" SITE "71" ;
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@ -61,7 +61,6 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
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assign RD[7:0] = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
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/* UFM Interface */
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reg wb_clk;
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reg wb_rst;
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reg wb_cyc_stb;
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reg wb_we;
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@ -71,7 +70,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
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wire [7:0] wb_dato;
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wire ufm_irq;
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REFB ufmefb (
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.wb_clk_i(wb_clk),
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.wb_clk_i(RCLK),
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.wb_rst_i(wb_rst),
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.wb_cyc_i(wb_cyc_stb),
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.wb_stb_i(wb_cyc_stb),
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@ -85,7 +84,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
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reg C1Submitted = 0;
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reg ADSubmitted = 0;
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reg CmdEnable = 0;
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reg CmdSubmitted = 0;
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reg CmdValid = 0;
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reg Cmdn8MEGEN = 0;
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reg CmdLEDEN = 0;
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reg CmdUFMData = 0;
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@ -326,75 +325,80 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
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// if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
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if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
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XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
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CmdValid <= 1'b0;
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end else if (Din[7:4]==4'h0) begin // Unsupported type
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XOR8MEG <= 0;
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CmdValid <= 1'b0;
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end else if (Din[7:4]==4'h1) begin
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CmdLEDEN <= Din[1];
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Cmdn8MEGEN <= ~Din[0];
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CmdSubmitted <= 1'b1;
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CmdUFMShift <= 1'b0;
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CmdUFMWrite <= 1'b0;
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CmdValid <= 1'b1;
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end else if (Din[7:4]==4'h2) begin
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// Reserved for MAX commands
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CmdValid <= 1'b0;
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end else if (Din[7:4]==4'h3 && !Din[3]) begin
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// Reserved for SPI (LCMXO, iCE40) commands
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// Din[2] - CS
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// Din[1] - SCK
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// Din[0] - SDI
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CmdValid <= 1'b0;
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end else if (Din[7:4]==4'h3 && Din[3]) begin
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// LCMXO2 commands
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// Din[1] - Shift when low, execute when high
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// Din[0] - Shift data
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CMDUFMWrite <= Din[1];
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CmdUFMShift <= !Din[1];
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CmdUFMWrite <= Din[1:0] == 2'b10;
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CmdUFMData <= Din[0];
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CmdLEDEN <= LEDEN;
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Cmdn8MEGEN <= n8MEGEN;
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CmdSubmitted <= 1'b1;
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end
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end
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CmdValid <= 1'b1;
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end else CmdValid <= 1'b0;
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end else CmdValid <= 1'b0;
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end
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/* UFM Control */
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always @(posedge RCLK) begin
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if (~InitReady && FS[17:10]==8'h00) begin
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wb_clk <= 1'b0;
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wb_rst <= ~FS[9];
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wb_cyc_stb <= 1'b0;
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h00;
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wb_dati[7:0] <= 8'h00;
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end else if (~InitReady && FS[17:10]==8'h01) begin
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wb_clk <= FS[2];
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wb_rst <= 1'b0;
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case (FS[9:5])
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5'h00: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h10;
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end 5'h01: begin // Enable configuration interface - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h74;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end 5'h02: begin // Enable configuration interface - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h08;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end 5'h03: begin // Enable configuration interface - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end 5'h04: begin // Enable configuration interface - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end 5'h1F: begin // Close frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end default: begin
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h00;
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@ -403,59 +407,58 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
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end
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endcase
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end else if (~InitReady && FS[17:10]==8'h02) begin
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wb_clk <= FS[2];
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wb_rst <= 1'b0;
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case (FS[9:5])
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5'h00: begin // Open frame
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h70;
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wb_dati[7:0] <= 8'h80;
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wb_cyc_stb <= ~FS[4];
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end 5'h01: begin // Poll status register - command
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h3C;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end 5'h02: begin // Poll status register - operand 1/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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end 5'h03: begin // Poll status register - operand 2/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end 5'h04: begin // Poll status register - operand 3/3
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wb_we <= 1'b1;
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wb_adr[7:0] <= 8'h71;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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end 5'h05: begin // Read status register 1/4
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h3C;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end 5'h06: begin // Read status register 2/4
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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end 5'h07: begin // Read status register 3/4
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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wb_cyc_stb <= FS[4:0]==5'h00;
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end 5'h08: begin // Read status register 4/4
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wb_we <= 1'b0;
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wb_adr[7:0] <= 8'h73;
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wb_dati[7:0] <= 8'h00;
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wb_cyc_stb <= ~FS[4];
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end 5'h1F: begin // Close frame
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wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end default: begin
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
|
@ -464,59 +467,58 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
endcase
|
||||
end else if (~InitReady && FS[17:10]==8'h03) begin
|
||||
wb_clk <= FS[2];
|
||||
wb_rst <= 1'b0;
|
||||
case (FS[9:5])
|
||||
5'h00: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h01: begin // Set UFM address - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hB4;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h02: begin // Set UFM address - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h03: begin // Set UFM address - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h04: begin // Set UFM address - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h05: begin // Set UFM address - data 1/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h40;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h06: begin // Set UFM address - data 2/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h07: begin // Set UFM address - data 3/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h08: begin // Set UFM address - data 4/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h01;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h1F: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end default: begin
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
|
@ -525,41 +527,40 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
endcase
|
||||
end else if (~InitReady && FS[17:10]==8'h04) begin
|
||||
wb_clk <= FS[2];
|
||||
wb_rst <= 1'b0;
|
||||
case (FS[9:5])
|
||||
5'h00: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h01: begin // Read UFM page - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hCA;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h02: begin // Read UFM page - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h10;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h03: begin // Read UFM page - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h04: begin // Read UFM page - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h01;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h05: begin // Read UFM page - data 1/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
|
||||
if (FS[4:0]==5'h0C) begin
|
||||
if (FS[4:0]==5'h1F) begin
|
||||
LEDEN <= wb_dato[1];
|
||||
n8MEGEN <= wb_dato[0];
|
||||
end
|
||||
|
@ -567,82 +568,82 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h07: begin // Read UFM page - data 3/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h08: begin // Read UFM page - data 4/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h09: begin // Read UFM page - data 5/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h0A: begin // Read UFM page - data 6/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h0B: begin // Read UFM page - data 7/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h0C: begin // Read UFM page - data 8/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h0D: begin // Read UFM page - data 9/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h0E: begin // Read UFM page - data 10/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h0F: begin // Read UFM page - data 11/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h10: begin // Read UFM page - data 12/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h11: begin // Read UFM page - data 13/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h12: begin // Read UFM page - data 14/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h13: begin // Read UFM page - data 15/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h14: begin // Read UFM page - data 16/16
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h1F: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end default: begin
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
|
@ -651,34 +652,33 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
endcase
|
||||
end else if (~InitReady && FS[17:10]==8'h05) begin
|
||||
wb_clk <= FS[2];
|
||||
wb_rst <= 1'b0;
|
||||
case (FS[9:5])
|
||||
5'h00: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h01: begin // Disable configuration interface - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h26;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h02: begin // Disable configuration interface - operand 1/2
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h03: begin // Disable configuration interface - operand 2/2
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h1F: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end default: begin
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
|
@ -687,24 +687,23 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
endcase
|
||||
end else if (~InitReady && FS[17:10]==8'h06) begin
|
||||
wb_clk <= FS[2];
|
||||
wb_rst <= 1'b0;
|
||||
case (FS[9:5])
|
||||
5'h00: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h01: begin // Disable configuration interface - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hFF;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end 5'h1F: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_cyc_stb <= ~FS[4];
|
||||
wb_cyc_stb <= FS[4:0]==5'h00;
|
||||
end default: begin
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
|
@ -713,23 +712,22 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
endcase
|
||||
end else if (~InitReady) begin
|
||||
wb_clk <= 1'b0;
|
||||
wb_rst <= 1'b0;
|
||||
wb_cyc_stb <= 1'b0;
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
|
||||
end else if (~PHI2r2 & PHI2r3 & CmdValid) begin
|
||||
wb_rst <= 1'b0;
|
||||
// Set user command signals after PHI2 falls
|
||||
LEDEN <= CmdLEDEN;
|
||||
n8MEGEN <= Cmdn8MEGEN;
|
||||
if (!CMDUFMWrite) begin
|
||||
if (CmdUFMShift) begin
|
||||
wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
|
||||
wb_dati[7:0] <= { wb_dati[6:0], wb_we };
|
||||
wb_we <= wb_cyc_stb;
|
||||
wb_cyc_stb <= CmdUFMData;
|
||||
wb_clk <= 1'b0;
|
||||
end else wb_clk <= 1'b1;
|
||||
wb_we <= CmdUFMData;
|
||||
end
|
||||
if (CmdUFMWrite) wb_cyc_stb <= 1;
|
||||
end else wb_cyc_stb <= 0;
|
||||
end
|
||||
endmodule
|
||||
|
|
Loading…
Reference in New Issue